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    2f721d17
    MXC: Fix byte-ordering in SPI driver for i.MX31/i.MX51 · 2f721d17
    Stefano Babic authored
    
    The actual SPI driver for i.MX31 and i.MX51 controller
    use a wrong byte ordering, because it is supposed
    to work only with Freescale's devices, as the Power
    Controllers (PMIC). The driver is not suitable for
    general purposes, because the buffers passed to spi_xfer
    must be 32-bit aligned, as it is used mainly to send
    integer to PMIC devices.
    
    The patch drops any kind of limitation and makes the
    driver useful with devices controlled sending commands
    composed by single bytes (or by a odd number of bytes), such as
    spi flash, sensor, etc.
    
    Because the byte ordering is changed,
    any current driver using this controller must be adapted, too.
    
    Signed-off-by: default avatarStefano Babic <sbabic@denx.de>
    2f721d17
    History
    MXC: Fix byte-ordering in SPI driver for i.MX31/i.MX51
    Stefano Babic authored
    
    The actual SPI driver for i.MX31 and i.MX51 controller
    use a wrong byte ordering, because it is supposed
    to work only with Freescale's devices, as the Power
    Controllers (PMIC). The driver is not suitable for
    general purposes, because the buffers passed to spi_xfer
    must be 32-bit aligned, as it is used mainly to send
    integer to PMIC devices.
    
    The patch drops any kind of limitation and makes the
    driver useful with devices controlled sending commands
    composed by single bytes (or by a odd number of bytes), such as
    spi flash, sensor, etc.
    
    Because the byte ordering is changed,
    any current driver using this controller must be adapted, too.
    
    Signed-off-by: default avatarStefano Babic <sbabic@denx.de>