ddr3_init.c

		break;
	case 11:
		return 14;
		break;
	case 12:
		return 1;
		break;
	case 13:
		return 3;
		break;
	case 14:
		return 5;
		break;
	default:
		return 2;
	}
}

/*
 * Name:     ddr3_cl_to_valid_cl - this return register matching CL value
 * Desc:
 * Args:     clValue - the value
 * Notes:
 * Returns:  required CL value
 */
u32 ddr3_valid_cl_to_cl(u32 ui_valid_cl)
{
	switch (ui_valid_cl) {
	case 1:
		return 12;
		break;
	case 2:
		return 5;
		break;
	case 3:
		return 13;
		break;
	case 4:
		return 6;
		break;
	case 5:
		return 14;
		break;
	case 6:
		return 7;
		break;
	case 8:
		return 8;
		break;
	case 10:
		return 9;
		break;
	case 12:
		return 10;
		break;
	case 14:
		return 11;
		break;
	default:
		return 0;
	}
}

/*
 * Name:     ddr3_get_cs_num_from_reg
 * Desc:
 * Args:
 * Notes:
 * Returns:
 */
u32 ddr3_get_cs_num_from_reg(void)
{
	u32 cs_ena = ddr3_get_cs_ena_from_reg();
	u32 cs_count = 0;
	u32 cs;

	for (cs = 0; cs < MAX_CS; cs++) {
		if (cs_ena & (1 << cs))
			cs_count++;
	}

	return cs_count;
}

/*
 * Name:     ddr3_get_cs_ena_from_reg
 * Desc:
 * Args:
 * Notes:
 * Returns:
 */
u32 ddr3_get_cs_ena_from_reg(void)
{
	return reg_read(REG_DDR3_RANK_CTRL_ADDR) &
		REG_DDR3_RANK_CTRL_CS_ENA_MASK;
}

/*
 * mv_ctrl_rev_get - Get Marvell controller device revision number
 *
 * DESCRIPTION:
 *       This function returns 8bit describing the device revision as defined
 *       in PCI Express Class Code and Revision ID Register.
 *
 * INPUT:
 *       None.
 *
 * OUTPUT:
 *       None.
 *
 * RETURN:
 *       8bit desscribing Marvell controller revision number
 *
 */
#if !defined(MV88F672X)
u8 mv_ctrl_rev_get(void)
{
	u8 rev_num;

#if defined(MV_INCLUDE_CLK_PWR_CNTRL)
	/* Check pex power state */
	u32 pex_power;
	pex_power = mv_ctrl_pwr_clck_get(PEX_UNIT_ID, 0);
	if (pex_power == 0)
		mv_ctrl_pwr_clck_set(PEX_UNIT_ID, 0, 1);
#endif
	rev_num = (u8)reg_read(PEX_CFG_DIRECT_ACCESS(0,
			PCI_CLASS_CODE_AND_REVISION_ID));

#if defined(MV_INCLUDE_CLK_PWR_CNTRL)
	/* Return to power off state */
	if (pex_power == 0)
		mv_ctrl_pwr_clck_set(PEX_UNIT_ID, 0, 0);
#endif

	return (rev_num & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS;
}

#endif

#if defined(MV88F672X)
void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps)
{
	u32 tmp, hclk;

	switch (freq_mode) {
	case CPU_333MHz_DDR_167MHz_L2_167MHz:
		hclk = 84;
		tmp = DDR_100;
		break;
	case CPU_266MHz_DDR_266MHz_L2_133MHz:
	case CPU_333MHz_DDR_222MHz_L2_167MHz:
	case CPU_400MHz_DDR_200MHz_L2_200MHz:
	case CPU_400MHz_DDR_267MHz_L2_200MHz:
	case CPU_533MHz_DDR_267MHz_L2_267MHz:
	case CPU_500MHz_DDR_250MHz_L2_250MHz:
	case CPU_600MHz_DDR_300MHz_L2_300MHz:
	case CPU_800MHz_DDR_267MHz_L2_400MHz:
	case CPU_900MHz_DDR_300MHz_L2_450MHz:
		tmp = DDR_300;
		hclk = 150;
		break;
	case CPU_333MHz_DDR_333MHz_L2_167MHz:
	case CPU_500MHz_DDR_334MHz_L2_250MHz:
	case CPU_666MHz_DDR_333MHz_L2_333MHz:
		tmp = DDR_333;
		hclk = 165;
		break;
	case CPU_533MHz_DDR_356MHz_L2_267MHz:
		tmp = DDR_360;
		hclk = 180;
		break;
	case CPU_400MHz_DDR_400MHz_L2_200MHz:
	case CPU_600MHz_DDR_400MHz_L2_300MHz:
	case CPU_800MHz_DDR_400MHz_L2_400MHz:
	case CPU_400MHz_DDR_400MHz_L2_400MHz:
		tmp = DDR_400;
		hclk = 200;
		break;
	case CPU_666MHz_DDR_444MHz_L2_333MHz:
	case CPU_900MHz_DDR_450MHz_L2_450MHz:
		tmp = DDR_444;
		hclk = 222;
		break;
	case CPU_500MHz_DDR_500MHz_L2_250MHz:
	case CPU_1000MHz_DDR_500MHz_L2_500MHz:
	case CPU_1000MHz_DDR_500MHz_L2_333MHz:
		tmp = DDR_500;
		hclk = 250;
		break;
	case CPU_533MHz_DDR_533MHz_L2_267MHz:
	case CPU_800MHz_DDR_534MHz_L2_400MHz:
	case CPU_1100MHz_DDR_550MHz_L2_550MHz:
		tmp = DDR_533;
		hclk = 267;
		break;
	case CPU_600MHz_DDR_600MHz_L2_300MHz:
	case CPU_900MHz_DDR_600MHz_L2_450MHz:
	case CPU_1200MHz_DDR_600MHz_L2_600MHz:
		tmp = DDR_600;
		hclk = 300;
		break;
	case CPU_666MHz_DDR_666MHz_L2_333MHz:
	case CPU_1000MHz_DDR_667MHz_L2_500MHz:
		tmp = DDR_666;
		hclk = 333;
		break;
	default:
		*ddr_freq = 0;
		*hclk_ps = 0;
		break;
	}

	*ddr_freq = tmp;		/* DDR freq define */
	*hclk_ps = 1000000 / hclk;	/* values are 1/HCLK in ps */

	return;
}
#endif