ddr3_hw_training.c

/*
 * Copyright (C) Marvell International Ltd. and its affiliates
 *
 * SPDX-License-Identifier:	GPL-2.0
 */

#include <common.h>
#include <i2c.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>

#include "ddr3_init.h"
#include "ddr3_hw_training.h"
#include "xor.h"

#ifdef MV88F78X60
#include "ddr3_patterns_64bit.h"
#else
#include "ddr3_patterns_16bit.h"
#if defined(MV88F672X)
#include "ddr3_patterns_16bit.h"
#endif
#endif

/*
 * Debug
 */

#define DEBUG_MAIN_C(s, d, l) \
	DEBUG_MAIN_S(s); DEBUG_MAIN_D(d, l); DEBUG_MAIN_S("\n")
#define DEBUG_MAIN_FULL_C(s, d, l) \
	DEBUG_MAIN_FULL_S(s); DEBUG_MAIN_FULL_D(d, l); DEBUG_MAIN_FULL_S("\n")

#ifdef MV_DEBUG_MAIN
#define DEBUG_MAIN_S(s)			puts(s)
#define DEBUG_MAIN_D(d, l)		printf("%x", d)
#else
#define DEBUG_MAIN_S(s)
#define DEBUG_MAIN_D(d, l)
#endif

#ifdef MV_DEBUG_MAIN_FULL
#define DEBUG_MAIN_FULL_S(s)		puts(s)
#define DEBUG_MAIN_FULL_D(d, l)		printf("%x", d)
#else
#define DEBUG_MAIN_FULL_S(s)
#define DEBUG_MAIN_FULL_D(d, l)
#endif

#ifdef MV_DEBUG_SUSPEND_RESUME
#define DEBUG_SUSPEND_RESUME_S(s)	puts(s)
#define DEBUG_SUSPEND_RESUME_D(d, l)	printf("%x", d)
#else
#define DEBUG_SUSPEND_RESUME_S(s)
#define DEBUG_SUSPEND_RESUME_D(d, l)
#endif

static u32 ddr3_sw_wl_rl_debug;
static u32 ddr3_run_pbs = 1;

void ddr3_print_version(void)
{
	puts("DDR3 Training Sequence - Ver 5.7.");
}

void ddr3_set_sw_wl_rl_debug(u32 val)
{
	ddr3_sw_wl_rl_debug = val;
}

void ddr3_set_pbs(u32 val)
{
	ddr3_run_pbs = val;
}

int ddr3_hw_training(u32 target_freq, u32 ddr_width, int xor_bypass,
		     u32 scrub_offs, u32 scrub_size, int dqs_clk_aligned,
		     int debug_mode, int reg_dimm_skip_wl)
{
	/* A370 has no PBS mechanism */
	__maybe_unused u32 first_loop_flag = 0;
	u32 freq, reg;
	MV_DRAM_INFO dram_info;
	int ratio_2to1 = 0;
	int tmp_ratio = 1;
	int status;

	if (debug_mode)
		DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 1\n");

	memset(&dram_info, 0, sizeof(dram_info));
	dram_info.num_cs = ddr3_get_cs_num_from_reg();
	dram_info.cs_ena = ddr3_get_cs_ena_from_reg();
	dram_info.target_frequency = target_freq;
	dram_info.ddr_width = ddr_width;
	dram_info.num_of_std_pups = ddr_width / PUP_SIZE;
	dram_info.rl400_bug = 0;
	dram_info.multi_cs_mr_support = 0;
#ifdef MV88F67XX
	dram_info.rl400_bug = 1;
#endif

	/* Ignore ECC errors - if ECC is enabled */
	reg = reg_read(REG_SDRAM_CONFIG_ADDR);
	if (reg & (1 << REG_SDRAM_CONFIG_ECC_OFFS)) {
		dram_info.ecc_ena = 1;
		reg |= (1 << REG_SDRAM_CONFIG_IERR_OFFS);
		reg_write(REG_SDRAM_CONFIG_ADDR, reg);
	} else {
		dram_info.ecc_ena = 0;
	}

	reg = reg_read(REG_SDRAM_CONFIG_ADDR);
	if (reg & (1 << REG_SDRAM_CONFIG_REGDIMM_OFFS))
		dram_info.reg_dimm = 1;
	else
		dram_info.reg_dimm = 0;

	dram_info.num_of_total_pups = ddr_width / PUP_SIZE + dram_info.ecc_ena;

	/* Get target 2T value */
	reg = reg_read(REG_DUNIT_CTRL_LOW_ADDR);
	dram_info.mode_2t = (reg >> REG_DUNIT_CTRL_LOW_2T_OFFS) &
		REG_DUNIT_CTRL_LOW_2T_MASK;

	/* Get target CL value */
#ifdef MV88F67XX
	reg = reg_read(REG_DDR3_MR0_ADDR) >> 2;
#else
	reg = reg_read(REG_DDR3_MR0_CS_ADDR) >> 2;
#endif

	reg = (((reg >> 1) & 0xE) | (reg & 0x1)) & 0xF;
	dram_info.cl = ddr3_valid_cl_to_cl(reg);

	/* Get target CWL value */
#ifdef MV88F67XX
	reg = reg_read(REG_DDR3_MR2_ADDR) >> REG_DDR3_MR2_CWL_OFFS;
#else
	reg = reg_read(REG_DDR3_MR2_CS_ADDR) >> REG_DDR3_MR2_CWL_OFFS;
#endif

	reg &= REG_DDR3_MR2_CWL_MASK;
	dram_info.cwl = reg;
#if !defined(MV88F67XX)
	/* A370 has no PBS mechanism */
#if defined(MV88F78X60)
	if ((dram_info.target_frequency > DDR_400) && (ddr3_run_pbs))
		first_loop_flag = 1;
#else
	/* first_loop_flag = 1; skip mid freq at ALP/A375 */
	if ((dram_info.target_frequency > DDR_400) && (ddr3_run_pbs) &&
	    (mv_ctrl_revision_get() >= UMC_A0))
		first_loop_flag = 1;
	else
		first_loop_flag = 0;
#endif
#endif

	freq = dram_info.target_frequency;

	/* Set ODT to always on */
	ddr3_odt_activate(1);

	/* Init XOR */
	mv_sys_xor_init(&dram_info);

	/* Get DRAM/HCLK ratio */
	if (reg_read(REG_DDR_IO_ADDR) & (1 << REG_DDR_IO_CLK_RATIO_OFFS))
		ratio_2to1 = 1;

	/*
	 * Xor Bypass - ECC support in AXP is currently available for 1:1
	 * modes frequency modes.
	 * Not all frequency modes support the ddr3 training sequence
	 * (Only 1200/300).
	 * Xor Bypass allows using the Xor initializations and scrubbing
	 * inside the ddr3 training sequence without running the training
	 * itself.
	 */
	if (xor_bypass == 0) {
		if (ddr3_run_pbs) {
			DEBUG_MAIN_S("DDR3 Training Sequence - Run with PBS.\n");
		} else {
			DEBUG_MAIN_S("DDR3 Training Sequence - Run without PBS.\n");
		}

		if (dram_info.target_frequency > DFS_MARGIN) {
			tmp_ratio = 0;
			freq = DDR_100;

			if (dram_info.reg_dimm == 1)
				freq = DDR_300;

			if (MV_OK != ddr3_dfs_high_2_low(freq, &dram_info)) {
				/* Set low - 100Mhz DDR Frequency by HW */
				DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Dfs High2Low)\n");
				return MV_DDR3_TRAINING_ERR_DFS_H2L;