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    #define PD_MII_RX_ERR	((ushort)0x0100)	/* PD  7 */
#define PD_MII_RX_CLK	((ushort)0x0080)	/* PD  8 */
#define PD_MII_TXD0	((ushort)0x0040)	/* PD  9 */
#define PD_MII_RXD0	((ushort)0x0020)	/* PD 10 */
#define PD_MII_TX_ERR	((ushort)0x0010)	/* PD 11 */
#define PD_MII_MDC	((ushort)0x0008)	/* PD 12 */
#define PD_MII_RXD1	((ushort)0x0004)	/* PD 13 */
#define PD_MII_RXD2	((ushort)0x0002)	/* PD 14 */
#define PD_MII_RXD3	((ushort)0x0001)	/* PD 15 */

#define PD_MII_MASK	((ushort)0x1FFF)	/* PD 3...15 */

#endif	/* CONFIG_KUP4K */
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    /***  LANTEC  *********************************************************/

#if defined(CONFIG_LANTEC) && CONFIG_LANTEC >= 2
/* Bits in parallel I/O port registers that have to be set/cleared
 * to configure the pins for SCC2 use.
 */
#define	PROFF_ENET	PROFF_SCC2
#define	CPM_CR_ENET	CPM_CR_CH_SCC2
#define	SCC_ENET	1
#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
#define PA_ENET_RCLK	((ushort)0x0200)	/* PA  6 */
#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */

#define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */

#define PC_ENET_LBK	((ushort)0x0010)	/* PC 11 */
#define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
#define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */

/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
 * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
 */
#define SICR_ENET_MASK	((uint)0x0000FF00)
#define SICR_ENET_CLKRT	((uint)0x00002E00)
#endif	/* CONFIG_LANTEC v2 */

/***  LWMON  **********************************************************/
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    #if defined(CONFIG_LWMON)
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    /* Bits in parallel I/O port registers that have to be set/cleared
 * to configure the pins for SCC2 use.
 */
#define	PROFF_ENET	PROFF_SCC2
#define	CPM_CR_ENET	CPM_CR_CH_SCC2
#define	SCC_ENET	1
#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
#define PA_ENET_RCLK	((ushort)0x0800)	/* PA  4 */
#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */

#define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */

#define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
#define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */

/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK4) to
 * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
 */
#define SICR_ENET_MASK	((uint)0x0000ff00)
#define SICR_ENET_CLKRT	((uint)0x00003E00)
#endif	/* CONFIG_LWMON */

/***  NX823  ***********************************************/

#if defined(CONFIG_NX823)
/* Bits in parallel I/O port registers that have to be set/cleared
 * to configure the pins for SCC1 use.
 */
#define PROFF_ENET	PROFF_SCC2
#define CPM_CR_ENET	CPM_CR_CH_SCC2
#define SCC_ENET	1
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    #define PA_ENET_RXD	((ushort)0x0004)  /* PA 13 */
#define PA_ENET_TXD	((ushort)0x0008)  /* PA 12 */
#define PA_ENET_RCLK	((ushort)0x0200)  /* PA  6 */
#define PA_ENET_TCLK	((ushort)0x0800)  /* PA  4 */
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    #define PB_ENET_TENA	((uint)0x00002000)   /* PB 18 */
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    #define PC_ENET_CLSN	((ushort)0x0040)  /* PC  9 */
#define PC_ENET_RENA	((ushort)0x0080)  /* PC  8 */
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/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
 * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
 */
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    #define SICR_ENET_MASK	((uint)0x0000ff00)
#define SICR_ENET_CLKRT	((uint)0x00002f00)
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#endif   /* CONFIG_NX823 */

/***  MBX  ************************************************************/

#ifdef CONFIG_MBX
/* Bits in parallel I/O port registers that have to be set/cleared
 * to configure the pins for SCC1 use.  The TCLK and RCLK seem unique
 * to the MBX860 board.  Any two of the four available clocks could be
 * used, and the MPC860 cookbook manual has an example using different
 * clock pins.
 */
#define	PROFF_ENET	PROFF_SCC1
#define	CPM_CR_ENET	CPM_CR_CH_SCC1
#define	SCC_ENET	0
#define PA_ENET_RXD	((ushort)0x0001)
#define PA_ENET_TXD	((ushort)0x0002)
#define PA_ENET_TCLK	((ushort)0x0200)
#define PA_ENET_RCLK	((ushort)0x0800)
#define PC_ENET_TENA	((ushort)0x0001)
#define PC_ENET_CLSN	((ushort)0x0010)
#define PC_ENET_RENA	((ushort)0x0020)

/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
 * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
 */
#define SICR_ENET_MASK	((uint)0x000000ff)
#define SICR_ENET_CLKRT	((uint)0x0000003d)
#endif	/* CONFIG_MBX */

/***  MHPC  ********************************************************/

#if defined(CONFIG_MHPC)
/* This ENET stuff is for the MHPC with ethernet on SCC2.
 * Note TENA is on Port B.
 */
#define	PROFF_ENET	PROFF_SCC2
#define	CPM_CR_ENET	CPM_CR_CH_SCC2
#define	SCC_ENET	1
#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
#define PA_ENET_RCLK	((ushort)0x0200)	/* PA 6 */
#define PA_ENET_TCLK	((ushort)0x0400)	/* PA 5 */
#define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */
#define PC_ENET_CLSN	((ushort)0x0040)	/* PC 9 */
#define PC_ENET_RENA	((ushort)0x0080)	/* PC 8 */

#define SICR_ENET_MASK	((uint)0x0000ff00)
#define SICR_ENET_CLKRT	((uint)0x00002e00)	/* RCLK-CLK2, TCLK-CLK3 */
#endif	/* CONFIG_MHPC */
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    /***  NETVIA  *******************************************************/
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    /* SinoVee Microsystems SC8xx series FEL8xx-AT,SC823,SC850,SC855T,SC860T */
#if ( defined CONFIG_SVM_SC8xx )
# ifndef CONFIG_FEC_ENET

#define PROFF_ENET      PROFF_SCC2
#define CPM_CR_ENET     CPM_CR_CH_SCC2
#define SCC_ENET        1

	/* Bits in parallel I/O port registers that have to be set/cleared
	 *  *  *  * to configure the pins for SCC2 use.
	 *   *   *   */
#define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
#define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
#define PA_ENET_RCLK    ((ushort)0x0400)        /* PA  5 */
#define PA_ENET_TCLK    ((ushort)0x0800)        /* PA  4 */

#define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */

#define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
#define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
 *  *  *  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
 *   *   *   */
#define SICR_ENET_MASK  ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00003700)

# else                          /* Use FEC for Fast Ethernet */

#undef  SCC_ENET
#define FEC_ENET

#define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3 */
#define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4 */
#define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5 */
#define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6 */
#define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7 */
#define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8 */
#define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9 */
#define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10 */
#define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11 */
#define PD_MII_MDC      ((ushort)0x0008)        /* PD 12 */
#define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13 */
#define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14 */
#define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15 */

#define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3...15 */

# endif /* CONFIG_FEC_ENET */
#endif  /* CONFIG_SVM_SC8xx */
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    #if defined(CONFIG_NETVIA)
/* Bits in parallel I/O port registers that have to be set/cleared
 * to configure the pins for SCC2 use.
 */
#define	PROFF_ENET	PROFF_SCC2
#define	CPM_CR_ENET	CPM_CR_CH_SCC2
#define	SCC_ENET	1
#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
#define PA_ENET_RCLK	((ushort)0x0200)	/* PA  6 */
#define PA_ENET_TCLK	((ushort)0x0800)	/* PA  4 */
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    #if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
# define PB_ENET_PDN	((ushort)0x4000)	/* PB 17 */
#elif CONFIG_NETVIA_VERSION >= 2
# define PC_ENET_PDN	((ushort)0x0008)	/* PC 12 */
#endif
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    #define PB_ENET_TENA	((ushort)0x2000)	/* PB 18 */

#define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
#define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */

/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
 * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
 */
#define SICR_ENET_MASK	((uint)0x0000ff00)
#define SICR_ENET_CLKRT	((uint)0x00002f00)

#endif	/* CONFIG_NETVIA */
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    /***  QS850/QS823  ***************************************************/

#if defined(CONFIG_QS850) || defined(CONFIG_QS823)
#undef FEC_ENET /* Don't use FEC for EThernet */

#define PROFF_ENET		PROFF_SCC2
#define CPM_CR_ENET		CPM_CR_CH_SCC2
#define SCC_ENET		1

#define PA_ENET_RXD		((ushort)0x0004)  /* RXD on PA13 (Pin D9) */
#define PA_ENET_TXD		((ushort)0x0008)  /* TXD on PA12 (Pin D7) */
#define PC_ENET_RENA		((ushort)0x0080)  /* RENA on PC8 (Pin D12) */
#define PC_ENET_CLSN		((ushort)0x0040)  /* CLSN on PC9 (Pin C12) */
#define PA_ENET_TCLK		((ushort)0x0200)  /* TCLK on PA6 (Pin D8) */
#define PA_ENET_RCLK		((ushort)0x0800)  /* RCLK on PA4 (Pin D10) */
#define PB_ENET_TENA		((uint)0x00002000)  /* TENA on PB18 (Pin D11) */
#define PC_ENET_LBK		((ushort)0x0010)  /* Loopback control on PC11 (Pin B14) */
#define PC_ENET_LI		((ushort)0x0020)  /* Link Integrity control PC10 (A15) */
#define PC_ENET_SQE		((ushort)0x0100)  /* SQE Disable control PC7 (B15) */

/* SCC2 TXCLK from CLK2
 * SCC2 RXCLK from CLK4
 * SCC2 Connected to NMSI */
#define SICR_ENET_MASK		((uint)0x00007F00)
#define SICR_ENET_CLKRT		((uint)0x00003D00)

#endif /* CONFIG_QS850/QS823 */

/***  QS860T  ***************************************************/

#ifdef CONFIG_QS860T
#ifdef CONFIG_FEC_ENET
#define FEC_ENET /* use FEC for EThernet */
#endif /* CONFIG_FEC_ETHERNET */

/* This ENET stuff is for GTH 10 Mbit ( SCC ) */
#define PROFF_ENET		PROFF_SCC1
#define CPM_CR_ENET		CPM_CR_CH_SCC1
#define SCC_ENET		0

#define PA_ENET_RXD		((ushort)0x0001) /* PA15 */
#define PA_ENET_TXD		((ushort)0x0002) /* PA14 */
#define PA_ENET_TCLK		((ushort)0x0800) /* PA4 */
#define PA_ENET_RCLK		((ushort)0x0200) /* PA6 */
#define PB_ENET_TENA		((uint)0x00001000) /* PB19 */
#define PC_ENET_CLSN		((ushort)0x0010) /* PC11 */
#define PC_ENET_RENA		((ushort)0x0020) /* PC10 */

#define SICR_ENET_MASK		((uint)0x000000ff)
/* RCLK PA4 -->CLK4, TCLK PA6 -->CLK2 */
#define SICR_ENET_CLKRT		((uint)0x0000003D)

#endif /* CONFIG_QS860T */
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    /***  RPXCLASSIC  *****************************************************/

#ifdef CONFIG_RPXCLASSIC

#ifdef CONFIG_FEC_ENET

# define FEC_ENET				/* use FEC for EThernet */
# undef SCC_ENET

#else	/* ! CONFIG_FEC_ENET */

/* Bits in parallel I/O port registers that have to be set/cleared
 * to configure the pins for SCC1 use.
 */
#define	PROFF_ENET	PROFF_SCC1
#define	CPM_CR_ENET	CPM_CR_CH_SCC1
#define	SCC_ENET	0
#define PA_ENET_RXD	((ushort)0x0001)
#define PA_ENET_TXD	((ushort)0x0002)
#define PA_ENET_TCLK	((ushort)0x0200)
#define PA_ENET_RCLK	((ushort)0x0800)
#define PB_ENET_TENA	((uint)0x00001000)
#define PC_ENET_CLSN	((ushort)0x0010)
#define PC_ENET_RENA	((ushort)0x0020)

/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
 * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
 */
#define SICR_ENET_MASK	((uint)0x000000ff)
#define SICR_ENET_CLKRT	((uint)0x0000003d)

#endif	/* CONFIG_FEC_ENET */

#endif	/* CONFIG_RPXCLASSIC */

/***  RPXLITE  ********************************************************/

#ifdef CONFIG_RPXLITE
/* This ENET stuff is for the MPC850 with ethernet on SCC2.  Some of
 * this may be unique to the RPX-Lite configuration.
 * Note TENA is on Port B.
 */
#define	PROFF_ENET	PROFF_SCC2
#define	CPM_CR_ENET	CPM_CR_CH_SCC2
#define	SCC_ENET	1
#define PA_ENET_RXD	((ushort)0x0004)
#define PA_ENET_TXD	((ushort)0x0008)
#define PA_ENET_TCLK	((ushort)0x0200)
#define PA_ENET_RCLK	((ushort)0x0800)
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    #if defined(CONFIG_RMU)
#define PC_ENET_TENA	((uint)0x00000002)	/* PC14 */
#else
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    #define PB_ENET_TENA	((uint)0x00002000)
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    #endif
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    #define PC_ENET_CLSN	((ushort)0x0040)
#define PC_ENET_RENA	((ushort)0x0080)

#define SICR_ENET_MASK	((uint)0x0000ff00)
#define SICR_ENET_CLKRT	((uint)0x00003d00)
#endif	/* CONFIG_RPXLITE */

/***  SM850  *********************************************************/

/* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */

#ifdef CONFIG_SM850
#define PROFF_ENET	PROFF_SCC3		/* Ethernet on SCC3 */
#define CPM_CR_ENET	CPM_CR_CH_SCC3
#define SCC_ENET	2
#define PB_ENET_RXD	((uint)0x00000004)	/* PB 29 */
#define PB_ENET_TXD	((uint)0x00000002)	/* PB 30 */
#define PA_ENET_RCLK	((ushort)0x0100)	/* PA  7 */
#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */

#define PC_ENET_LBK	((ushort)0x0008)	/* PC 12 */
#define PC_ENET_TENA	((ushort)0x0004)	/* PC 13 */

#define PC_ENET_RENA	((ushort)0x0800)	/* PC  4 */
#define PC_ENET_CLSN	((ushort)0x0400)	/* PC  5 */

/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
 * SCC3.  Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
 */
#define SICR_ENET_MASK	((uint)0x00FF0000)
#define SICR_ENET_CLKRT	((uint)0x00260000)
#endif	/* CONFIG_SM850 */

/***  SPD823TS  ******************************************************/

#ifdef CONFIG_SPD823TS
/* Bits in parallel I/O port registers that have to be set/cleared
 * to configure the pins for SCC2 use.
 */
#define	PROFF_ENET	PROFF_SCC2		/* Ethernet on SCC2 */
#define CPM_CR_ENET     CPM_CR_CH_SCC2
#define	SCC_ENET	1
#define PA_ENET_MDC	((ushort)0x0001)	/* PA 15 !!! */
#define PA_ENET_MDIO	((ushort)0x0002)	/* PA 14 !!! */
#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
#define PA_ENET_RCLK	((ushort)0x0200)	/* PA  6 */
#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */

#define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */

#define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
#define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */
#define	PC_ENET_RESET	((ushort)0x0100)	/* PC  7 !!! */

/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
 * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
 */
#define SICR_ENET_MASK	((uint)0x0000ff00)
#define SICR_ENET_CLKRT	((uint)0x00002E00)
#endif	/* CONFIG_SPD823TS */

/***  SXNI855T  ******************************************************/

#if defined(CONFIG_SXNI855T)

#ifdef CONFIG_FEC_ENET
#define	FEC_ENET	/* use FEC for Ethernet */
#endif	/* CONFIG_FEC_ETHERNET */

#endif	/* CONFIG_SXNI855T */
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    /***  MVS1, TQM823L/M, TQM850L/M, ETX094, R360MPI  *******************/
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#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
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        defined(CONFIG_R360MPI) || defined(CONFIG_RBC823)  || \
    defined(CONFIG_TQM823L) || defined(CONFIG_TQM823M) || \
    defined(CONFIG_TQM850L) || defined(CONFIG_TQM850M) || \
    defined(CONFIG_ETX094)  || defined(CONFIG_RRVISION)|| \
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        defined(CONFIG_VIRTLAB2)||				  \
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       (defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2)
/* Bits in parallel I/O port registers that have to be set/cleared
 * to configure the pins for SCC2 use.
 */
#define	PROFF_ENET	PROFF_SCC2
#define	CPM_CR_ENET	CPM_CR_CH_SCC2
#define	SCC_ENET	1
#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
#define PA_ENET_RCLK	((ushort)0x0100)	/* PA  7 */
#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */

#define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */

#define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
#define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */
#if defined(CONFIG_R360MPI)
#define PC_ENET_LBK	((ushort)0x0008)	/* PC 12 */
#endif   /* CONFIG_R360MPI */

/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
 * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
 */
#define SICR_ENET_MASK	((uint)0x0000ff00)
#define SICR_ENET_CLKRT	((uint)0x00002600)
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    #endif	/* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */
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    /***  TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M  *********************/
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    #if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \
    defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \
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        defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \
    defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M)
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# ifdef CONFIG_SCC1_ENET	/* use SCC for 10Mbps Ethernet	*/

/* Bits in parallel I/O port registers that have to be set/cleared
 * to configure the pins for SCC1 use.
 */
#define	PROFF_ENET	PROFF_SCC1
#define	CPM_CR_ENET	CPM_CR_CH_SCC1
#define	SCC_ENET	0
#define PA_ENET_RXD	((ushort)0x0001)	/* PA 15 */
#define PA_ENET_TXD	((ushort)0x0002)	/* PA 14 */
#define PA_ENET_RCLK	((ushort)0x0100)	/* PA  7 */
#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */

#define PC_ENET_TENA	((ushort)0x0001)	/* PC 15 */
#define PC_ENET_CLSN	((ushort)0x0010)	/* PC 11 */
#define PC_ENET_RENA	((ushort)0x0020)	/* PC 10 */

/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
 * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
 */
#define SICR_ENET_MASK	((uint)0x000000ff)
#define SICR_ENET_CLKRT	((uint)0x00000026)

# endif	/* CONFIG_SCC1_ENET */

# ifdef CONFIG_FEC_ENET		/* Use FEC for Fast Ethernet */

#define FEC_ENET

#define PD_MII_TXD1	((ushort)0x1000)	/* PD  3 */
#define PD_MII_TXD2	((ushort)0x0800)	/* PD  4 */
#define PD_MII_TXD3	((ushort)0x0400)	/* PD  5 */
#define PD_MII_RX_DV	((ushort)0x0200)	/* PD  6 */
#define PD_MII_RX_ERR	((ushort)0x0100)	/* PD  7 */
#define PD_MII_RX_CLK	((ushort)0x0080)	/* PD  8 */
#define PD_MII_TXD0	((ushort)0x0040)	/* PD  9 */
#define PD_MII_RXD0	((ushort)0x0020)	/* PD 10 */
#define PD_MII_TX_ERR	((ushort)0x0010)	/* PD 11 */
#define PD_MII_MDC	((ushort)0x0008)	/* PD 12 */
#define PD_MII_RXD1	((ushort)0x0004)	/* PD 13 */
#define PD_MII_RXD2	((ushort)0x0002)	/* PD 14 */
#define PD_MII_RXD3	((ushort)0x0001)	/* PD 15 */

#define PD_MII_MASK	((ushort)0x1FFF)	/* PD 3...15 */

# endif	/* CONFIG_FEC_ENET */
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    #endif	/* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */
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    /***  V37  **********************************************************/

#ifdef CONFIG_V37
/* This ENET stuff is for the MPC823 with ethernet on SCC2.  Some of
 * this may be unique to the Marel V37 configuration.
 * Note TENA is on Port B.
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     */
#define	PROFF_ENET	PROFF_SCC2
#define	CPM_CR_ENET	CPM_CR_CH_SCC2
#define	SCC_ENET	1
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    #define PA_ENET_RXD	((ushort)0x0004)
#define PA_ENET_TXD	((ushort)0x0008)
#define PA_ENET_TCLK	((ushort)0x0400)
#define PA_ENET_RCLK	((ushort)0x0200)
#define PB_ENET_TENA	((uint)0x00002000)
#define PC_ENET_CLSN	((ushort)0x0040)
#define PC_ENET_RENA	((ushort)0x0080)
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#define SICR_ENET_MASK	((uint)0x0000ff00)
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    #define SICR_ENET_CLKRT	((uint)0x00002e00)
#endif	/* CONFIG_V37 */
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    /*********************************************************************/

/* SCC Event register as used by Ethernet.
*/
#define SCCE_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
#define SCCE_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
#define SCCE_ENET_RXF	((ushort)0x0008)	/* Full frame received */
#define SCCE_ENET_BSY	((ushort)0x0004)	/* All incoming buffers full */
#define SCCE_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
#define SCCE_ENET_RXB	((ushort)0x0001)	/* A buffer was received */

/* SCC Mode Register (PSMR) as used by Ethernet.
*/
#define SCC_PSMR_HBC	((ushort)0x8000)	/* Enable heartbeat */
#define SCC_PSMR_FC	((ushort)0x4000)	/* Force collision */
#define SCC_PSMR_RSH	((ushort)0x2000)	/* Receive short frames */
#define SCC_PSMR_IAM	((ushort)0x1000)	/* Check individual hash */
#define SCC_PSMR_ENCRC	((ushort)0x0800)	/* Ethernet CRC mode */
#define SCC_PSMR_PRO	((ushort)0x0200)	/* Promiscuous mode */
#define SCC_PSMR_BRO	((ushort)0x0100)	/* Catch broadcast pkts */
#define SCC_PSMR_SBT	((ushort)0x0080)	/* Special backoff timer */
#define SCC_PSMR_LPB	((ushort)0x0040)	/* Set Loopback mode */
#define SCC_PSMR_SIP	((ushort)0x0020)	/* Sample Input Pins */
#define SCC_PSMR_LCW	((ushort)0x0010)	/* Late collision window */
#define SCC_PSMR_NIB22	((ushort)0x000a)	/* Start frame search */
#define SCC_PSMR_FDE	((ushort)0x0001)	/* Full duplex enable */

/* Buffer descriptor control/status used by Ethernet receive.
*/
#define BD_ENET_RX_EMPTY	((ushort)0x8000)
#define BD_ENET_RX_WRAP		((ushort)0x2000)
#define BD_ENET_RX_INTR		((ushort)0x1000)
#define BD_ENET_RX_LAST		((ushort)0x0800)
#define BD_ENET_RX_FIRST	((ushort)0x0400)
#define BD_ENET_RX_MISS		((ushort)0x0100)
#define BD_ENET_RX_LG		((ushort)0x0020)
#define BD_ENET_RX_NO		((ushort)0x0010)
#define BD_ENET_RX_SH		((ushort)0x0008)
#define BD_ENET_RX_CR		((ushort)0x0004)
#define BD_ENET_RX_OV		((ushort)0x0002)
#define BD_ENET_RX_CL		((ushort)0x0001)
#define BD_ENET_RX_STATS	((ushort)0x013f)	/* All status bits */

/* Buffer descriptor control/status used by Ethernet transmit.
*/
#define BD_ENET_TX_READY	((ushort)0x8000)
#define BD_ENET_TX_PAD		((ushort)0x4000)
#define BD_ENET_TX_WRAP		((ushort)0x2000)
#define BD_ENET_TX_INTR		((ushort)0x1000)
#define BD_ENET_TX_LAST		((ushort)0x0800)
#define BD_ENET_TX_TC		((ushort)0x0400)
#define BD_ENET_TX_DEF		((ushort)0x0200)
#define BD_ENET_TX_HB		((ushort)0x0100)
#define BD_ENET_TX_LC		((ushort)0x0080)
#define BD_ENET_TX_RL		((ushort)0x0040)
#define BD_ENET_TX_RCMASK	((ushort)0x003c)
#define BD_ENET_TX_UN		((ushort)0x0002)
#define BD_ENET_TX_CSL		((ushort)0x0001)
#define BD_ENET_TX_STATS	((ushort)0x03ff)	/* All status bits */

/* SCC as UART
*/
typedef struct scc_uart {
	sccp_t	scc_genscc;
	uint	scc_res1;	/* Reserved */
	uint	scc_res2;	/* Reserved */
	ushort	scc_maxidl;	/* Maximum idle chars */
	ushort	scc_idlc;	/* temp idle counter */
	ushort	scc_brkcr;	/* Break count register */
	ushort	scc_parec;	/* receive parity error counter */
	ushort	scc_frmec;	/* receive framing error counter */
	ushort	scc_nosec;	/* receive noise counter */
	ushort	scc_brkec;	/* receive break condition counter */
	ushort	scc_brkln;	/* last received break length */
	ushort	scc_uaddr1;	/* UART address character 1 */
	ushort	scc_uaddr2;	/* UART address character 2 */
	ushort	scc_rtemp;	/* Temp storage */
	ushort	scc_toseq;	/* Transmit out of sequence char */
	ushort	scc_char1;	/* control character 1 */
	ushort	scc_char2;	/* control character 2 */
	ushort	scc_char3;	/* control character 3 */
	ushort	scc_char4;	/* control character 4 */
	ushort	scc_char5;	/* control character 5 */
	ushort	scc_char6;	/* control character 6 */
	ushort	scc_char7;	/* control character 7 */
	ushort	scc_char8;	/* control character 8 */
	ushort	scc_rccm;	/* receive control character mask */
	ushort	scc_rccr;	/* receive control character register */
	ushort	scc_rlbc;	/* receive last break character */
} scc_uart_t;

/* SCC Event and Mask registers when it is used as a UART.
*/
#define UART_SCCM_GLR		((ushort)0x1000)
#define UART_SCCM_GLT		((ushort)0x0800)
#define UART_SCCM_AB		((ushort)0x0200)
#define UART_SCCM_IDL		((ushort)0x0100)
#define UART_SCCM_GRA		((ushort)0x0080)
#define UART_SCCM_BRKE		((ushort)0x0040)
#define UART_SCCM_BRKS		((ushort)0x0020)
#define UART_SCCM_CCR		((ushort)0x0008)
#define UART_SCCM_BSY		((ushort)0x0004)
#define UART_SCCM_TX		((ushort)0x0002)
#define UART_SCCM_RX		((ushort)0x0001)

/* The SCC PSMR when used as a UART.
*/
#define SCU_PSMR_FLC		((ushort)0x8000)
#define SCU_PSMR_SL		((ushort)0x4000)
#define SCU_PSMR_CL		((ushort)0x3000)
#define SCU_PSMR_UM		((ushort)0x0c00)
#define SCU_PSMR_FRZ		((ushort)0x0200)
#define SCU_PSMR_RZS		((ushort)0x0100)
#define SCU_PSMR_SYN		((ushort)0x0080)
#define SCU_PSMR_DRT		((ushort)0x0040)
#define SCU_PSMR_PEN		((ushort)0x0010)
#define SCU_PSMR_RPM		((ushort)0x000c)
#define SCU_PSMR_REVP		((ushort)0x0008)
#define SCU_PSMR_TPM		((ushort)0x0003)
#define SCU_PSMR_TEVP		((ushort)0x0003)

/* CPM Transparent mode SCC.
 */
typedef struct scc_trans {
	sccp_t	st_genscc;
	uint	st_cpres;	/* Preset CRC */
	uint	st_cmask;	/* Constant mask for CRC */
} scc_trans_t;

#define BD_SCC_TX_LAST		((ushort)0x0800)

/* IIC parameter RAM.
*/
typedef struct iic {
	ushort	iic_rbase;	/* Rx Buffer descriptor base address */
	ushort	iic_tbase;	/* Tx Buffer descriptor base address */
	u_char	iic_rfcr;	/* Rx function code */
	u_char	iic_tfcr;	/* Tx function code */
	ushort	iic_mrblr;	/* Max receive buffer length */
	uint	iic_rstate;	/* Internal */
	uint	iic_rdp;	/* Internal */
	ushort	iic_rbptr;	/* Internal */
	ushort	iic_rbc;	/* Internal */
	uint	iic_rxtmp;	/* Internal */
	uint	iic_tstate;	/* Internal */
	uint	iic_tdp;	/* Internal */
	ushort	iic_tbptr;	/* Internal */
	ushort	iic_tbc;	/* Internal */
	uint	iic_txtmp;	/* Internal */
	uint	iic_res;	/* reserved */
	ushort	iic_rpbase;	/* Relocation pointer */
	ushort	iic_res2;	/* reserved */
} iic_t;

/* SPI parameter RAM.
*/
typedef struct spi {
	ushort	spi_rbase;	/* Rx Buffer descriptor base address */
	ushort	spi_tbase;	/* Tx Buffer descriptor base address */
	u_char	spi_rfcr;	/* Rx function code */
	u_char	spi_tfcr;	/* Tx function code */
	ushort	spi_mrblr;	/* Max receive buffer length */
	uint	spi_rstate;	/* Internal */
	uint	spi_rdp;	/* Internal */
	ushort	spi_rbptr;	/* Internal */
	ushort	spi_rbc;	/* Internal */
	uint	spi_rxtmp;	/* Internal */
	uint	spi_tstate;	/* Internal */
	uint	spi_tdp;	/* Internal */
	ushort	spi_tbptr;	/* Internal */
	ushort	spi_tbc;	/* Internal */
	uint	spi_txtmp;	/* Internal */
	uint	spi_res;
	ushort	spi_rpbase;	/* Relocation pointer */
	ushort	spi_res2;
} spi_t;

/* SPI Mode register.
*/
#define SPMODE_LOOP	((ushort)0x4000)	/* Loopback */
#define SPMODE_CI	((ushort)0x2000)	/* Clock Invert */
#define SPMODE_CP	((ushort)0x1000)	/* Clock Phase */
#define SPMODE_DIV16	((ushort)0x0800)	/* BRG/16 mode */
#define SPMODE_REV	((ushort)0x0400)	/* Reversed Data */
#define SPMODE_MSTR	((ushort)0x0200)	/* SPI Master */
#define SPMODE_EN	((ushort)0x0100)	/* Enable */
#define SPMODE_LENMSK	((ushort)0x00f0)	/* character length */
#define SPMODE_PMMSK	((ushort)0x000f)	/* prescale modulus */

#define SPMODE_LEN(x)	((((x)-1)&0xF)<<4)
#define SPMODE_PM(x)	((x) &0xF)

/* HDLC parameter RAM.
*/

typedef struct hdlc_pram_s {
	/*
	 * SCC parameter RAM
	 */
	ushort	rbase;		/* Rx Buffer descriptor base address */
	ushort	tbase;		/* Tx Buffer descriptor base address */
	uchar	rfcr;		/* Rx function code */
	uchar	tfcr;		/* Tx function code */
	ushort	mrblr;		/* Rx buffer length */
	ulong	rstate;		/* Rx internal state */
	ulong	rptr;		/* Rx internal data pointer */
	ushort	rbptr;		/* rb BD Pointer */
	ushort	rcount;		/* Rx internal byte count */
	ulong	rtemp;		/* Rx temp */
	ulong	tstate;		/* Tx internal state */
	ulong	tptr;		/* Tx internal data pointer */
	ushort	tbptr;		/* Tx BD pointer */
	ushort	tcount;		/* Tx byte count */
	ulong	ttemp;		/* Tx temp */
	ulong	rcrc;		/* temp receive CRC */
	ulong	tcrc;		/* temp transmit CRC */
	/*
	 * HDLC specific parameter RAM
	 */
	uchar	res[4];		/* reserved */
	ulong	c_mask;		/* CRC constant */
	ulong	c_pres;		/* CRC preset */
	ushort	disfc;		/* discarded frame counter */
	ushort	crcec;		/* CRC error counter */
	ushort	abtsc;		/* abort sequence counter */
	ushort	nmarc;		/* nonmatching address rx cnt */
	ushort	retrc;		/* frame retransmission cnt */
	ushort	mflr;		/* maximum frame length reg */
	ushort	max_cnt;	/* maximum length counter */
	ushort	rfthr;		/* received frames threshold */
	ushort	rfcnt;		/* received frames count */
	ushort	hmask;		/* user defined frm addr mask */
	ushort	haddr1;		/* user defined frm address 1 */
	ushort	haddr2;		/* user defined frm address 2 */
	ushort	haddr3;		/* user defined frm address 3 */
	ushort	haddr4;		/* user defined frm address 4 */
	ushort	tmp;		/* temp */
	ushort	tmp_mb;		/* temp */
} hdlc_pram_t;

/* CPM interrupts.  There are nearly 32 interrupts generated by CPM
 * channels or devices.  All of these are presented to the PPC core
 * as a single interrupt.  The CPM interrupt handler dispatches its
 * own handlers, in a similar fashion to the PPC core handler.  We
 * use the table as defined in the manuals (i.e. no special high
 * priority and SCC1 == SCCa, etc...).
 */
#define CPMVEC_NR		32
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    #define CPMVEC_OFFSET           0x00010000
#define CPMVEC_PIO_PC15		((ushort)0x1f | CPMVEC_OFFSET)
#define CPMVEC_SCC1		((ushort)0x1e | CPMVEC_OFFSET)
#define CPMVEC_SCC2		((ushort)0x1d | CPMVEC_OFFSET)
#define CPMVEC_SCC3		((ushort)0x1c | CPMVEC_OFFSET)
#define CPMVEC_SCC4		((ushort)0x1b | CPMVEC_OFFSET)
#define CPMVEC_PIO_PC14		((ushort)0x1a | CPMVEC_OFFSET)
#define CPMVEC_TIMER1		((ushort)0x19 | CPMVEC_OFFSET)
#define CPMVEC_PIO_PC13		((ushort)0x18 | CPMVEC_OFFSET)
#define CPMVEC_PIO_PC12		((ushort)0x17 | CPMVEC_OFFSET)
#define CPMVEC_SDMA_CB_ERR	((ushort)0x16 | CPMVEC_OFFSET)
#define CPMVEC_IDMA1		((ushort)0x15 | CPMVEC_OFFSET)
#define CPMVEC_IDMA2		((ushort)0x14 | CPMVEC_OFFSET)
#define CPMVEC_TIMER2		((ushort)0x12 | CPMVEC_OFFSET)
#define CPMVEC_RISCTIMER	((ushort)0x11 | CPMVEC_OFFSET)
#define CPMVEC_I2C		((ushort)0x10 | CPMVEC_OFFSET)
#define CPMVEC_PIO_PC11		((ushort)0x0f | CPMVEC_OFFSET)
#define CPMVEC_PIO_PC10		((ushort)0x0e | CPMVEC_OFFSET)
#define CPMVEC_TIMER3		((ushort)0x0c | CPMVEC_OFFSET)
#define CPMVEC_PIO_PC9		((ushort)0x0b | CPMVEC_OFFSET)
#define CPMVEC_PIO_PC8		((ushort)0x0a | CPMVEC_OFFSET)
#define CPMVEC_PIO_PC7		((ushort)0x09 | CPMVEC_OFFSET)
#define CPMVEC_TIMER4		((ushort)0x07 | CPMVEC_OFFSET)
#define CPMVEC_PIO_PC6		((ushort)0x06 | CPMVEC_OFFSET)
#define CPMVEC_SPI		((ushort)0x05 | CPMVEC_OFFSET)
#define CPMVEC_SMC1		((ushort)0x04 | CPMVEC_OFFSET)
#define CPMVEC_SMC2		((ushort)0x03 | CPMVEC_OFFSET)
#define CPMVEC_PIO_PC5		((ushort)0x02 | CPMVEC_OFFSET)
#define CPMVEC_PIO_PC4		((ushort)0x01 | CPMVEC_OFFSET)
#define CPMVEC_ERROR		((ushort)0x00 | CPMVEC_OFFSET)
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extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);

/* CPM interrupt configuration vector.
*/
#define	CICR_SCD_SCC4		((uint)0x00c00000)	/* SCC4 @ SCCd */
#define	CICR_SCC_SCC3		((uint)0x00200000)	/* SCC3 @ SCCc */
#define	CICR_SCB_SCC2		((uint)0x00040000)	/* SCC2 @ SCCb */
#define	CICR_SCA_SCC1		((uint)0x00000000)	/* SCC1 @ SCCa */
#define CICR_IRL_MASK		((uint)0x0000e000)	/* Core interrrupt */
#define CICR_HP_MASK		((uint)0x00001f00)	/* Hi-pri int. */
#define CICR_IEN		((uint)0x00000080)	/* Int. enable */
#define CICR_SPS		((uint)0x00000001)	/* SCC Spread */
#endif /* __CPM_8XX__ */
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