lpddr4_timing.c

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	{ 0x13012, 0x1 },
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	{ 0x13018, 0x1 },
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	{ 0x138b4, 0x1 },
	{ 0x20089, 0x1 },
	{ 0x20088, 0x19 },
	{ 0xc0080, 0x2 },
	{ 0xd0000, 0x1 },
};

static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
	{
		/* P0 3200mts 1D */
		.drate = 3200,
		.fw_type = FW_1D_IMAGE,
		.fsp_cfg = lpddr4_fsp0_cfg,
		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
	},
	{
		/* P0 3200mts 2D */
		.drate = 3200,
		.fw_type = FW_2D_IMAGE,
		.fsp_cfg = lpddr4_fsp0_2d_cfg,
		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
	},
	{
		/* P1 400mts 1D */
		.drate = 400,
		.fw_type = FW_1D_IMAGE,
		.fsp_cfg = lpddr4_fsp1_cfg,
		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
	},
#if 0
	{
		/* P1 100mts 1D */
		.drate = 100,
		.fw_type = FW_1D_IMAGE,
		.fsp_cfg = lpddr4_fsp2_cfg,
		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
	},
#endif
};

struct dram_timing_info lpddr4_timing_ = {
	.ddrc_cfg = lpddr4_ddrc_cfg,
	.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
	.ddrphy_cfg = lpddr4_ddrphy_cfg,
	.ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
	.fsp_msg = lpddr4_dram_fsp_msg,
	.fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
	.ddrphy_pie = lpddr4_phy_pie,
	.ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
};