disable 200Mhz ddr mode for emmc (usdhc1)

This seems to cause data abort panics on "mmc rescan"
command.

Also remove the pinmuxing options on the GP_EMMC_RESET
and USDHC2_RST signals. We keep it how spl left it.

arch/arm/dts/imx8mq-nitrogen8m_som.dts

@@ -310,15 +310,6 @@
 		>;
 	};
 
-/*
-	pinctrl_reg_wlan_vmmc: reg-wlan-vmmcgrp {
-		fsl,pins = <
-#define GP_REG_WLAN_VMMC	<&gpio3 20 GPIO_ACTIVE_HIGH>
-			MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20		0x16
-		>;
-	};
-*/
-
 	pinctrl_sai1: sai1grp {
 		fsl,pins = <
 			/* wm8960 */
@@ -408,12 +399,6 @@
 			MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5		0xc3
 			MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6		0xc3
 			MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7		0xc3
-#if 0
-			MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B		0xc1
-#else
-#define GP_EMMC_RESET		<&gpio2 10 GPIO_ACTIVE_LOW>
-			MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10		0x41
-#endif
 		>;
 	};
 
@@ -447,6 +432,7 @@
 		>;
 	};
 
+
 	pinctrl_usdhc2: usdhc2grp {
 		fsl,pins = <
 			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x03
@@ -455,8 +441,6 @@
 			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
 			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
 			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
-			/* Bluetooth slow clock */
-			MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K	0x03
 		>;
 	};
 
@@ -605,20 +589,6 @@
 		regulator-max-microvolt = <5000000>;
 	};
 
-/*
-	reg_wlan_vmmc: regulator-wlan-vmmc {
-		compatible = "regulator-fixed";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_reg_wlan_vmmc>;
-		regulator-name = "reg_wlan_vmmc";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		gpio = GP_REG_WLAN_VMMC;
-		startup-delay-us = <70000>;
-		enable-active-high;
-	};
-*/
-
 #if 0
 	sound-wm8960 {
 		compatible = "fsl,imx-audio-wm8960";
@@ -1336,8 +1306,8 @@
 &usdhc1 {
 	cap-mmc-highspeed;
 	bus-width = <8>;
-	mmc-ddr-1_8v;
-	mmc-hs200-1_8v;
+	// mmc-ddr-1_8v;
+	// mmc-hs200-1_8v;
 	fsl,strobe-dll-delay-target = <5>;
 	fsl,tuning-start-tap = <63>;
 	fsl,tuning-step = <2>;
@@ -1366,7 +1336,6 @@
 	tuning-delay = <32>;
 	tuning-mode = <1>;
 	vmmc-supply = <&reg_vref_3v3>;
-	vqmmc-1-8-v;
 };