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    /*
     * (C) Copyright 2007-2008
     * Stelian Pop <stelian.pop@leadtechdesign.com>
     * Lead Tech Design <www.leadtechdesign.com>
     *
     * See file CREDITS for list of people who contributed to this
     * project.
     *
     * This program is free software; you can redistribute it and/or
     * modify it under the terms of the GNU General Public License as
     * published by the Free Software Foundation; either version 2 of
     * the License, or (at your option) any later version.
     *
     * This program is distributed in the hope that it will be useful,
     * but WITHOUT ANY WARRANTY; without even the implied warranty of
     * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
     * GNU General Public License for more details.
     *
     * You should have received a copy of the GNU General Public License
     * along with this program; if not, write to the Free Software
     * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
     * MA 02111-1307 USA
     */
    
    #include <common.h>
    #include <asm/arch/at91sam9261.h>
    #include <asm/arch/at91sam9261_matrix.h>
    #include <asm/arch/at91sam9_smc.h>
    #include <asm/arch/at91_pmc.h>
    #include <asm/arch/at91_rstc.h>
    #include <asm/arch/gpio.h>
    #include <asm/arch/io.h>
    #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
    #include <net.h>
    #endif
    
    DECLARE_GLOBAL_DATA_PTR;
    
    /* ------------------------------------------------------------------------- */
    /*
     * Miscelaneous platform dependent initialisations
     */
    
    static void at91sam9261ek_serial_hw_init(void)
    {
    #ifdef CONFIG_USART0
    	at91_set_A_periph(AT91_PIN_PC8, 1);		/* TXD0 */
    	at91_set_A_periph(AT91_PIN_PC9, 0);		/* RXD0 */
    	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
    #endif
    
    #ifdef CONFIG_USART1
    	at91_set_A_periph(AT91_PIN_PC12, 1);		/* TXD1 */
    	at91_set_A_periph(AT91_PIN_PC13, 0);		/* RXD1 */
    	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
    #endif
    
    #ifdef CONFIG_USART2
    	at91_set_A_periph(AT91_PIN_PC14, 1);		/* TXD2 */
    	at91_set_A_periph(AT91_PIN_PC15, 0);		/* RXD2 */
    	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
    #endif
    
    #ifdef CONFIG_USART3	/* DBGU */
    	at91_set_A_periph(AT91_PIN_PA9, 0);		/* DRXD */
    	at91_set_A_periph(AT91_PIN_PA10, 1);		/* DTXD */
    	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
    #endif
    }
    
    #ifdef CONFIG_CMD_NAND
    static void at91sam9261ek_nand_hw_init(void)
    {
    	unsigned long csa;
    
    	/* Enable CS3 */
    	csa = at91_sys_read(AT91_MATRIX_EBICSA);
    	at91_sys_write(AT91_MATRIX_EBICSA,
    		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
    
    	/* Configure SMC CS3 for NAND/SmartMedia */
    	at91_sys_write(AT91_SMC_SETUP(3),
    		       AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
    		       AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
    	at91_sys_write(AT91_SMC_PULSE(3),
    		       AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5) |
    		       AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));
    	at91_sys_write(AT91_SMC_CYCLE(3),
    		       AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
    	at91_sys_write(AT91_SMC_MODE(3),
    		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
    		       AT91_SMC_EXNWMODE_DISABLE |
    #ifdef CFG_NAND_DBW_16
    		       AT91_SMC_DBW_16 |
    #else /* CFG_NAND_DBW_8 */
    		       AT91_SMC_DBW_8 |
    #endif
    		       AT91_SMC_TDF_(1));
    
    	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
    
    	/* Configure RDY/BSY */
    	at91_set_gpio_input(AT91_PIN_PC15, 1);
    
    	/* Enable NandFlash */
    	at91_set_gpio_output(AT91_PIN_PC14, 1);
    
    	at91_set_A_periph(AT91_PIN_PC0, 0);	/* NANDOE */
    	at91_set_A_periph(AT91_PIN_PC1, 0);	/* NANDWE */
    }
    #endif
    
    #ifdef CONFIG_HAS_DATAFLASH
    static void at91sam9261ek_spi_hw_init(void)
    {
    	at91_set_A_periph(AT91_PIN_PA3, 0);	/* SPI0_NPCS0 */
    
    	at91_set_A_periph(AT91_PIN_PA0, 0);	/* SPI0_MISO */
    	at91_set_A_periph(AT91_PIN_PA1, 0);	/* SPI0_MOSI */
    	at91_set_A_periph(AT91_PIN_PA2, 0);	/* SPI0_SPCK */
    
    	/* Enable clock */
    	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI0);
    }
    #endif
    
    #ifdef CONFIG_DRIVER_DM9000
    static void at91sam9261ek_dm9000_hw_init(void)
    {
    	/* Configure SMC CS2 for DM9000 */
    	at91_sys_write(AT91_SMC_SETUP(2),
    		       AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
    		       AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
    	at91_sys_write(AT91_SMC_PULSE(2),
    		       AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) |
    		       AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));
    	at91_sys_write(AT91_SMC_CYCLE(2),
    		       AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
    	at91_sys_write(AT91_SMC_MODE(2),
    		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
    		       AT91_SMC_EXNWMODE_DISABLE |
    		       AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
    		       AT91_SMC_TDF_(1));
    
    	/* Configure Reset signal as output */
    	at91_set_gpio_output(AT91_PIN_PC10, 0);
    
    	/* Configure Interrupt pin as input, no pull-up */
    	at91_set_gpio_input(AT91_PIN_PC11, 0);
    }
    #endif
    
    int board_init(void)
    {
    	/* Enable Ctrlc */
    	console_init_f();
    
    	/* arch number of AT91SAM9261EK-Board */
    	gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
    	/* adress of boot parameters */
    	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
    
    	at91sam9261ek_serial_hw_init();
    #ifdef CONFIG_CMD_NAND
    	at91sam9261ek_nand_hw_init();
    #endif
    #ifdef CONFIG_HAS_DATAFLASH
    	at91sam9261ek_spi_hw_init();
    #endif
    #ifdef CONFIG_DRIVER_DM9000
    	at91sam9261ek_dm9000_hw_init();
    #endif
    	return 0;
    }
    
    int dram_init(void)
    {
    	gd->bd->bi_dram[0].start = PHYS_SDRAM;
    	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
    	return 0;
    }
    
    #ifdef CONFIG_RESET_PHY_R
    void reset_phy(void)
    {
    #ifdef CONFIG_DRIVER_DM9000
    	/*
    	 * Initialize ethernet HW addr prior to starting Linux,
    	 * needed for nfsroot
    	 */
    	eth_init(gd->bd);
    #endif
    }
    #endif