Unverified Commit 9399ca0c authored by mntmn's avatar mntmn
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Merge branch 'axi-dma-writes' of https://source.mntmn.com/shanshe/zz9000-firmware into wip-fw16

parents b8531162 bc57d793
......@@ -16,7 +16,7 @@ The interesting bits:
- `mntzorro.v` is the Zorro 2/3 interface and 24-bit video capture engine, AXI4-Lite interface
- `video_formatter.v` is the AXI video stream formatter that reinterprets and controls an incoming 32-bit word stream as 8-bit palette indexed, 16-bit 565 or 24-bit RGBX pixels and outputs a 24-bit true color parallel RGB stream with horizontal and vertical sync
- `zz9000-fw/ZZ9000_proto.sdk/ZZ9000Test/src`
- `zz9000-fw/ZZ9000_proto.sdk/ZZ9000OS/src`
- `main.c` is the main entrypoint of ZZ9000OS.elf which runs on the ARM core 0 and talks to `MNTZorro` and `video_formatter` in the FPGA fabric
- `gfx.c` graphics acceleration routines, currently mainly rect fill and copy
- `ethernet.c` low-level ethernet driver/framer
......@@ -31,7 +31,7 @@ As Vivado projects are not suitable for version control, the Vivado project / bl
Start Vivado from your terminal in tcl mode:
```
source settings64.sh
source /path/to/Xilinx/Vivado/2018.3/settings64.sh
cd /place/where/you/checked/out/zz9000-firmware
vivado -mode tcl
```
......@@ -49,7 +49,7 @@ After a while you should be able to select "Run Synthesis" in Flow Navigator, an
Your SDK workspace will start with the `zz9000_ps_wrapper_hw_platform_0` project.
To recreate a project for ZZ9000OS, go to "File" / "New" / "Application Project". Enter "ZZ9000OS" as the Project name and click "Next". Select "Empty Application". Click "Finish". Right click "ZZ9000OS" in your Project Explorer and select "Import". Select "General" / "File System", click "Next". Select the `ZZ9000_proto.sdk` / `ZZ9000Test` subfolder in your `zz9000-firmware` folder. Check the checkmark next to "ZZ9000Test". Click Finish. Select "Yes to all" in the overwrite dialog. Now you will be able to build ZZ9000OS.
To recreate a project for ZZ9000OS, go to "File" / "New" / "Application Project". Enter "ZZ9000OS" as the Project name and click "Next". Select "Empty Application". Click "Finish". Right click "ZZ9000OS" in your Project Explorer and select "Import". Select "General" / "File System", click "Next". Select the `ZZ9000_proto.sdk` / `ZZ9000OS` subfolder in your `zz9000-firmware` folder. Check the checkmark next to "ZZ9000OS". Click Finish. Select "Yes to all" in the overwrite dialog. Now you will be able to build ZZ9000OS.
Before the next step, configure your BSP Project. Expand the ZZ9000OS_bsp node and double click `system.mss`. Click "Modify this BSP's Settings". Check `xilffs` in the Supported Libraries.
......@@ -57,9 +57,9 @@ To recreate the bootloader project, go to "File" / "New" / "Application Project"
# Building BOOT.bin
The Eclipse-based Vivado SDK has a built-in tool (Menu "Xilinx" / "Create Boot Image") to generate the boot image `BOOT.bin`. To prepare, open `ZZ9000_proto.sdk/ZZ9000Test/bootimage/ZZ9000OS.bif` in a text editor and change the absolute paths to match the correct ELF files on your filesystem.
The Eclipse-based Vivado SDK has a built-in tool (Menu "Xilinx" / "Create Boot Image") to generate the boot image `BOOT.bin`. To prepare, open `ZZ9000_proto.sdk/ZZ9000OS/bootimage/ZZ9000OS.bif` in a text editor and change the absolute paths to match the correct ELF files on your filesystem.
In the "Create Boot Image" dialog, select "Import from existing BIF file" and select the definition file `ZZ9000_proto.sdk/ZZ9000Test/bootimage/ZZ9000OS.bif` and click "Create Image".
In the "Create Boot Image" dialog, select "Import from existing BIF file" and select the definition file `ZZ9000_proto.sdk/ZZ9000OS/bootimage/ZZ9000OS.bif` and click "Create Image".
`BOOT.bin` contains 3 files (“partitions”):
......
......@@ -138,24 +138,24 @@ module MNTZorro_v0_1_S00_AXI
output reg m00_axi_bready,
// read address channel
/*input wire m00_axi_arready,
output reg [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_arid,
output reg [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_araddr,
output reg [7 : 0] m00_axi_arlen,
output reg [2 : 0] m00_axi_arsize,
output reg [1 : 0] m00_axi_arburst,
output reg m00_axi_arlock,
output reg [3 : 0] m00_axi_arcache,
output reg [2 : 0] m00_axi_arprot,
output reg [3 : 0] m00_axi_arqos,
output reg m00_axi_arvalid,
input wire m00_axi_arready,
// output reg [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_arid,
output reg [`C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_araddr,
output reg [7 : 0] m00_axi_arlen,
output reg [2 : 0] m00_axi_arsize,
output reg [1 : 0] m00_axi_arburst,
output reg m00_axi_arlock,
output reg [3 : 0] m00_axi_arcache,
output reg [2 : 0] m00_axi_arprot,
output reg [3 : 0] m00_axi_arqos,
output reg m00_axi_arvalid,
output reg m00_axi_rready,
input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_rid,
input wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_rdata,
input wire [1 : 0] m00_axi_rresp,
input wire m00_axi_rlast,
input wire m00_axi_rvalid,*/
output reg m00_axi_rready,
// input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_rid,
input wire [`C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_rdata,
input wire [1 : 0] m00_axi_rresp,
input wire m00_axi_rlast,
input wire m00_axi_rvalid,
// HP master interface 2 to write to PS memory directly (for videocap)
input wire m01_axi_aclk,
......@@ -891,6 +891,9 @@ module MNTZorro_v0_1_S00_AXI
localparam Z3_WRITE_PRE2 = 51;
localparam WAIT_WRITE_DMA_Z3B = 52;
localparam WAIT_WRITE_DMA_Z3C = 53;
localparam WAIT_READ_DMA_Z3 = 54;
localparam WAIT_READ_DMA_Z3B = 55;
localparam WAIT_READ_DMA_Z3C = 56;
(* mark_debug = "true" *) reg [7:0] zorro_state = COLD;
reg zorro_idle = 0;
......@@ -1204,6 +1207,15 @@ module MNTZorro_v0_1_S00_AXI
m00_axi_wlast <= 'h1;
m00_axi_bready <= 'h1;
m00_axi_arlen <= 'h0;
m00_axi_arsize <= 'h2;
m00_axi_arburst <= 'h0;
m00_axi_arcache <= 'hF; //was 3
m00_axi_arlock <= 'h0;
m00_axi_arprot <= 'h0;
m00_axi_arqos <= 'h0;
m00_axi_rready <= 1;
// FIXME this could use bursts
m01_axi_awlen <= 'h0; // 1 burst (1 write)
m01_axi_awsize <= 'h2; //'h2; // 2^2 == 4 bytes
......@@ -1818,7 +1830,10 @@ module MNTZorro_v0_1_S00_AXI
data_z3_low16 <= default_data;
slaven <= 1;
zorro_state <= Z3_READ_UPPER;
if (z3_mapped_addr<'h10000 || videocap_mode)
zorro_state <= Z3_READ_UPPER;
else
zorro_state <= WAIT_READ_DMA_Z3;
end else begin
// address not recognized
slaven <= 0;
......@@ -1935,6 +1950,27 @@ module MNTZorro_v0_1_S00_AXI
end
end
WAIT_READ_DMA_Z3: begin
m00_axi_araddr <= `ARM_MEMORY_START + (z3_mapped_addr/*&32'hfffffffc*/); // max 256MB
m00_axi_arvalid <= 1;
// m00_axi_rready <= 1;
if (m00_axi_arready) begin
zorro_state <= WAIT_READ_DMA_Z3B;
end
end
WAIT_READ_DMA_Z3B: begin
m00_axi_arvalid <= 0;
// m00_axi_rready <= 1;
if (m00_axi_rvalid) begin
zorro_state <= Z3_ENDCYCLE;
data_z3_hi16 <= {m00_axi_rdata[7:0], m00_axi_rdata[15:8]};
data_z3_low16 <= {m00_axi_rdata[23:16], m00_axi_rdata[31:24]};
dataout_z3 <= 1; // enable data output
dtack <= 1;
end
end
WAIT_WRITE_DMA_Z3: begin
//z3_axi_write <= 1;
......@@ -1949,6 +1985,7 @@ module MNTZorro_v0_1_S00_AXI
end
WAIT_WRITE_DMA_Z3B: begin
dtack <= 1;
m00_axi_awvalid_z3 <= 0;
m00_axi_wvalid_z3 <= 1;
if (m00_axi_wready) begin
......@@ -1965,7 +2002,7 @@ module MNTZorro_v0_1_S00_AXI
Z3_ENDCYCLE: begin
//z3_axi_write <= 0;
dtack <= 1;
slaven <= 0;
// slaven <= 0;
// we're timing out or own dtack here. because of a zorro
// bug / subtlety, dtack can be sampled incorrectly to "hang over"
......
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