From efe33c9764efc997507cf66da8c706716888a33f Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 25 Jun 2020 11:21:24 +0200
Subject: [PATCH] targets/arty: add fixed sdcard clock and remove sys2x (use
NETWORKING interface_type on DDR3).
---
litex_boards/targets/arty.py | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/litex_boards/targets/arty.py b/litex_boards/targets/arty.py
index 8a7e373..52b5785 100755
--- a/litex_boards/targets/arty.py
+++ b/litex_boards/targets/arty.py
@@ -27,11 +27,11 @@ from liteeth.phy.mii import LiteEthPHYMII
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
- self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_eth = ClockDomain()
+ self.clock_domains.cd_sdcard = ClockDomain()
# # #
@@ -39,11 +39,11 @@ class _CRG(Module):
self.comb += pll.reset.eq(~platform.request("cpu_reset"))
pll.register_clkin(platform.request("clk100"), 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
- pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_clk200, 200e6)
pll.create_clkout(self.cd_eth, 25e6)
+ pll.create_clkout(self.cd_sdcard, 10e6)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
@@ -66,8 +66,7 @@ class BaseSoC(SoCCore):
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
- sys_clk_freq = sys_clk_freq,
- interface_type = "MEMORY")
+ sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
--
GitLab