From dcc65b347df4c3e3334fce2a6723a793f60a69a6 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 22 Jan 2020 15:56:21 +0100
Subject: [PATCH] targets/colorlight_5a_75b: switch to SoCCore, CPU and
Etherbone working :)
Tested with:
./colorlight_5a_75b.py --cpu-type=picorv32 --uart-name=crossover --with-etherbone --csr-csv=csr.csv
Load with following script:
#!/usr/bin/env python3
# Load ---------------------------------------------------------------------------------------------
def load():
import os
f = open("openocd.cfg", "w")
f.write(
"""
interface ftdi
ftdi_vid_pid 0x0403 0x6011
ftdi_channel 0
ftdi_layout_init 0x0098 0x008b
reset_config none
adapter_khz 25000
jtag newtap ecp5 tap -irlen 8 -expected-id 0x41111043
""")
f.close()
os.system("openocd -f openocd.cfg -c \"transport select jtag; init; svf soc_etherbonesoc_colorlight_5a_75b/gateware/top.svf; exit\"")
exit()
if __name__ == "__main__":
load()
Then start lxserver:
lxserver --udp
And run following script:
#!/usr/bin/env python3
import sys
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# # #
while True:
if wb.regs.uart_xover_rxempty.read() == 0:
print(chr(wb.regs.uart_xover_rxtx.read()), end="")
sys.stdout.flush()
# # #
wb.close()
---
litex_boards/partner/targets/colorlight_5a_75b.py | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/litex_boards/partner/targets/colorlight_5a_75b.py b/litex_boards/partner/targets/colorlight_5a_75b.py
index 39ac3e8..44f6f80 100755
--- a/litex_boards/partner/targets/colorlight_5a_75b.py
+++ b/litex_boards/partner/targets/colorlight_5a_75b.py
@@ -41,13 +41,13 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
-class BaseSoC(SoCMini):
+class BaseSoC(SoCCore):
def __init__(self, revision, **kwargs):
platform = colorlight_5a_75b.Platform(revision=revision)
sys_clk_freq = int(125e6)
- # SoCMini ----------------------------------------------------------------------------------
- SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
+ # SoCCore ----------------------------------------------------------------------------------
+ SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
--
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