diff --git a/litex_boards/targets/ecpix5.py b/litex_boards/targets/ecpix5.py
index 5305053a83dff0cd7c1166952b089dbd1c305099..1e2dc8b931e33241b854befcc8044650158cef57 100755
--- a/litex_boards/targets/ecpix5.py
+++ b/litex_boards/targets/ecpix5.py
@@ -20,6 +20,7 @@ from litex.build.lattice.trellis import trellis_args, trellis_argdict
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
 
 from litedram.modules import MT41K256M16
 from litedram.phy import ECP5DDRPHY
@@ -116,11 +117,16 @@ class BaseSoC(SoCCore):
             self.add_csr("ethphy")
             self.add_ethernet(phy=self.ethphy)
 
-        # Leds (Disable...) ------------------------------------------------------------------------
+        # Leds -------------------------------------------------------------------------------------
+        leds_pads = []
         for i in range(4):
             rgb_led_pads = platform.request("rgb_led", i)
-            for c in "rgb":
-                self.comb += getattr(rgb_led_pads, c).eq(1)
+            self.comb += [getattr(rgb_led_pads, n).eq(1) for n in "gb"] # Disable Green/Blue Leds.
+            leds_pads += [getattr(rgb_led_pads, n) for n in "r"]
+        self.submodules.leds = LedChaser(
+            pads         = Cat(leds_pads),
+            sys_clk_freq = sys_clk_freq)
+        self.add_csr("leds")
 
 # Build --------------------------------------------------------------------------------------------