From 8d26c241cdd8c4adf3db1eb618b61132f90ebb0c Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 2 Nov 2020 19:51:48 +0100
Subject: [PATCH] kc705: revert sys_clk_freq to 125MHz.
---
litex_boards/targets/kc705.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/litex_boards/targets/kc705.py b/litex_boards/targets/kc705.py
index a479152..4c67880 100755
--- a/litex_boards/targets/kc705.py
+++ b/litex_boards/targets/kc705.py
@@ -48,7 +48,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
- def __init__(self, sys_clk_freq=int(150e6), with_ethernet=False, with_sata=False, **kwargs):
+ def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_sata=False, **kwargs):
platform = kc705.Platform()
# SoCCore ----------------------------------------------------------------------------------
--
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