diff --git a/litex_boards/platforms/colorlight_5a_75b.py b/litex_boards/platforms/colorlight_5a_75b.py
index 6564bd21cdfde9f901fa33ffad52bb82d9aa0561..944338d2421f011fa0121de90232bca3f80fc620 100644
--- a/litex_boards/platforms/colorlight_5a_75b.py
+++ b/litex_boards/platforms/colorlight_5a_75b.py
@@ -20,11 +20,10 @@ _io_v6_1 = [ # Documented by @smunaut
     ("user_btn_n", 0, Pins("R16"), IOStandard("LVCMOS33")),
 
     # serial
+    # There seems to be some capacitance on KEY+ pin, so high baudrates may not work (>9600bps).
     ("serial", 0,
         Subsignal("tx", Pins("U16")), # led (J19 DATA_LED-)
         Subsignal("rx", Pins("R16")), # btn (J19 KEY+)
-        # It seems there's some capacitance on the KEY+ pin, so bigger baudrates
-        # may not work
         IOStandard("LVCMOS33")
     ),
 
diff --git a/litex_boards/targets/colorlight_5a_75b.py b/litex_boards/targets/colorlight_5a_75b.py
index 131213c16ae4f3297e404bc47aea3980cf60ba8d..1d77bb512ff50909ed69db52d4bdbc7ba26691a0 100755
--- a/litex_boards/targets/colorlight_5a_75b.py
+++ b/litex_boards/targets/colorlight_5a_75b.py
@@ -7,12 +7,13 @@
 #
 # 1) SoC with regular UART and optional Ethernet connected to the CPU:
 # Connect a USB/UART to J19: TX of the FPGA is DATA_LED-, RX of the FPGA is KEY+.
-# ./colorlight_5a_75b.py --uart-baudrate 9600 (add --with-ethernet to add Ethernet capability)
+# ./colorlight_5a_75b.py --revision=7.0 (or 6.1) (--with-ethernet to add Ethernet capability)
+# Note: on revision 6.1, add --uart-baudrate=9600 to lower the baudrate.
 # ./colorlight_5a_75b.py --load
 # You should see the LiteX BIOS and be able to interact with it.
 #
 # 2) SoC with UART in crossover mode over Etherbone:
-# ./colorlight_5a_75b.py --uart-name=crossover --with-etherbone --csr-csv=csr.csv
+# ./colorlight_5a_75b.py --revision=7.0 (or 6.1) --uart-name=crossover --with-etherbone --csr-csv=csr.csv
 # ./colorlight_5a_75b.py --load
 # ping 192.168.1.50
 # Get and install wishbone tool from: https://github.com/litex-hub/wishbone-utils/releases