From 4401fec1e6d9bb1048ccb91b9e59c68094329edb Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 12 Nov 2020 11:54:11 +0100
Subject: [PATCH] targets: remove add_csr("crg") (no longer needed).
---
litex_boards/targets/acorn_cle_215.py | 1 -
litex_boards/targets/aller.py | 1 -
litex_boards/targets/nereid.py | 1 -
litex_boards/targets/tagus.py | 1 -
4 files changed, 4 deletions(-)
diff --git a/litex_boards/targets/acorn_cle_215.py b/litex_boards/targets/acorn_cle_215.py
index 43769e9..bbde93e 100755
--- a/litex_boards/targets/acorn_cle_215.py
+++ b/litex_boards/targets/acorn_cle_215.py
@@ -87,7 +87,6 @@ class BaseSoC(SoCCore):
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform, sys_clk_freq)
- self.add_csr("crg")
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
diff --git a/litex_boards/targets/aller.py b/litex_boards/targets/aller.py
index 9d5fe06..cc18085 100755
--- a/litex_boards/targets/aller.py
+++ b/litex_boards/targets/aller.py
@@ -70,7 +70,6 @@ class BaseSoC(SoCCore):
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform, sys_clk_freq)
- self.add_csr("crg")
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
diff --git a/litex_boards/targets/nereid.py b/litex_boards/targets/nereid.py
index 366ad6c..30dc47a 100755
--- a/litex_boards/targets/nereid.py
+++ b/litex_boards/targets/nereid.py
@@ -67,7 +67,6 @@ class BaseSoC(SoCCore):
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform, sys_clk_freq)
- self.add_csr("crg")
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
diff --git a/litex_boards/targets/tagus.py b/litex_boards/targets/tagus.py
index 96903e4..e716a85 100755
--- a/litex_boards/targets/tagus.py
+++ b/litex_boards/targets/tagus.py
@@ -70,7 +70,6 @@ class BaseSoC(SoCCore):
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform, sys_clk_freq)
- self.add_csr("crg")
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
--
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