diff --git a/litex_boards/targets/acorn_cle_215.py b/litex_boards/targets/acorn_cle_215.py
index 43769e9d5cb4b0e2c73aae9de35cf563a9ef09f4..bbde93e73af9a831266b3f2698abe1a423c51f62 100755
--- a/litex_boards/targets/acorn_cle_215.py
+++ b/litex_boards/targets/acorn_cle_215.py
@@ -87,7 +87,6 @@ class BaseSoC(SoCCore):
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = CRG(platform, sys_clk_freq)
-        self.add_csr("crg")
 
         # DDR3 SDRAM -------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
diff --git a/litex_boards/targets/aller.py b/litex_boards/targets/aller.py
index 9d5fe069982da0be80e0f12fbad1a5058da86956..cc18085553074a2adec761c6cb71a0cf1983a967 100755
--- a/litex_boards/targets/aller.py
+++ b/litex_boards/targets/aller.py
@@ -70,7 +70,6 @@ class BaseSoC(SoCCore):
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = CRG(platform, sys_clk_freq)
-        self.add_csr("crg")
 
         # DDR3 SDRAM -------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
diff --git a/litex_boards/targets/nereid.py b/litex_boards/targets/nereid.py
index 366ad6c4023016d8080de5542339b68f21840ea0..30dc47a2ee46c872c5e9b988d5a7783104ec7a1e 100755
--- a/litex_boards/targets/nereid.py
+++ b/litex_boards/targets/nereid.py
@@ -67,7 +67,6 @@ class BaseSoC(SoCCore):
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = CRG(platform, sys_clk_freq)
-        self.add_csr("crg")
 
         # DDR3 SDRAM -------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
diff --git a/litex_boards/targets/tagus.py b/litex_boards/targets/tagus.py
index 96903e41369a1c6649f71066b108266be6ad4e76..e716a85c17c0836958193572a58ad8f690e8dda4 100755
--- a/litex_boards/targets/tagus.py
+++ b/litex_boards/targets/tagus.py
@@ -70,7 +70,6 @@ class BaseSoC(SoCCore):
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = CRG(platform, sys_clk_freq)
-        self.add_csr("crg")
 
         # DDR3 SDRAM -------------------------------------------------------------------------------
         if not self.integrated_main_ram_size: