diff --git a/litex_boards/targets/colorlight_i5.py b/litex_boards/targets/colorlight_i5.py
index 0478a33a5e43bcec895fc6191a5e169f39c8d569..5e20cdcf4bb2dcaa43621d6f8f48758141fb5b47 100755
--- a/litex_boards/targets/colorlight_i5.py
+++ b/litex_boards/targets/colorlight_i5.py
@@ -21,7 +21,7 @@ from litex.build.lattice.trellis import trellis_args, trellis_argdict
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.builder import *
-from litex.soc.cores.video import VideoECP5HDMIPHY
+from litex.soc.cores.video import VideoHDMIPHY
 from litex.soc.cores.led import LedChaser
 
 from litex.soc.interconnect.csr import *
@@ -164,7 +164,7 @@ class BaseSoC(SoCCore):
 
         # Video ------------------------------------------------------------------------------------
         if with_video_terminal or with_video_framebuffer:
-            self.submodules.videophy = VideoECP5HDMIPHY(platform.request("gpdi"), clock_domain="hdmi")
+            self.submodules.videophy = VideoHDMIPHY(platform.request("gpdi"), clock_domain="hdmi")
             if with_video_terminal:
                 self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
             if with_video_framebuffer:
diff --git a/litex_boards/targets/litex_m2_baseboard.py b/litex_boards/targets/litex_m2_baseboard.py
index 330db1571f354632c9f39769fc1490f060c34072..2b717db279a177df65d296400a7f654a8866ad2e 100755
--- a/litex_boards/targets/litex_m2_baseboard.py
+++ b/litex_boards/targets/litex_m2_baseboard.py
@@ -19,7 +19,7 @@ from litex.build.lattice.trellis import trellis_args, trellis_argdict
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.builder import *
-from litex.soc.cores.video import VideoECP5HDMIPHY
+from litex.soc.cores.video import VideoHDMIPHY
 
 from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
 
@@ -92,7 +92,7 @@ class BaseSoC(SoCCore):
 
         # Video ------------------------------------------------------------------------------------
         if with_video_terminal:
-            self.submodules.videophy = VideoECP5HDMIPHY(platform.request("hdmi"), clock_domain="hdmi", pn_swap=["g", "b"])
+            self.submodules.videophy = VideoHDMIPHY(platform.request("hdmi"), clock_domain="hdmi", pn_swap=["g", "b"])
             self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi")
 
 # Build --------------------------------------------------------------------------------------------
diff --git a/litex_boards/targets/muselab_icesugar_pro.py b/litex_boards/targets/muselab_icesugar_pro.py
index 22cb8ec94e6e8217864c4b039054e64f56dfb773..60ddde2d1ff520dc1840b08978821f45427d51fe 100755
--- a/litex_boards/targets/muselab_icesugar_pro.py
+++ b/litex_boards/targets/muselab_icesugar_pro.py
@@ -21,7 +21,7 @@ from litex.build.lattice.trellis import trellis_args, trellis_argdict
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.builder import *
-from litex.soc.cores.video import VideoECP5HDMIPHY
+from litex.soc.cores.video import VideoHDMIPHY
 from litex.soc.cores.led import LedChaser
 
 from litex.soc.interconnect.csr import *
@@ -124,7 +124,7 @@ class BaseSoC(SoCCore):
 
         # Video ------------------------------------------------------------------------------------
         if with_video_terminal or with_video_framebuffer:
-            self.submodules.videophy = VideoECP5HDMIPHY(platform.request("gpdi"), clock_domain="hdmi")
+            self.submodules.videophy = VideoHDMIPHY(platform.request("gpdi"), clock_domain="hdmi")
             if with_video_terminal:
                 self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
             if with_video_framebuffer:
diff --git a/litex_boards/targets/radiona_ulx3s.py b/litex_boards/targets/radiona_ulx3s.py
index 36b36cd3a931c58493e86e14fcd218e8feb1a5e0..dd1acfdeb96bef94673445e410e3c9da8bfd9a6e 100755
--- a/litex_boards/targets/radiona_ulx3s.py
+++ b/litex_boards/targets/radiona_ulx3s.py
@@ -23,7 +23,7 @@ from litex.build.lattice.trellis import trellis_args, trellis_argdict
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.builder import *
-from litex.soc.cores.video import VideoECP5HDMIPHY
+from litex.soc.cores.video import VideoHDMIPHY
 from litex.soc.cores.led import LedChaser
 from litex.soc.cores.spi import SPIMaster
 from litex.soc.cores.gpio import GPIOOut
@@ -121,7 +121,7 @@ class BaseSoC(SoCCore):
 
         # Video ------------------------------------------------------------------------------------
         if with_video_terminal or with_video_framebuffer:
-            self.submodules.videophy = VideoECP5HDMIPHY(platform.request("gpdi"), clock_domain="hdmi")
+            self.submodules.videophy = VideoHDMIPHY(platform.request("gpdi"), clock_domain="hdmi")
             if with_video_terminal:
                 self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi")
             if with_video_framebuffer: