Commit 4831bc54 authored by mntmn's avatar mntmn

kernel: add new patches incl sai 48khz fix, pcie/lcdif fix, hdmi, sleep/wake fix

parent dea4a5c6
From 477d56dc76a0f7635c1b1272d525688d45571cda Mon Sep 17 00:00:00 2001
From: mntmn <lukas@mntmn.com>
Date: Tue, 24 Nov 2020 00:54:20 +0100
Subject: [PATCH 2/8] WIP: dcss: set the pixel clock to 70% for DSI
If DSI input and output have the same clock, there can be a race that
leads to the image desynchronizing horizontally.
TODO: Enable this only when feeding to DSI, not HDMI.
---
drivers/gpu/drm/imx/dcss/dcss-dtg.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/imx/dcss/dcss-dtg.c b/drivers/gpu/drm/imx/dcss/dcss-dtg.c
index 30de00540..fbd5914ac 100644
--- a/drivers/gpu/drm/imx/dcss/dcss-dtg.c
+++ b/drivers/gpu/drm/imx/dcss/dcss-dtg.c
@@ -221,7 +221,7 @@ void dcss_dtg_sync_set(struct dcss_dtg *dtg, struct videomode *vm)
vm->vactive - 1;
clk_disable_unprepare(dcss->pix_clk);
- clk_set_rate(dcss->pix_clk, vm->pixelclock);
+ clk_set_rate(dcss->pix_clk, (vm->pixelclock * 700)/1000);
clk_prepare_enable(dcss->pix_clk);
actual_clk = clk_get_rate(dcss->pix_clk);
@@ -406,4 +406,3 @@ bool dcss_dtg_vblank_irq_valid(struct dcss_dtg *dtg)
{
return !!(dcss_readl(dtg->base_reg + DCSS_DTG_INT_STATUS) & LINE1_IRQ);
}
-
--
2.28.0
From 32d8ea3eab4eb79431e3a9342449efcf3607a7c9 Mon Sep 17 00:00:00 2001
From: mntmn <lukas@mntmn.com>
Date: Tue, 24 Nov 2020 00:56:23 +0100
Subject: [PATCH 3/8] dcss: fix attaching to sn56dsi86 bridge
The sn56dsi86 DSI to eDP bridge driver does not support attaching
without a drm connector. This patch makes the attachment work. Required
for the display chain in MNT Reform 2.0.
---
drivers/gpu/drm/imx/dcss/dcss-kms.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/imx/dcss/dcss-kms.c b/drivers/gpu/drm/imx/dcss/dcss-kms.c
index 135a62366..4967f828b 100644
--- a/drivers/gpu/drm/imx/dcss/dcss-kms.c
+++ b/drivers/gpu/drm/imx/dcss/dcss-kms.c
@@ -82,6 +82,7 @@ static int dcss_kms_bridge_connector_init(struct dcss_kms_dev *kms)
struct drm_crtc *crtc = (struct drm_crtc *)&kms->crtc;
struct drm_panel *panel;
struct drm_bridge *bridge;
+ struct drm_connector_list_iter iter;
int ret;
ret = drm_of_find_panel_or_bridge(ddev->dev->of_node, 0, 0,
@@ -104,19 +105,19 @@ static int dcss_kms_bridge_connector_init(struct dcss_kms_dev *kms)
return ret;
}
- ret = drm_bridge_attach(encoder, bridge, NULL,
- DRM_BRIDGE_ATTACH_NO_CONNECTOR);
+ ret = drm_bridge_attach(encoder, bridge, NULL, 0);
if (ret < 0) {
dev_err(ddev->dev, "Unable to attach bridge %pOF\n",
bridge->of_node);
return ret;
}
- kms->connector = drm_bridge_connector_init(ddev, encoder);
- if (IS_ERR(kms->connector)) {
- dev_err(ddev->dev, "Unable to create bridge connector.\n");
- return PTR_ERR(kms->connector);
- }
+ /*
+ * This hack to look up the connector is copied from mxsfb.
+ */
+ drm_connector_list_iter_begin(ddev, &iter);
+ kms->connector = drm_connector_list_iter_next(&iter);
+ drm_connector_list_iter_end(&iter);
drm_connector_attach_encoder(kms->connector, encoder);
--
2.28.0
From b9b161fcc88ab6fa0642aa3f533be3e0aac6978b Mon Sep 17 00:00:00 2001
From: mntmn <lukas@mntmn.com>
Date: Thu, 28 May 2020 22:51:46 +0200
Subject: [PATCH] MNT Reform: imx8mq: add PHY_27M clock
---
drivers/clk/imx/clk-imx8mq.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index fdc68db68de5..a9e2d2f09864 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -25,7 +25,7 @@ static u32 share_count_sai6;
static u32 share_count_dcss;
static u32 share_count_nand;
-static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "dummy", "dummy", };
+static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "phy_27m", "dummy", };
static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
@@ -304,6 +304,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
hws[IMX8MQ_CLK_EXT2] = imx_obtain_fixed_clk_hw(np, "clk_ext2");
hws[IMX8MQ_CLK_EXT3] = imx_obtain_fixed_clk_hw(np, "clk_ext3");
hws[IMX8MQ_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4");
+ hws[IMX8MQ_CLK_PHY_27MHZ] = imx_clk_hw_fixed("phy_27m", 27000000);
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-anatop");
base = of_iomap(np, 0);
From 5bbfbc478adc68ae7e9fb1d5b0239d3ba93c8471 Mon Sep 17 00:00:00 2001
From: mntmn <lukas@mntmn.com>
Date: Thu, 28 May 2020 23:22:18 +0200
Subject: [PATCH] MNT Reform: imx8mq: add PHY_27M clock: missing define
---
include/dt-bindings/clock/imx8mq-clock.h | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h
index 9b8045d75b8b..29b86c579b40 100644
--- a/include/dt-bindings/clock/imx8mq-clock.h
+++ b/include/dt-bindings/clock/imx8mq-clock.h
@@ -431,6 +431,9 @@
#define IMX8MQ_CLK_A53_CORE 289
-#define IMX8MQ_CLK_END 290
+#define IMX8MQ_CLK_PHY_27MHZ 290
+
+#define IMX8MQ_CLK_END 291
+
#endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
--
2.26.2
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index f3d3d20d35d7..449af79e2640 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -27,9 +27,7 @@
FSL_SAI_CSR_FEIE)
static const unsigned int fsl_sai_rates[] = {
- 8000, 11025, 12000, 16000, 22050,
- 24000, 32000, 44100, 48000, 64000,
- 88200, 96000, 176400, 192000
+ 48000, 96000, 192000
};
static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
diff --git a/drivers/gpu/drm/mxsfb/mxsfb_kms.c b/drivers/gpu/drm/mxsfb/mxsfb_kms.c
index 3e1bb0aefb87..13128b6f2770 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_kms.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_kms.c
@@ -212,7 +212,7 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)
mxsfb_set_formats(mxsfb);
- clk_set_rate(mxsfb->clk, m->crtc_clock * 1000);
+ clk_set_rate(mxsfb->clk, m->crtc_clock * 660);
if (mxsfb->bridge && mxsfb->bridge->timings)
bus_flags = mxsfb->bridge->timings->input_bus_flags;
@@ -540,12 +540,44 @@ static const uint64_t mxsfb_modifiers[] = {
* Initialization
*/
+void imx8mq_pcie_qos_for_lcdif(void)
+{
+ void __iomem *qosc = ioremap(0x307f0000, 0x2100);
+ // clock and unlock QoSC registers
+ writel(0x0, qosc);
+ writel(0x1, qosc);
+ writel(0x0, qosc+0x60);
+
+ // limit number of outstanding transactions for PCIe1
+ writel(0x0, qosc+0x1000);
+ writel(0x1, qosc+0x1000);
+ writel(0x01010100, qosc+0x1050);
+ writel(0x01010100, qosc+0x1060);
+ writel(0x01010100, qosc+0x1070);
+ writel(0x1, qosc+0x1000);
+
+ // limit number of outstanding transactions for PCIe2
+ writel(0x0, qosc+0x2000);
+ writel(0x1, qosc+0x2000);
+ writel(0x01010100, qosc+0x2050);
+ writel(0x01010100, qosc+0x2060);
+ writel(0x01010100, qosc+0x2070);
+ writel(0x1, qosc+0x2000);
+
+ iounmap(qosc);
+}
+
int mxsfb_kms_init(struct mxsfb_drm_private *mxsfb)
{
struct drm_encoder *encoder = &mxsfb->encoder;
struct drm_crtc *crtc = &mxsfb->crtc;
int ret;
+ /*
+ FIXME Workaround to fix PCIe interfering with LCDIF refresh (MNT Reform)
+ */
+ imx8mq_pcie_qos_for_lcdif();
+
drm_plane_helper_add(&mxsfb->planes.primary,
&mxsfb_plane_primary_helper_funcs);
ret = drm_universal_plane_init(mxsfb->drm, &mxsfb->planes.primary, 1,
diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c
index 7031ef44de4f..9cba81b5050d 100644
--- a/drivers/irqchip/irq-imx-gpcv2.c
+++ b/drivers/irqchip/irq-imx-gpcv2.c
@@ -3,6 +3,7 @@
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*/
+#include <linux/arm-smccc.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/slab.h>
@@ -17,6 +18,13 @@
#define GPC_IMR1_CORE2 0x1c0
#define GPC_IMR1_CORE3 0x1d0
+#define FSL_SIP_GPC 0xC2000000
+#define FSL_SIP_CONFIG_GPC_MASK 0x00
+#define FSL_SIP_CONFIG_GPC_UNMASK 0x01
+#define FSL_SIP_CONFIG_GPC_SET_WAKE 0x02
+#define FSL_SIP_CONFIG_GPC_PM_DOMAIN 0x03
+#define FSL_SIP_CONFIG_GPC_SET_AFF 0x04
+#define FSL_SIP_CONFIG_GPC_CORE_WAKE 0x05
struct gpcv2_irqchip_data {
struct raw_spinlock rlock;
@@ -76,12 +84,17 @@ static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on)
unsigned int idx = d->hwirq / 32;
unsigned long flags;
u32 mask, val;
+ struct arm_smccc_res res;
raw_spin_lock_irqsave(&cd->rlock, flags);
mask = BIT(d->hwirq % 32);
val = cd->wakeup_sources[idx];
cd->wakeup_sources[idx] = on ? (val & ~mask) : (val | mask);
+
+ // save wakeup config in vendor tf-a
+ arm_smccc_smc(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_SET_WAKE, d->hwirq, on, 0, 0, 0, 0, &res);
+
raw_spin_unlock_irqrestore(&cd->rlock, flags);
/*
@@ -97,6 +110,7 @@ static void imx_gpcv2_irq_unmask(struct irq_data *d)
struct gpcv2_irqchip_data *cd = d->chip_data;
void __iomem *reg;
u32 val;
+ struct arm_smccc_res res;
raw_spin_lock(&cd->rlock);
reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
@@ -105,6 +119,10 @@ static void imx_gpcv2_irq_unmask(struct irq_data *d)
writel_relaxed(val, reg);
raw_spin_unlock(&cd->rlock);
+ // call into vendor tf-a
+ //arm_smccc_smc(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_UNMASK,
+ // d->hwirq, 0, 0, 0, 0, 0, &res);
+
irq_chip_unmask_parent(d);
}
@@ -113,12 +131,18 @@ static void imx_gpcv2_irq_mask(struct irq_data *d)
struct gpcv2_irqchip_data *cd = d->chip_data;
void __iomem *reg;
u32 val;
+ struct arm_smccc_res res;
raw_spin_lock(&cd->rlock);
reg = gpcv2_idx_to_reg(cd, d->hwirq / 32);
val = readl_relaxed(reg);
val |= BIT(d->hwirq % 32);
writel_relaxed(val, reg);
+
+ // call into vendor tf-a
+ //arm_smccc_smc(FSL_SIP_GPC, FSL_SIP_CONFIG_GPC_MASK,
+ // d->hwirq, 0, 0, 0, 0, 0, &res);
+
raw_spin_unlock(&cd->rlock);
irq_chip_mask_parent(d);
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