diff --git a/reform2-imx8mq/mkkernel.sh b/reform2-imx8mq/mkkernel.sh
index e4c2f51403f21231d7973ebf75f5a34c895f113f..1c3ac676e4743160899ac5e962b0c4fde8dc14a7 100755
--- a/reform2-imx8mq/mkkernel.sh
+++ b/reform2-imx8mq/mkkernel.sh
@@ -16,14 +16,13 @@ then
cd linux
git init
git remote add origin https://github.com/torvalds/linux.git
- # 5.7 release commit
- git fetch --depth 1 origin 3d77e6a8804abcc0504c904bd6e5cdf3a5cf8162
+ # temporary linux 5.9 commit
+ git fetch --depth 1 origin 6d28cf7dfede6cfca5119a0d415a6a447c68f3a0
git checkout FETCH_HEAD
cd ..
fi
cp ./template-kernel/*.dts ./linux/arch/arm64/boot/dts/freescale/
-cp ./template-kernel/*.dtsi ./linux/arch/arm64/boot/dts/freescale/
cp ./template-kernel/kernel-config ./linux/.config
cd linux
diff --git a/reform2-imx8mq/template-kernel/imx8mq-mnt-reform2.dts b/reform2-imx8mq/template-kernel/imx8mq-mnt-reform2.dts
index 6b2567d5f86658c003e53f12631a41da70d6a4df..1fcbaf27a351ae1636fe71becbbbed6a034a2066 100644
--- a/reform2-imx8mq/template-kernel/imx8mq-mnt-reform2.dts
+++ b/reform2-imx8mq/template-kernel/imx8mq-mnt-reform2.dts
@@ -6,82 +6,25 @@
/dts-v1/;
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pwm/pwm.h>
-#include <dt-bindings/usb/pd.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/leds/common.h>
+#include "dt-bindings/input/input.h"
+#include "dt-bindings/pwm/pwm.h"
+#include "dt-bindings/usb/pd.h"
+#include "dt-bindings/gpio/gpio.h"
#include "imx8mq.dtsi"
/ {
model = "MNT Reform 2";
compatible = "boundary,imx8mq-nitrogen8m_som", "fsl,imx8mq";
- memory@40000000 {
- device_type = "memory";
- reg = <0x00000000 0x40000000 0 0xc0000000>;
- };
-
- sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "wm8960-audio";
- simple-audio-card,format = "i2s";
- simple-audio-card,frame-master = <&dai_cpu_master>;
- simple-audio-card,bitclock-master = <&dai_cpu_master>;
-
- status = "okay";
-
- simple-audio-card,widgets =
- "Microphone", "Mic Jack",
- "Line", "Line In",
- "Line", "Line Out",
- "Speaker", "Speaker",
- "Headphone", "Headphone Jack";
- simple-audio-card,routing =
- "Headphone Jack", "HP_L",
- "Headphone Jack", "HP_R",
- "Speaker", "SPK_LP",
- "Speaker", "SPK_LN",
- "Speaker", "SPK_RP",
- "Speaker", "SPK_RN",
- "LINPUT1", "Mic Jack",
- "LINPUT3", "Mic Jack",
- "RINPUT1", "Mic Jack",
- "RINPUT2", "Mic Jack";
-
- dai_cpu_master: simple-audio-card,cpu {
- sound-dai = <&sai2>;
- };
-
- dailink0: simple-audio-card,codec {
- sound-dai = <&codec>;
- };
+ chosen {
+ stdout-path = "serial0:115200n8";
};
- backlight: backlight {
- compatible = "pwm-backlight";
- pwms = <&pwm2 0 10000>;
- enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
- brightness-levels = <0 32 64 128 160 200 255>;
- default-brightness-level = <6>;
- status = "okay";
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000 0 0xc0000000>; // TODO: confirm what this means
};
- panel: panel {
- compatible = "innolux,n125hce-gn1", "simple-panel";
- // FIXME: why not?
- //backlight = <&backlight>;
- status = "okay";
- no-hpd;
- power = <®_vref_3v3>;
-
- port@0 {
- panel_in: endpoint {
- remote-endpoint = <&edp_bridge_out>;
- };
- };
- };
-
reg_vref_0v9: regulator-vref-0v9 {
compatible = "regulator-fixed";
regulator-name = "vref-0v9";
@@ -97,7 +40,7 @@
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
-
+
reg_vref_1v8: regulator-vref-1v8 {
compatible = "regulator-fixed";
regulator-name = "vref-1v8";
@@ -130,15 +73,61 @@
regulator-always-on;
};
- reg_usdhc2_vmmc: regulator-vsd-3v3 {
- pinctrl-names = "default";
- compatible = "regulator-fixed";
- regulator-name = "3V3_SD";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm2 0 10000>;
+ enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+ brightness-levels = <0 32 64 128 160 200 255>; // TODO determine useful levels
+ default-brightness-level = <6>;
};
-
+
+ panel {
+ compatible = "innolux,n125hce-gn1", "simple-panel";
+ power = <®_vref_3v3>;
+ backlight = <&backlight>;
+ no-hpd; // TODO: can we leave it out?
+
+ port@0 {
+ panel_in: endpoint {
+ remote-endpoint = <&edp_bridge_out>;
+ };
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "wm8960-audio";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,frame-master = <&dai_cpu_master>;
+ simple-audio-card,bitclock-master = <&dai_cpu_master>;
+
+ simple-audio-card,widgets =
+ "Microphone", "Mic Jack",
+ "Line", "Line In",
+ "Line", "Line Out",
+ "Speaker", "Speaker",
+ "Headphone", "Headphone Jack";
+ simple-audio-card,routing =
+ "Headphone Jack", "HP_L",
+ "Headphone Jack", "HP_R",
+ "Speaker", "SPK_LP",
+ "Speaker", "SPK_LN",
+ "Speaker", "SPK_RP",
+ "Speaker", "SPK_RN",
+ "Mic Jack", "MICB",
+ "LINPUT1", "Mic Jack",
+ "LINPUT2", "Line In",
+ "RINPUT2", "Line In";
+
+ dai_cpu_master: simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ };
+
+ dailink0: simple-audio-card,codec {
+ sound-dai = <&codec>;
+ };
+ };
+
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -150,34 +139,207 @@
#clock-cells = <0>;
clock-frequency = <100000000>;
};
+};
+
+&A53_0 {
+ cpu-supply = <®_arm_dram>;
+};
+
+&A53_1 {
+ cpu-supply = <®_arm_dram>;
+};
- /*usb_hub_reset {
- compatible = "gpio-leds";
- status = "okay";
+&A53_2 {
+ cpu-supply = <®_arm_dram>;
+};
- // The TUSB8041 USB Hub on the motherboard needs to get
- // a reset pulse at boot. This is what we do here (200ms).
- led-0 {
- function = LED_FUNCTION_BOOT;
- linux,default-trigger = "one-shot";
- led-pattern = "0 200";
- gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+&A53_3 {
+ cpu-supply = <®_arm_dram>;
+};
+
+// TODO: check AUDIO_PLL1 in librem5-devkit
+
+&dphy {
+ status = "okay";
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <4>;
+ interrupts = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; // TODO: useful?
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ // I2C Mux on Nitrogen8M_SOM
+ i2cmux@70 {
+ compatible = "nxp,pca9546";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_pca9546>;
+ reg = <0x70>;
+ reset-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c1a: i2c1@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ // Regulator on Nitrogen8M_SOM
+ reg_arm_dram: fan53555@60 {
+ compatible = "fcs,fan53555";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_arm_dram>;
+ reg = <0x60>;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-ramp-delay = <8000>;
+ regulator-always-on;
+ vsel-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ i2c1b: i2c1@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ // Regulator on Nitrogen8M_SOM
+ reg_dram_1p1v: fan53555@60 {
+ compatible = "fcs,fan53555";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_dram_1p1v>;
+ reg = <0x60>;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-ramp-delay = <8000>;
+ regulator-always-on;
+ vsel-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ i2c1c: i2c1@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ // Regulator on Nitrogen8M_SOM
+ reg_soc_gpu_vpu: fan53555@60 {
+ compatible = "fcs,fan53555";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>;
+ reg = <0x60>;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-ramp-delay = <8000>;
+ regulator-always-on;
+ vsel-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+ };
};
- };*/
+
+ // No peripheral connected, available on DSI connector
+ i2c1d: i2c1@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
};
+// No peripheral connected, available on CSI connector
+&i2c2 {
+ status = "disabled";
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+ // Audio chip on motherboard
+ codec: wm8960@1a {
+ compatible = "wlf,wm8960";
+ reg = <0x1a>;
+ clocks = <&clk IMX8MQ_CLK_SAI2>;
+ clock-names = "mclk";
+ #sound-dai-cells = <0>;
+ };
+
+ // Realtime clock chip on motherboard
+ pcf8523: pcf8523@68 {
+ compatible = "nxp,pcf8523";
+ reg = <0x68>;
+ };
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ // TODO: DSI to eDP converter on motherboard
+ edp_bridge: sn65dsi86@2c {
+ compatible = "ti,sn65dsi86";
+ reg = <0x2c>;
+ enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ // TODO: uncomment as soon as nwl-dsi and DCSS are upstreamed
+ //edp_bridge_in: endpoint {
+ // remote-endpoint = <&dsi_out>;
+ //};
+ };
+
+ port@1 {
+ reg = <1>;
+
+ edp_bridge_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ };
+};
+
+// TODO: add external pin numbers
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
- //MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* Pin 105 */
- MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 // FIXME what's this?
- MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x56 // pullup usb hub reset (0x40)
+ MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 // WL_EN on Nitrogen8M_SOM, pin 38, goes to /EN input of SN65DSI86
+ MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x56 // TODO: check pullup of usb hub reset on the board (0x40)
>;
};
+ // TODO: link to manual page to describe magic values
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
@@ -194,9 +356,7 @@
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
-#define GP_FEC1_RESET <&gpio1 9 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
-#define GPIRQ_FEC1_PHY <&gpio1 11 IRQ_TYPE_LEVEL_LOW>
MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59
>;
};
@@ -207,10 +367,9 @@
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
-
+
pinctrl_i2c1_pca9546: i2c1-pca9546grp {
fsl,pins = <
-#define GP_I2C1_PCA9546_RESET <&gpio1 4 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x46
>;
};
@@ -236,23 +395,12 @@
>;
};
- // DSE = 45ohms, SRE = FAST, LVTTL = 1
- pinctrl_ecspi2: ecspi2grp {
- fsl.pins = <
- MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x116
- MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x116
- MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x116
- MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x116
- >;
- };
-
pinctrl_pcie0: pcie0grp {
fsl,pins = <
-#define GP_PCIE0_RESET <&gpio5 7 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x16
>;
};
-
+
pinctrl_pcie1: pcie1grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x16
@@ -271,6 +419,7 @@
>;
};
+ // Backlight
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x16
@@ -279,35 +428,22 @@
pinctrl_reg_arm_dram: reg-arm-dram {
fsl,pins = <
-#define GP_ARM_DRAM_VSEL <&gpio3 24 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16
>;
};
pinctrl_reg_dram_1p1v: reg-dram-1p1v {
fsl,pins = <
-#define GP_DRAM_1P1_VSEL <&gpio2 11 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x16
>;
};
pinctrl_reg_soc_gpu_vpu: reg-soc-gpu-vpu {
fsl,pins = <
-#define GP_SOC_GPU_VPU_VSEL <&gpio2 20 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x16
>;
};
- /*pinctrl_sai1: sai1grp {
- fsl,pins = <
- MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6
- MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6
- MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6
- MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6
- MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6
- >;
- };*/
-
pinctrl_sai2: sai2grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 /* Pin 166 */
@@ -320,16 +456,6 @@
>;
};
- pinctrl_sai3: sai3grp {
- fsl,pins = <
- /* Bluetooth PCM */
- MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
- MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
- MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
- MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
- >;
- };
-
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45
@@ -348,31 +474,9 @@
fsl,pins = <
MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x45
MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x45
- MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x45
- MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x45
>;
};
- pinctrl_uart4: uart4grp {
- fsl,pins = <
- MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x45
- MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x45
- >;
- };
-
- /*pinctrl_usb3_0: usb3-0grp {
- fsl,pins = <
- MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x16
- >;
- };
-
- pinctrl_usb3_1: usb3-1grp {
- fsl,pins = <
-#define GP_USB3_1_HUB_RESET <&gpio1 14 GPIO_ACTIVE_LOW>
- MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
- >;
- };*/
-
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
@@ -385,16 +489,11 @@
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
-#if 0
- MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
-#else
-#define GP_EMMC_RESET <&gpio2 10 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
-#endif
>;
};
- pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
@@ -409,7 +508,7 @@
>;
};
- pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
@@ -431,12 +530,11 @@
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
- MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
- //MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x03
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc
>;
};
- pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x0d
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
@@ -447,7 +545,7 @@
>;
};
- pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x1e
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xce
@@ -465,174 +563,15 @@
};
};
-&wdog1 {
- status = "okay";
-};
-
-&wdog2 {
- status = "okay";
-};
-
-&wdog3 {
- status = "okay";
-};
-
-&fec1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_fec1>;
- phy-mode = "rgmii-id";
- phy-handle = <ðphy0>;
- //phy-reset-gpios = GP_FEC1_RESET;
- //phy-reset-duration = <10>;
- fsl,magic-packet;
- status = "okay";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@4 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <4>;
- //at803x,vddio-1p8v;
- interrupts = GPIRQ_FEC1_PHY;
- //max-speed = <100>;
- };
- };
-};
-
-&i2c1 {
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- status = "okay";
-
- // I2C Mux on Nitrogen8M_SOM
- i2cmux@70 {
- compatible = "pca9546";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1_pca9546>;
- reg = <0x70>;
- reset-gpios = GP_I2C1_PCA9546_RESET;
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2c1a: i2c1@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c1b: i2c1@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c1c: i2c1@2 {
- reg = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- i2c1d: i2c1@3 {
- reg = <3>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-};
-
-&i2c1a {
- // Regulator on Nitrogen8M_SOM
- reg_arm_dram: fan53555@60 {
- compatible = "fcs,fan53555";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_arm_dram>;
- reg = <0x60>;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1000000>;
- regulator-ramp-delay = <8000>;
- regulator-always-on;
- vsel-gpios = GP_ARM_DRAM_VSEL;
- };
-};
-
-&A53_0 {
- cpu-supply = <®_arm_dram>;
-};
-
-&A53_1 {
- cpu-supply = <®_arm_dram>;
-};
-
-&A53_2 {
- cpu-supply = <®_arm_dram>;
-};
-
-&A53_3 {
- cpu-supply = <®_arm_dram>;
-};
-
-&i2c1b {
- // Regulator on Nitrogen8M_SOM
- reg_dram_1p1v: fan53555@60 {
- compatible = "fcs,fan53555";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_dram_1p1v>;
- reg = <0x60>;
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-ramp-delay = <8000>;
- regulator-always-on;
- vsel-gpios = GP_DRAM_1P1_VSEL;
- };
-};
-
-&i2c1c {
- // Regulator on Nitrogen8M_SOM
- reg_soc_gpu_vpu: fan53555@60 {
- compatible = "fcs,fan53555";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>;
- reg = <0x60>;
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1000000>;
- regulator-ramp-delay = <8000>;
- regulator-always-on;
- vsel-gpios = GP_SOC_GPU_VPU_VSEL;
- };
-};
-
-&pcie0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pcie0>;
- reset-gpio = GP_PCIE0_RESET;
-
- clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
- <&clk IMX8MQ_CLK_PCIE1_AUX>,
- <&clk IMX8MQ_CLK_PCIE1_PHY>,
- <&pcie0_refclk>;
-
- clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
-
- ext_osc = <0>;
- status = "okay";
-};
-
&pcie1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie1>;
reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>;
-
clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
<&clk IMX8MQ_CLK_PCIE2_AUX>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&pcie1_refclk>;
-
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
-
- ext_osc = <1>;
status = "okay";
};
@@ -658,281 +597,88 @@
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
- status = "okay";
-
assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL2_OUT>;
- assigned-clock-rates = <12288000>;
+ assigned-clock-rates = <12288000>; // TODO check if it works without corresponding patch
+ status = "okay";
};
-&uart1 { /* console */
+// Don't use i.MX8M internal RTC because we have a dedicated one
+&snvs_rtc {
+ status = "disabled";
+};
+
+// Console
+&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
- assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
- assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
status = "okay";
};
+// Auxiliary serial port on motherboard
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
- assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
- assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
status = "okay";
};
+// connected to LPC11U24 chip on the motherboard
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
- assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
- assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
status = "okay";
};
-&usb3_phy0 {
- vbus-supply = <®_vref_5v>;
+&usb_dwc3_0 {
status = "okay";
+ dr_mode = "host";
};
-&usb_dwc3_0 {
+&usb_dwc3_1 {
status = "okay";
dr_mode = "host";
};
-&usb3_phy1 {
+&usb3_phy0 {
vbus-supply = <®_vref_5v>;
status = "okay";
};
-&usb_dwc3_1 {
+&usb3_phy1 {
+ vbus-supply = <®_vref_5v>;
status = "okay";
- dr_mode = "host";
};
// eMMC on Nitrogen8M_SOM
+// TODO: check IMX8MQ_CLK_USDHC1 rate
&usdhc1 {
- bus-width = <4>;
- //fsl,strobe-dll-delay-target = <5>;
- //fsl,tuning-start-tap = <63>;
- //fsl,tuning-step = <2>;
- no-mmc-hs400;
+ bus-width = <8>; // TODO verify
+ no-mmc-hs400; // TODO verify
non-removable;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
status = "okay";
- //cd-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
- //vmmc-supply = <®_vref_1v8>;
- //vqmmc-1-8-v;
};
// SD Card on motherboard
+// TODO: check IMX8MQ_CLK_USDHC2 rate
+// TODO: check keep-power-in-suspend, cap-sdio-irq
&usdhc2 {
bus-width = <4>;
- // doesn't seem to make any difference
- //fsl,tuning-start-tap = <32>;
-
- // 1 can make tuning fail, 2 works on some cards, 3 same, 5 same
- //fsl,tuning-step = <2>;
-
- // 1 = no difference, 16 = no difference, 128 = no difference
- //fsl,delay-line = <0>;
-
- // this makes microSD cards stop working
- no-1-8-v;
-
- // changing these around breaks tuning
+ no-1-8-v; // We don't support 1.8V signaling
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
- status = "okay";
vmmc-supply = <®_vref_3v3>;
- //no-sd-uhs-sdr104;
-
- //assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
- //assigned-clock-rates = <200000000>;
-};
-
-&hdmi {
- compatible = "cdn,imx8mq-hdmi";
- lane-mapping = <0xe4>; // 0=0, 1=1, 2=2, 3=3 (no swapping)
- status = "okay";
-
- port@1 {
- hdmi_in: endpoint {
- remote-endpoint = <&dcss_out>;
- };
- };
-};
-
-// Note: don't forget to adjust the clock factor in dcss-crtc.c!
-&dcss {
- status = "okay";
-
- clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
- <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
- <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
- <&clk IMX8MQ_VIDEO2_PLL_OUT>, // HDMI
- <&clk IMX8MQ_CLK_DC_PIXEL>, // DSI
- <&clk IMX8MQ_CLK_DISP_DTRC>,
- <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>,
- <&clk IMX8MQ_CLK_PHY_27MHZ>;
- clock-names = "apb", "axi", "rtrm", "pix", "pix2", "dtrc", "pll_src", "pll_phy_ref";
-
- assigned-clocks =
- <&clk IMX8MQ_CLK_DC_PIXEL>,
- <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
- <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
- <&clk IMX8MQ_CLK_DISP_AXI>,
- <&clk IMX8MQ_CLK_DISP_RTRM>;
- //<&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>;
-
- assigned-clock-parents =
- <&clk IMX8MQ_VIDEO_PLL1_OUT>,
- <&clk IMX8MQ_VIDEO_PLL1>,
- <&clk IMX8MQ_CLK_25M>, // 27M makes the internal display flicker!
- <&clk IMX8MQ_SYS1_PLL_800M>,
- <&clk IMX8MQ_SYS1_PLL_800M>;
- //<&clk IMX8MQ_CLK_27M>; // this freezes with IMX8MQ_CLK_PHY_27MHZ IMX8MQ_CLK_27M
- assigned-clock-rates =
- <594000000>,
- <0>,
- <0>,
- <800000000>,
- <400000000>;
-
- port@0 {
- reg = <0>;
- dcss_out_dsi: endpoint {
- remote-endpoint = <&mipi_dsi_in>;
- };
- };
-
- port@1 {
- reg = <1>;
- dcss_out: endpoint {
- //remote-endpoint = <&mipi_dsi_in>;
- remote-endpoint = <&hdmi_in>;
- };
- };
-};
-
-// LCDIF is not used, but has to be active or DCSS (or DSI?) won't work
-&lcdif {
- status = "okay";
-
- /*port@0 {
- lcdif_mipi_dsi: endpoint {
- remote-endpoint = <&mipi_dsi_in>;
- };
- };*/
-};
-
-&dphy {
status = "okay";
};
-&mipi_dsi {
- status = "okay";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
-
- mipi_dsi_in: endpoint@1 { // @1 for dcss?
- reg = <1>;
- remote-endpoint = <&dcss_out_dsi>;
- //reg = <0>;
- //remote-endpoint = <&lcdif_mipi_dsi>;
- };
- };
- port@1 {
- reg = <1>;
- dsi_out: endpoint {
- remote-endpoint = <&edp_bridge_in>;
- };
- };
- };
-};
-
-// we use our own RTC instead
-&snvs_rtc {
- status = "disabled";
-};
-
-&i2c3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3>;
- status = "okay";
-
- // Audio chip on motherboard
- codec: wm8960@1a {
- compatible = "wlf,wm8960";
- reg = <0x1a>;
- clocks = <&clk IMX8MQ_CLK_SAI2>;
- clock-names = "mclk";
- #sound-dai-cells = <0>;
-
- AVDD-supply = <®_vref_3v3>;
- HPVDD-supply = <®_vref_3v3>;
- DCVDD-supply = <®_vref_3v3>;
- DBVDD-supply = <®_vref_3v3>;
- };
-
- // Realtime clock chip on motherboard
- pcf8523: pcf8523@68 {
- compatible = "nxp,pcf8523";
- reg = <0x68>;
- status = "okay";
- };
-};
-
-&i2c4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c4>;
- status = "okay";
-
- // DSI to eDP converter on motherboard
- edp_bridge: sn65dsi86@2c {
- compatible = "ti,sn65dsi86";
- reg = <0x2c>;
- status = "okay";
- enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- edp_bridge_in: endpoint {
- remote-endpoint = <&dsi_out>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- edp_bridge_out: endpoint {
- //data-lanes = <2 1 3 0>;
- //lane-polarities = <0 1 0 1>;
- remote-endpoint = <&panel_in>;
- };
- };
- };
- };
-};
-
-&ecspi2 {
+&wdog1 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi2>;
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output; // TODO read in driver what this means
status = "okay";
};
diff --git a/reform2-imx8mq/template-kernel/imx8mq.dtsi b/reform2-imx8mq/template-kernel/imx8mq.dtsi
deleted file mode 100644
index 36af4f6ce9e793daed695bb449e61aff1b01ed4d..0000000000000000000000000000000000000000
--- a/reform2-imx8mq/template-kernel/imx8mq.dtsi
+++ /dev/null
@@ -1,1313 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2017 NXP
- * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
- */
-
-#include <dt-bindings/clock/imx8mq-clock.h>
-#include <dt-bindings/power/imx8mq-power.h>
-#include <dt-bindings/reset/imx8mq-reset.h>
-#include <dt-bindings/gpio/gpio.h>
-#include "dt-bindings/input/input.h"
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/thermal/thermal.h>
-#include "imx8mq-pinfunc.h"
-
-/ {
- interrupt-parent = <&gpc>;
-
- #address-cells = <2>;
- #size-cells = <2>;
-
- aliases {
- gpio0 = &gpio1;
- gpio1 = &gpio2;
- gpio2 = &gpio3;
- gpio3 = &gpio4;
- gpio4 = &gpio5;
- i2c0 = &i2c1;
- i2c1 = &i2c2;
- i2c2 = &i2c3;
- i2c3 = &i2c4;
- serial0 = &uart1;
- serial1 = &uart2;
- serial2 = &uart3;
- serial3 = &uart4;
- spi0 = &ecspi1;
- spi1 = &ecspi2;
- spi2 = &ecspi3;
- };
-
- ckil: clock-ckil {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "ckil";
- };
-
- osc_25m: clock-osc-25m {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- clock-output-names = "osc_25m";
- };
-
- osc_27m: clock-osc-27m {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <27000000>;
- clock-output-names = "osc_27m";
- };
-
- clk_ext1: clock-ext1 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <133000000>;
- clock-output-names = "clk_ext1";
- };
-
- clk_ext2: clock-ext2 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <133000000>;
- clock-output-names = "clk_ext2";
- };
-
- clk_ext3: clock-ext3 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <133000000>;
- clock-output-names = "clk_ext3";
- };
-
- clk_ext4: clock-ext4 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency= <133000000>;
- clock-output-names = "clk_ext4";
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- A53_0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x0>;
- clock-latency = <61036>; /* two CLK32 periods */
- clocks = <&clk IMX8MQ_CLK_ARM>;
- enable-method = "psci";
- next-level-cache = <&A53_L2>;
- operating-points-v2 = <&a53_opp_table>;
- #cooling-cells = <2>;
- nvmem-cells = <&cpu_speed_grade>;
- nvmem-cell-names = "speed_grade";
- };
-
- A53_1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x1>;
- clock-latency = <61036>; /* two CLK32 periods */
- clocks = <&clk IMX8MQ_CLK_ARM>;
- enable-method = "psci";
- next-level-cache = <&A53_L2>;
- operating-points-v2 = <&a53_opp_table>;
- #cooling-cells = <2>;
- };
-
- A53_2: cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x2>;
- clock-latency = <61036>; /* two CLK32 periods */
- clocks = <&clk IMX8MQ_CLK_ARM>;
- enable-method = "psci";
- next-level-cache = <&A53_L2>;
- operating-points-v2 = <&a53_opp_table>;
- #cooling-cells = <2>;
- };
-
- A53_3: cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a53";
- reg = <0x3>;
- clock-latency = <61036>; /* two CLK32 periods */
- clocks = <&clk IMX8MQ_CLK_ARM>;
- enable-method = "psci";
- next-level-cache = <&A53_L2>;
- operating-points-v2 = <&a53_opp_table>;
- #cooling-cells = <2>;
- };
-
- A53_L2: l2-cache0 {
- compatible = "cache";
- };
- };
-
- a53_opp_table: opp-table {
- compatible = "operating-points-v2";
- opp-shared;
-
- opp-800000000 {
- opp-hz = /bits/ 64 <800000000>;
- opp-microvolt = <900000>;
- /* Industrial only */
- opp-supported-hw = <0xf>, <0x4>;
- clock-latency-ns = <150000>;
- opp-suspend;
- };
-
- opp-1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <900000>;
- /* Consumer only */
- opp-supported-hw = <0xe>, <0x3>;
- clock-latency-ns = <150000>;
- opp-suspend;
- };
-
- opp-1300000000 {
- opp-hz = /bits/ 64 <1300000000>;
- opp-microvolt = <1000000>;
- opp-supported-hw = <0xc>, <0x4>;
- clock-latency-ns = <150000>;
- opp-suspend;
- };
-
- opp-1500000000 {
- opp-hz = /bits/ 64 <1500000000>;
- opp-microvolt = <1000000>;
- opp-supported-hw = <0x8>, <0x3>;
- clock-latency-ns = <150000>;
- opp-suspend;
- };
- };
-
- pmu {
- compatible = "arm,cortex-a53-pmu";
- interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
- };
-
- psci {
- compatible = "arm,psci-1.0";
- method = "smc";
- };
-
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <250>;
- polling-delay = <2000>;
- thermal-sensors = <&tmu 0>;
-
- trips {
- cpu_alert: cpu-alert {
- temperature = <80000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- cpu-crit {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&cpu_alert>;
- cooling-device =
- <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
-
- gpu-thermal {
- polling-delay-passive = <250>;
- polling-delay = <2000>;
- thermal-sensors = <&tmu 1>;
-
- trips {
- gpu_alert: gpu-alert {
- temperature = <80000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- gpu-crit {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&gpu_alert>;
- cooling-device =
- <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
-
- vpu-thermal {
- polling-delay-passive = <250>;
- polling-delay = <2000>;
- thermal-sensors = <&tmu 2>;
-
- trips {
- vpu-crit {
- temperature = <90000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
- <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
- <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
- interrupt-parent = <&gic>;
- arm,no-tick-in-suspend;
- };
-
- soc@0 {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x0 0x3e000000>;
- dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
-
- bus@30000000 { /* AIPS1 */
- compatible = "fsl,aips-bus", "simple-bus";
- reg = <0x301f0000 0x10000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x30000000 0x30000000 0x400000>;
-
- sai1: sai@30010000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx8mq-sai";
- reg = <0x30010000 0x10000>;
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_SAI1_IPG>,
- <&clk IMX8MQ_CLK_SAI1_ROOT>,
- <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
- clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- sai6: sai@30030000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx8mq-sai";
- reg = <0x30030000 0x10000>;
- interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_SAI6_IPG>,
- <&clk IMX8MQ_CLK_SAI6_ROOT>,
- <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
- clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- sai5: sai@30040000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx8mq-sai";
- reg = <0x30040000 0x10000>;
- interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_SAI5_IPG>,
- <&clk IMX8MQ_CLK_SAI5_ROOT>,
- <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
- clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- sai4: sai@30050000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx8mq-sai";
- reg = <0x30050000 0x10000>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_SAI4_IPG>,
- <&clk IMX8MQ_CLK_SAI4_ROOT>,
- <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
- clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- gpio1: gpio@30200000 {
- compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
- reg = <0x30200000 0x10000>;
- interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-ranges = <&iomuxc 0 10 30>;
- };
-
- gpio2: gpio@30210000 {
- compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
- reg = <0x30210000 0x10000>;
- interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-ranges = <&iomuxc 0 40 21>;
- };
-
- gpio3: gpio@30220000 {
- compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
- reg = <0x30220000 0x10000>;
- interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-ranges = <&iomuxc 0 61 26>;
- };
-
- gpio4: gpio@30230000 {
- compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
- reg = <0x30230000 0x10000>;
- interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-ranges = <&iomuxc 0 87 32>;
- };
-
- gpio5: gpio@30240000 {
- compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
- reg = <0x30240000 0x10000>;
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-ranges = <&iomuxc 0 119 30>;
- };
-
- tmu: tmu@30260000 {
- compatible = "fsl,imx8mq-tmu";
- reg = <0x30260000 0x10000>;
- interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_TMU_ROOT>;
- little-endian;
- fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
- fsl,tmu-calibration = <0x00000000 0x00000023
- 0x00000001 0x00000029
- 0x00000002 0x0000002f
- 0x00000003 0x00000035
- 0x00000004 0x0000003d
- 0x00000005 0x00000043
- 0x00000006 0x0000004b
- 0x00000007 0x00000051
- 0x00000008 0x00000057
- 0x00000009 0x0000005f
- 0x0000000a 0x00000067
- 0x0000000b 0x0000006f
-
- 0x00010000 0x0000001b
- 0x00010001 0x00000023
- 0x00010002 0x0000002b
- 0x00010003 0x00000033
- 0x00010004 0x0000003b
- 0x00010005 0x00000043
- 0x00010006 0x0000004b
- 0x00010007 0x00000055
- 0x00010008 0x0000005d
- 0x00010009 0x00000067
- 0x0001000a 0x00000070
-
- 0x00020000 0x00000017
- 0x00020001 0x00000023
- 0x00020002 0x0000002d
- 0x00020003 0x00000037
- 0x00020004 0x00000041
- 0x00020005 0x0000004b
- 0x00020006 0x00000057
- 0x00020007 0x00000063
- 0x00020008 0x0000006f
-
- 0x00030000 0x00000015
- 0x00030001 0x00000021
- 0x00030002 0x0000002d
- 0x00030003 0x00000039
- 0x00030004 0x00000045
- 0x00030005 0x00000053
- 0x00030006 0x0000005f
- 0x00030007 0x00000071>;
- #thermal-sensor-cells = <1>;
- };
-
- wdog1: watchdog@30280000 {
- compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
- reg = <0x30280000 0x10000>;
- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
- status = "disabled";
- };
-
- wdog2: watchdog@30290000 {
- compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
- reg = <0x30290000 0x10000>;
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
- status = "disabled";
- };
-
- wdog3: watchdog@302a0000 {
- compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
- reg = <0x302a0000 0x10000>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
- status = "disabled";
- };
-
- sdma2: sdma@302c0000 {
- compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
- reg = <0x302c0000 0x10000>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>,
- <&clk IMX8MQ_CLK_SDMA2_ROOT>;
- clock-names = "ipg", "ahb";
- #dma-cells = <3>;
- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
- };
-
- lcdif: lcd-controller@30320000 {
- compatible = "fsl,imx8mq-lcdif", "fsl,imx28-lcdif";
- reg = <0x30320000 0x10000>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
- clock-names = "pix";
- assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
- <&clk IMX8MQ_VIDEO_PLL1_BYPASS>,
- <&clk IMX8MQ_CLK_LCDIF_PIXEL>,
- <&clk IMX8MQ_VIDEO_PLL1>;
- assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
- <&clk IMX8MQ_VIDEO_PLL1>,
- <&clk IMX8MQ_VIDEO_PLL1_OUT>;
- assigned-clock-rates = <0>, <0>, <0>, <594000000>;
- status = "disabled";
- };
-
- iomuxc: pinctrl@30330000 {
- compatible = "fsl,imx8mq-iomuxc";
- reg = <0x30330000 0x10000>;
- };
-
- iomuxc_gpr: syscon@30340000 {
- compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr",
- "syscon", "simple-mfd";
- reg = <0x30340000 0x10000>;
-
- mux: mux-controller {
- compatible = "mmio-mux";
- #mux-control-cells = <1>;
- mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
- };
- };
-
- ocotp: ocotp-ctrl@30350000 {
- compatible = "fsl,imx8mq-ocotp", "syscon";
- reg = <0x30350000 0x10000>;
- clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- cpu_speed_grade: speed-grade@10 {
- reg = <0x10 4>;
- };
- };
-
- anatop: syscon@30360000 {
- compatible = "fsl,imx8mq-anatop", "syscon";
- reg = <0x30360000 0x10000>;
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- snvs: snvs@30370000 {
- compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
- reg = <0x30370000 0x10000>;
-
- snvs_rtc: snvs-rtc-lp{
- compatible = "fsl,sec-v4.0-mon-rtc-lp";
- regmap =<&snvs>;
- offset = <0x34>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
- clock-names = "snvs-rtc";
- };
-
- snvs_pwrkey: snvs-powerkey {
- compatible = "fsl,sec-v4.0-pwrkey";
- regmap = <&snvs>;
- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>;
- clock-names = "snvs-pwrkey";
- linux,keycode = <KEY_POWER>;
- wakeup-source;
- status = "disabled";
- };
- };
-
- clk: clock-controller@30380000 {
- compatible = "fsl,imx8mq-ccm";
- reg = <0x30380000 0x10000>;
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- #clock-cells = <1>;
- clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
- <&clk_ext1>, <&clk_ext2>,
- <&clk_ext3>, <&clk_ext4>;
- clock-names = "ckil", "osc_25m", "osc_27m",
- "clk_ext1", "clk_ext2",
- "clk_ext3", "clk_ext4";
- assigned-clocks = <&clk IMX8MQ_CLK_NOC>;
- assigned-clock-rates = <800000000>;
- };
-
- src: reset-controller@30390000 {
- compatible = "fsl,imx8mq-src", "syscon";
- reg = <0x30390000 0x10000>;
- #reset-cells = <1>;
- };
-
- gpc: gpc@303a0000 {
- compatible = "fsl,imx8mq-gpc";
- reg = <0x303a0000 0x10000>;
- interrupt-parent = <&gic>;
- interrupt-controller;
- #interrupt-cells = <3>;
-
- pgc {
- #address-cells = <1>;
- #size-cells = <0>;
-
- pgc_mipi: power-domain@0 {
- #power-domain-cells = <0>;
- reg = <IMX8M_POWER_DOMAIN_MIPI>;
- };
-
- /*
- * As per comment in ATF source code:
- *
- * PCIE1 and PCIE2 share the
- * same reset signal, if we
- * power down PCIE2, PCIE1
- * will be held in reset too.
- *
- * So instead of creating two
- * separate power domains for
- * PCIE1 and PCIE2 we create a
- * link between both and use
- * it as a shared PCIE power
- * domain.
- */
- pgc_pcie: power-domain@1 {
- #power-domain-cells = <0>;
- reg = <IMX8M_POWER_DOMAIN_PCIE1>;
- power-domains = <&pgc_pcie2>;
- };
-
- pgc_otg1: power-domain@2 {
- #power-domain-cells = <0>;
- reg = <IMX8M_POWER_DOMAIN_USB_OTG1>;
- };
-
- pgc_otg2: power-domain@3 {
- #power-domain-cells = <0>;
- reg = <IMX8M_POWER_DOMAIN_USB_OTG2>;
- };
-
- pgc_ddr1: power-domain@4 {
- #power-domain-cells = <0>;
- reg = <IMX8M_POWER_DOMAIN_DDR1>;
- };
-
- pgc_gpu: power-domain@5 {
- #power-domain-cells = <0>;
- reg = <IMX8M_POWER_DOMAIN_GPU>;
- clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
- <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
- <&clk IMX8MQ_CLK_GPU_AXI>,
- <&clk IMX8MQ_CLK_GPU_AHB>;
- };
-
- pgc_vpu: power-domain@6 {
- #power-domain-cells = <0>;
- reg = <IMX8M_POWER_DOMAIN_VPU>;
- clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
- };
-
- pgc_disp: power-domain@7 {
- #power-domain-cells = <0>;
- reg = <IMX8M_POWER_DOMAIN_DISP>;
- };
-
- pgc_mipi_csi1: power-domain@8 {
- #power-domain-cells = <0>;
- reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>;
- };
-
- pgc_mipi_csi2: power-domain@9 {
- #power-domain-cells = <0>;
- reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>;
- };
-
- pgc_pcie2: power-domain@a {
- #power-domain-cells = <0>;
- reg = <IMX8M_POWER_DOMAIN_PCIE2>;
- };
- };
- };
- };
-
- bus@30400000 { /* AIPS2 */
- compatible = "fsl,aips-bus", "simple-bus";
- reg = <0x305f0000 0x10000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x30400000 0x30400000 0x400000>;
-
- pwm1: pwm@30660000 {
- compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
- reg = <0x30660000 0x10000>;
- interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,
- <&clk IMX8MQ_CLK_PWM1_ROOT>;
- clock-names = "ipg", "per";
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm2: pwm@30670000 {
- compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
- reg = <0x30670000 0x10000>;
- interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
- <&clk IMX8MQ_CLK_PWM2_ROOT>;
- clock-names = "ipg", "per";
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm3: pwm@30680000 {
- compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
- reg = <0x30680000 0x10000>;
- interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,
- <&clk IMX8MQ_CLK_PWM3_ROOT>;
- clock-names = "ipg", "per";
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- pwm4: pwm@30690000 {
- compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
- reg = <0x30690000 0x10000>;
- interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,
- <&clk IMX8MQ_CLK_PWM4_ROOT>;
- clock-names = "ipg", "per";
- #pwm-cells = <2>;
- status = "disabled";
- };
-
- system_counter: timer@306a0000 {
- compatible = "nxp,sysctr-timer";
- reg = <0x306a0000 0x20000>;
- interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&osc_25m>;
- clock-names = "per";
- };
- };
-
- bus@30800000 { /* AIPS3 */
- compatible = "fsl,aips-bus", "simple-bus";
- reg = <0x309f0000 0x10000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x30800000 0x30800000 0x400000>,
- <0x08000000 0x08000000 0x10000000>;
-
- ecspi1: spi@30820000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
- reg = <0x30820000 0x10000>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
- <&clk IMX8MQ_CLK_ECSPI1_ROOT>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- ecspi2: spi@30830000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
- reg = <0x30830000 0x10000>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,
- <&clk IMX8MQ_CLK_ECSPI2_ROOT>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- ecspi3: spi@30840000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
- reg = <0x30840000 0x10000>;
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,
- <&clk IMX8MQ_CLK_ECSPI3_ROOT>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- uart1: serial@30860000 {
- compatible = "fsl,imx8mq-uart",
- "fsl,imx6q-uart";
- reg = <0x30860000 0x10000>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
- <&clk IMX8MQ_CLK_UART1_ROOT>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- uart3: serial@30880000 {
- compatible = "fsl,imx8mq-uart",
- "fsl,imx6q-uart";
- reg = <0x30880000 0x10000>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
- <&clk IMX8MQ_CLK_UART3_ROOT>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- uart2: serial@30890000 {
- compatible = "fsl,imx8mq-uart",
- "fsl,imx6q-uart";
- reg = <0x30890000 0x10000>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
- <&clk IMX8MQ_CLK_UART2_ROOT>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- sai2: sai@308b0000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx8mq-sai";
- reg = <0x308b0000 0x10000>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,
- <&clk IMX8MQ_CLK_SAI2_ROOT>,
- <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
- clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- sai3: sai@308c0000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx8mq-sai";
- reg = <0x308c0000 0x10000>;
- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_SAI3_IPG>,
- <&clk IMX8MQ_CLK_SAI3_ROOT>,
- <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
- clock-names = "bus", "mclk1", "mclk2", "mclk3";
- dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
-
- crypto: crypto@30900000 {
- compatible = "fsl,sec-v4.0";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x30900000 0x40000>;
- ranges = <0 0x30900000 0x40000>;
- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_AHB>,
- <&clk IMX8MQ_CLK_IPG_ROOT>;
- clock-names = "aclk", "ipg";
-
- sec_jr0: jr@1000 {
- compatible = "fsl,sec-v4.0-job-ring";
- reg = <0x1000 0x1000>;
- interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- sec_jr1: jr@2000 {
- compatible = "fsl,sec-v4.0-job-ring";
- reg = <0x2000 0x1000>;
- interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- sec_jr2: jr@3000 {
- compatible = "fsl,sec-v4.0-job-ring";
- reg = <0x3000 0x1000>;
- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- mipi_dsi: mipi_dsi@30a00000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx8mq-nwl-dsi";
- reg = <0x30a00000 0x300>;
- clocks = <&clk IMX8MQ_CLK_DSI_CORE>, <&clk IMX8MQ_CLK_DSI_AHB>, <&clk IMX8MQ_CLK_DSI_IPG_DIV>, <&clk IMX8MQ_CLK_DSI_PHY_REF>, <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
- clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
- assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>,
- <&clk IMX8MQ_CLK_DSI_CORE>,
- <&clk IMX8MQ_CLK_DSI_IPG_DIV>;
- assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>,
- <&clk IMX8MQ_SYS1_PLL_266M>;
- assigned-clock-rates = <80000000>,
- <266000000>,
- <20000000>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&pgc_mipi>;
- resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,
- <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,
- <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,
- <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;
- reset-names = "byte", "dpi", "esc", "pclk";
- mux-controls = <&mux 0>;
- phys = <&dphy>;
- phy-names = "dphy";
- status = "disabled";
- };
-
- dphy: dphy@30a00300 {
- compatible = "fsl,imx8mq-mipi-dphy";
- reg = <0x30a00300 0x100>;
- clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
- clock-names = "phy_ref";
- assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
- assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
- assigned-clock-rates = <24000000>;
- #phy-cells = <0>;
- power-domains = <&pgc_mipi>;
- status = "disabled";
- };
-
- i2c1: i2c@30a20000 {
- compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
- reg = <0x30a20000 0x10000>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@30a30000 {
- compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
- reg = <0x30a30000 0x10000>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c3: i2c@30a40000 {
- compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
- reg = <0x30a40000 0x10000>;
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c4: i2c@30a50000 {
- compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
- reg = <0x30a50000 0x10000>;
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- uart4: serial@30a60000 {
- compatible = "fsl,imx8mq-uart",
- "fsl,imx6q-uart";
- reg = <0x30a60000 0x10000>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
- <&clk IMX8MQ_CLK_UART4_ROOT>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
-
- usdhc1: mmc@30b40000 {
- compatible = "fsl,imx8mq-usdhc",
- "fsl,imx7d-usdhc";
- reg = <0x30b40000 0x10000>;
- interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
- <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
- <&clk IMX8MQ_CLK_USDHC1_ROOT>;
- clock-names = "ipg", "ahb", "per";
- fsl,tuning-start-tap = <20>;
- fsl,tuning-step = <2>;
- bus-width = <4>;
- status = "disabled";
- };
-
- usdhc2: mmc@30b50000 {
- compatible = "fsl,imx8mq-usdhc",
- "fsl,imx7d-usdhc";
- reg = <0x30b50000 0x10000>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_IPG_ROOT>,
- <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
- <&clk IMX8MQ_CLK_USDHC2_ROOT>;
- clock-names = "ipg", "ahb", "per";
- fsl,tuning-start-tap = <20>;
- fsl,tuning-step = <2>;
- bus-width = <4>;
- status = "disabled";
- };
-
- qspi0: spi@30bb0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
- reg = <0x30bb0000 0x10000>,
- <0x08000000 0x10000000>;
- reg-names = "QuadSPI", "QuadSPI-memory";
- interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
- <&clk IMX8MQ_CLK_QSPI_ROOT>;
- clock-names = "qspi_en", "qspi";
- status = "disabled";
- };
-
- sdma1: sdma@30bd0000 {
- compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
- reg = <0x30bd0000 0x10000>;
- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
- <&clk IMX8MQ_CLK_AHB>;
- clock-names = "ipg", "ahb";
- #dma-cells = <3>;
- fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
- };
-
- fec1: ethernet@30be0000 {
- compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
- reg = <0x30be0000 0x10000>;
- interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
- <&clk IMX8MQ_CLK_ENET1_ROOT>,
- <&clk IMX8MQ_CLK_ENET_TIMER>,
- <&clk IMX8MQ_CLK_ENET_REF>,
- <&clk IMX8MQ_CLK_ENET_PHY_REF>;
- clock-names = "ipg", "ahb", "ptp",
- "enet_clk_ref", "enet_out";
- fsl,num-tx-queues = <3>;
- fsl,num-rx-queues = <3>;
- status = "disabled";
- };
- };
-
- bus@32c00000 { /* AIPS4 */
- compatible = "fsl,aips-bus", "simple-bus";
- reg = <0x32df0000 0x10000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x32c00000 0x32c00000 0x400000>;
-
- hdmi: hdmi@32c00000 {
- reg = <0x32c00000 0x100000>,
- <0x32e40000 0x40000>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "plug_in", "plug_out";
- };
-
- irqsteer: interrupt-controller@32e2d000 {
- compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
- reg = <0x32e2d000 0x1000>;
- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
- clock-names = "ipg";
- fsl,channel = <0>;
- fsl,num-irqs = <64>;
- interrupt-controller;
- #interrupt-cells = <1>;
- };
-
- dcss: display-controller@32e00000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "nxp,imx8mq-dcss";
- reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>;
- interrupts = <6>, <8>, <9>, <16>, <17>;
- interrupt-names = "ctxld", "ctxld_kick", "vblank", "dtrc_ch1", "dtrc_ch2";
- interrupt-parent = <&irqsteer>;
- clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
- <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
- <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
- <&clk IMX8MQ_VIDEO2_PLL_OUT>,
- <&clk IMX8MQ_CLK_DISP_DTRC>,
- <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>,
- <&clk IMX8MQ_CLK_PHY_27MHZ>;
- clock-names = "apb", "axi", "rtrm", "pix", "dtrc", "pll_src",
- "pll_phy_ref";
- assigned-clocks = <&clk 107>, <&clk 109>, <&clk 266>;
- assigned-clock-parents = <&clk 78>, <&clk 78>, <&clk 3>;
- assigned-clock-rates = <800000000>, <400000000>;
- };
- };
-
- gpu: gpu@38000000 {
- compatible = "vivante,gc";
- reg = <0x38000000 0x40000>;
- interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
- <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
- <&clk IMX8MQ_CLK_GPU_AXI>,
- <&clk IMX8MQ_CLK_GPU_AHB>;
- clock-names = "core", "shader", "bus", "reg";
- #cooling-cells = <2>;
- assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
- <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
- <&clk IMX8MQ_CLK_GPU_AXI>,
- <&clk IMX8MQ_CLK_GPU_AHB>,
- <&clk IMX8MQ_GPU_PLL_BYPASS>;
- assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
- <&clk IMX8MQ_GPU_PLL_OUT>,
- <&clk IMX8MQ_GPU_PLL_OUT>,
- <&clk IMX8MQ_GPU_PLL_OUT>,
- <&clk IMX8MQ_GPU_PLL>;
- assigned-clock-rates = <800000000>, <800000000>,
- <800000000>, <800000000>, <0>;
- power-domains = <&pgc_gpu>;
- };
-
- usb_dwc3_0: usb@38100000 {
- compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
- reg = <0x38100000 0x10000>;
- clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>,
- <&clk IMX8MQ_CLK_USB_CORE_REF>,
- <&clk IMX8MQ_CLK_32K>;
- clock-names = "bus_early", "ref", "suspend";
- assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
- <&clk IMX8MQ_CLK_USB_CORE_REF>;
- assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
- <&clk IMX8MQ_SYS1_PLL_100M>;
- assigned-clock-rates = <500000000>, <100000000>;
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&usb3_phy0>, <&usb3_phy0>;
- phy-names = "usb2-phy", "usb3-phy";
- power-domains = <&pgc_otg1>;
- usb3-resume-missing-cas;
- status = "disabled";
- };
-
- usb3_phy0: usb-phy@381f0040 {
- compatible = "fsl,imx8mq-usb-phy";
- reg = <0x381f0040 0x40>;
- clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
- clock-names = "phy";
- assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
- assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
- assigned-clock-rates = <100000000>;
- #phy-cells = <0>;
- status = "disabled";
- };
-
- usb_dwc3_1: usb@38200000 {
- compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
- reg = <0x38200000 0x10000>;
- clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>,
- <&clk IMX8MQ_CLK_USB_CORE_REF>,
- <&clk IMX8MQ_CLK_32K>;
- clock-names = "bus_early", "ref", "suspend";
- assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
- <&clk IMX8MQ_CLK_USB_CORE_REF>;
- assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
- <&clk IMX8MQ_SYS1_PLL_100M>;
- assigned-clock-rates = <500000000>, <100000000>;
- interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&usb3_phy1>, <&usb3_phy1>;
- phy-names = "usb2-phy", "usb3-phy";
- power-domains = <&pgc_otg2>;
- usb3-resume-missing-cas;
- status = "disabled";
- };
-
- usb3_phy1: usb-phy@382f0040 {
- compatible = "fsl,imx8mq-usb-phy";
- reg = <0x382f0040 0x40>;
- clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
- clock-names = "phy";
- assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
- assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
- assigned-clock-rates = <100000000>;
- #phy-cells = <0>;
- status = "disabled";
- };
-
- vpu: video-codec@38300000 {
- compatible = "nxp,imx8mq-vpu";
- reg = <0x38300000 0x10000>,
- <0x38310000 0x10000>,
- <0x38320000 0x10000>;
- reg-names = "g1", "g2", "ctrl";
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "g1", "g2";
- clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
- <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
- <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
- clock-names = "g1", "g2", "bus";
- assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
- <&clk IMX8MQ_CLK_VPU_G2>,
- <&clk IMX8MQ_CLK_VPU_BUS>,
- <&clk IMX8MQ_VPU_PLL_BYPASS>;
- assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
- <&clk IMX8MQ_VPU_PLL_OUT>,
- <&clk IMX8MQ_SYS1_PLL_800M>,
- <&clk IMX8MQ_VPU_PLL>;
- assigned-clock-rates = <600000000>, <600000000>,
- <800000000>, <0>;
- power-domains = <&pgc_vpu>;
- };
-
- pcie0: pcie@33800000 {
- compatible = "fsl,imx8mq-pcie";
- reg = <0x33800000 0x400000>,
- <0x1ff00000 0x80000>;
- reg-names = "dbi", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- bus-range = <0x00 0xff>;
- ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
- 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
- num-lanes = <1>;
- num-viewport = <4>;
- interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
- fsl,max-link-speed = <2>;
- power-domains = <&pgc_pcie>;
- resets = <&src IMX8MQ_RESET_PCIEPHY>,
- <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
- <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
- reset-names = "pciephy", "apps", "turnoff";
- status = "disabled";
- };
-
- pcie1: pcie@33c00000 {
- compatible = "fsl,imx8mq-pcie";
- reg = <0x33c00000 0x400000>,
- <0x27f00000 0x80000>;
- reg-names = "dbi", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */
- 0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
- num-lanes = <1>;
- num-viewport = <4>;
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "msi";
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- fsl,max-link-speed = <2>;
- power-domains = <&pgc_pcie>;
- resets = <&src IMX8MQ_RESET_PCIEPHY2>,
- <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
- <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
- reset-names = "pciephy", "apps", "turnoff";
- status = "disabled";
- };
-
- gic: interrupt-controller@38800000 {
- compatible = "arm,gic-v3";
- reg = <0x38800000 0x10000>, /* GIC Dist */
- <0x38880000 0xc0000>, /* GICR */
- <0x31000000 0x2000>, /* GICC */
- <0x31010000 0x2000>, /* GICV */
- <0x31020000 0x2000>; /* GICH */
- #interrupt-cells = <3>;
- interrupt-controller;
- interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- };
-
- ddrc: memory-controller@3d400000 {
- compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc";
- reg = <0x3d400000 0x400000>;
- clock-names = "core", "pll", "alt", "apb";
- clocks = <&clk IMX8MQ_CLK_DRAM_CORE>,
- <&clk IMX8MQ_DRAM_PLL_OUT>,
- <&clk IMX8MQ_CLK_DRAM_ALT>,
- <&clk IMX8MQ_CLK_DRAM_APB>;
- };
-
- ddr-pmu@3d800000 {
- compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
- reg = <0x3d800000 0x400000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-};