Commits · main · Reform / MNT Reform Kintex-7 SoM

12 Jul, 2021 4 commits
- add d-1 gerbers · 225e70ef
  mntmn authored Jul 12, 2021
  
  225e70ef
- final tweaks for first fabbing · dc6115c2
  mntmn authored Jul 12, 2021
  
  dc6115c2
- snapshot before tusb length matching · 98fe0111
  mntmn authored Jul 12, 2021
  
  98fe0111
- reroute all diff pairs · b40e3691
  mntmn authored Jul 12, 2021
  
  b40e3691
11 Jul, 2021 4 commits
- TUSB: fix VDDA1P8 · 3187adc2
  mntmn authored Jul 11, 2021
  
  3187adc2
- DDR length matching double checked/fixed · 97ee0916
  mntmn authored Jul 11, 2021
  
  97ee0916
- reroute some DDR signals, tweak more track widths · 9c734579
  mntmn authored Jul 11, 2021
  
  9c734579
- WIP adjust ddr trace widths; prepare some TODOs for errors found with vivado · 6fe20f48
  mntmn authored Jul 11, 2021
  
  6fe20f48
10 Jul, 2021 2 commits
- add validated MIG UCF; requires a few DQ signal changes · b16b0ee0
  mntmn authored Jul 10, 2021
  
  b16b0ee0
- pcb: fix some ram trace lengths · 408c04b7
  mntmn authored Jul 10, 2021
  
  408c04b7
09 Jul, 2021 8 commits
- readme: typo · 4bf33c14
  mntmn authored Jul 09, 2021
  
  4bf33c14
- readme: add links · bb7c5b6a
  mntmn authored Jul 09, 2021
  
  bb7c5b6a
- readme: fix images · a1118eb4
  mntmn authored Jul 09, 2021
  
  a1118eb4
- add readme, schematics pdf, image · ffe5223b
  mntmn authored Jul 09, 2021
  
  ffe5223b
- DRC, polishing, bugfixes, badge · 28a9c049
  mntmn authored Jul 09, 2021
  
  28a9c049
- reconnect remaining pads · 153cf7e0
  mntmn authored Jul 09, 2021
  
  153cf7e0
- card edge: remove paste from pads · 717f50e6
  mntmn authored Jul 09, 2021
  
  717f50e6
- ddr3 length matching · 9dc54ae4
  mntmn authored Jul 09, 2021
  
  9dc54ae4
08 Jul, 2021 1 commit
- WIP ddr data and address groups length matching · a353d730
  mntmn authored Jul 08, 2021
  
  a353d730
07 Jul, 2021 5 commits
- actual 3d models and footprints · 5ecb4777
  mntmn authored Jul 07, 2021
  
  5ecb4777
- silkscreen cleanup, 3d models, some footprint fixes · d62396b3
  mntmn authored Jul 07, 2021
  
  d62396b3
- connect some missing i2c signals, backlight_en · fd1041a9
  mntmn authored Jul 07, 2021
  
  fd1041a9
- fully routed · 5bdda322
  mntmn authored Jul 07, 2021
  
  5bdda322
- more routing (39) · af0361ae
  mntmn authored Jul 07, 2021
  
  af0361ae
06 Jul, 2021 1 commit
- add power sequencer, main clock, some missing resets, more routing (198) · d35b7a5d
  mntmn authored Jul 06, 2021
  
  d35b7a5d
05 Jul, 2021 1 commit
- more routing: 215 to go · 8e9f2ac1
  mntmn authored Jul 05, 2021
  
  8e9f2ac1
29 Jun, 2021 1 commit
- more routing · ea4dc072
  mntmn authored Jun 29, 2021
  
  ea4dc072
20 Jun, 2021 1 commit
- more routing · 32afdefa
  mntmn authored Jun 20, 2021
  
  32afdefa
17 Jun, 2021 1 commit
- place all components · 4762f7ff
  mntmn authored Jun 17, 2021
  
  4762f7ff
16 Jun, 2021 1 commit
- place lots of caps; place some power supplies · 2eba2ec6
  mntmn authored Jun 16, 2021
  
  2eba2ec6
09 Jun, 2021 1 commit
- ram bypass caps placed · 5aacb41d
  mntmn authored Jun 09, 2021
  
  5aacb41d
06 Jun, 2021 1 commit
- schematics: add many decoupling caps · 7965c124
  mntmn authored Jun 06, 2021
  
  7965c124
04 Jun, 2021 1 commit
- more routing, bunch of fpga bypass caps, logo · 48c00928
  mntmn authored Jun 04, 2021
  
  48c00928
03 Jun, 2021 1 commit
- more routing, esp. ethernet · 6ecfde05
  mntmn authored Jun 03, 2021
  
  6ecfde05
28 May, 2021 2 commits
- DSI and some USB routing · 95ba00e3
  mntmn authored May 28, 2021
  
  95ba00e3
- ram bus termination · acc48ae5
  mntmn authored May 28, 2021
  
  acc48ae5
27 May, 2021 1 commit
- more DDR3 routing · f6e1b262
  mntmn authored May 27, 2021
  
  f6e1b262
09 May, 2021 1 commit
- finish first draft of TUSB connectivity · 4ba6cdc6
  mntmn authored May 09, 2021
  
  4ba6cdc6
24 Apr, 2021 2 commits
- more TUSB noodling · cc28ede5
  mntmn authored Apr 25, 2021
  
  cc28ede5
- some more TUSB signals connected · 2eb1203a
  mntmn authored Apr 24, 2021
  
  2eb1203a