diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index e4584ff8f96f401bef5ea1d673efefc98b1d5bf1..fab9125bcb7a7a69e52b4ca8c77251adabf1a5ca 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -14,18 +14,17 @@ build: fi export CROSS_COMPILE=aarch64-linux-gnu- export ARCH=arm64 - cp imx8mp-mnt-reform2.dts u-boot/arch/arm/dts/ - cp imx8mp-mnt-pocket-reform.dts u-boot/arch/arm/dts/ - patch -d u-boot -p1 < 0000-add-dts.patch - cp imx8mp-mnt-reform2_defconfig u-boot/configs/ - cp imx8mp-mnt-pocket-reform_defconfig u-boot/configs/ # LPDDR4 Blobs cp lpddr4*.bin u-boot/ # MNT Reform 2 + cp imx8mp-mnt-reform2.dts u-boot/arch/arm/dts/imx8mp-nitrogen8mp.dts + cp imx8mp-mnt-reform2_defconfig u-boot/configs/ make -C u-boot imx8mp-mnt-reform2_defconfig make -C u-boot -j$(nproc) flash.bin mv u-boot/flash.bin imx8mp-mnt-reform2-flash.bin # MNT Pocket Reform + cp imx8mp-mnt-pocket-reform.dts u-boot/arch/arm/dts/imx8mp-nitrogen8mp.dts + cp imx8mp-mnt-pocket-reform_defconfig u-boot/configs/ make -C u-boot imx8mp-mnt-pocket-reform_defconfig make -C u-boot -j$(nproc) flash.bin mv u-boot/flash.bin imx8mp-mnt-pocket-reform-flash.bin diff --git a/imx8mp-mnt-pocket-reform.dts b/imx8mp-mnt-pocket-reform.dts index 0d29c24edb57b00a5a95abb71abcbbaac0314e82..456f510c50c6f9abcd2b68cbeb9c24f0d98f3bc8 100644 --- a/imx8mp-mnt-pocket-reform.dts +++ b/imx8mp-mnt-pocket-reform.dts @@ -1,44 +1,34 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) - /* - * Copyright 2019-2022 MNT Research GmbH - * Copyright 2021 Lucas Stach <dev@lynxeye.de> * Copyright 2020 Boundary Devices -*/ - -// https://github.com/boundarydevices/linux/blob/boundary-imx_5.15.y/arch/arm64/boot/dts/freescale/imx8mp-nitrogen8mp.dts + */ /dts-v1/; +#ifdef CONFIG_DEFCONFIG +#define UBOOT +#endif +#define IMX8MP #include <dt-bindings/phy/phy-imx8-pcie.h> -#include "imx8mp.dtsi" +#include <dt-bindings/usb/pd.h> +#include "imx8mp-nitrogen8mp-som.dtsi" &iomuxc { - pinctrl_eqos: eqosgrp { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_ecspi2: ecspi2grp { fsl,pins = < - MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x20 - MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0xa0 - MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f - MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f - MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f - MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f - MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f - - MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 - MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 - MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 - MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 - MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 - MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 -#define GP_EQOS_RESET <&gpio3 16 GPIO_ACTIVE_LOW> - MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x100 -#define GPIRQ_EQOS_PHY <&gpio3 2 IRQ_TYPE_LEVEL_LOW> - MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02 0x10 + /* J31 */ + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 /* Pin 20 */ + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 /* Pin 10 */ + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 /* Pin 8 */ +#define GP_ECSPI2_CS <&gpio5 13 GPIO_ACTIVE_LOW> + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x143 /* Pin 6 */ >; }; - /*pinctrl_fec: fecgrp { + pinctrl_fec: fecgrp { fsl,pins = < MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x0 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0xa0 @@ -58,150 +48,141 @@ #define GP_FEC_RESET <&gpio5 8 GPIO_ACTIVE_LOW> MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x100 #define GPIRQ_FEC_PHY <&gpio1 7 IRQ_TYPE_LEVEL_LOW> - MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x10 - >; - };*/ - - pinctrl_hog: hoggrp { - fsl,pins = < - //MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x119 /* J31 */ - MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x41 /* Pin 17 */ - MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x41 /* Pin 19 */ - MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x41 /* Pin 21 */ - MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x41 /* Pin 23 */ - MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x41 /* Pin 25 */ - MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41 /* Pin 29 */ - //MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41 /* Pin 31 */ - MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x16 /* Pin 2 */ - MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c4 /* Pin 4 */ + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x1c0 >; }; - pinctrl_panel: panelgrp { + pinctrl_flexcan1: flexcan1grp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140 - MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x140 - MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41 /* Pin 31 */ + MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154 >; }; - pinctrl_bt_rfkill: bt-rfkillgrp { + pinctrl_flexcan1_reg: flexcan1reggrp { fsl,pins = < -#define GP_BT_RFKILL_RESET <&gpio3 9 GPIO_ACTIVE_LOW> - MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x119 +#define GP_CAN1_STANDBY <&gpio3 20 GPIO_ACTIVE_HIGH> + MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x154 /* CAN1_STBY */ >; }; - pinctrl_ecspi2: ecspi2grp { + pinctrl_flexcan2: flexcan2grp { fsl,pins = < - /* J31 */ - MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 /* Pin 20 */ - MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 /* Pin 10 */ - MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 /* Pin 8 */ -#define GP_ECSPI2_CS <&gpio5 13 GPIO_ACTIVE_LOW> - MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x143 /* Pin 6 */ + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 >; }; - pinctrl_i2c1: i2c1grp { + pinctrl_flexcan2_reg: flexcan2reggrp { fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 - MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 +#define GP_CAN2_STANDBY <&gpio2 9 GPIO_ACTIVE_HIGH> + MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x154 /* CAN2_STBY */ >; }; - pinctrl_i2c1_1: i2c1-1grp { + pinctrl_key_can1: key-can1grp { fsl,pins = < -#define GP_I2C1_SCL <&gpio5 14 GPIO_OPEN_DRAIN> - MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3 -#define GP_I2C1_SDA <&gpio5 15 GPIO_OPEN_DRAIN> - MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3 +#define GP_CAN1_DETECT <&gpio1 11 GPIO_ACTIVE_HIGH> + MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x16 >; }; - pinctrl_i2c2: i2c2grp { + pinctrl_key_can2: key-can2grp { fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 - MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 +#define GP_CAN2_DETECT <&gpio4 23 GPIO_ACTIVE_HIGH> + MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x180 >; }; - pinctrl_i2c2_1: i2c2-1grp { + pinctrl_hog: hoggrp { fsl,pins = < -#define GP_I2C2_SCL <&gpio5 16 GPIO_OPEN_DRAIN> - MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c3 -#define GP_I2C2_SDA <&gpio5 17 GPIO_OPEN_DRAIN> - MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c3 + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019 + MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x119 + /* J31 */ + MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x41 /* Pin 17 */ + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x41 /* Pin 19 */ + MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x41 /* Pin 21 */ + MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x41 /* Pin 23 */ + MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x41 /* Pin 25 */ + MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41 /* Pin 29 */ + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41 /* Pin 31 */ + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x16 /* Pin 2 */ + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c4 /* Pin 4 */ >; }; - pinctrl_i2c3: i2c3grp { + pinctrl_i2c2_pca9546: i2c2-pca9546grp { fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 - MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 +#define GP_PCA9546_RESET <&gpio1 5 GPIO_ACTIVE_LOW> + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x100 >; }; - pinctrl_i2c3_1: i2c3-1grp { + pinctrl_i2c2d_rv3028: i2c2d-rv3028grp { fsl,pins = < -#define GP_I2C3_SCL <&gpio5 18 GPIO_OPEN_DRAIN> - MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c3 -#define GP_I2C3_SDA <&gpio5 19 GPIO_OPEN_DRAIN> - MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c3 +#define GPIRQ_RV3028 <&gpio1 4 IRQ_TYPE_LEVEL_LOW> + MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x1c0 >; }; - pinctrl_i2c4: i2c4grp { + pinctrl_i2c4_hd3ss3220: i2c4-hd3ss3220grp { fsl,pins = < - MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 - MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 +#define GPIRQ_HD3SS3220 <&gpio1 8 IRQ_TYPE_LEVEL_LOW> + MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x16 + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x03 >; }; - pinctrl_i2c4_1: i2c4-1grp { + pinctrl_pdm: pdmgrp { fsl,pins = < -#define GP_I2C4_SCL <&gpio5 20 GPIO_OPEN_DRAIN> - MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x1c3 -#define GP_I2C4_SDA <&gpio5 21 GPIO_OPEN_DRAIN> - MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c3 + MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_PDM_CLK 0xd6 + MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_PDM_BIT_STREAM00 0xd6 >; }; - pinctrl_reg_wlan_vmmc: reg-wlan-vmmcgrp { + pinctrl_pcie: pciegrp { fsl,pins = < -#define GP_REG_WLAN_VMMC <&gpio2 19 GPIO_ACTIVE_HIGH> - MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x16 +#define GP_PCIE_RESET <&gpio4 29 GPIO_ACTIVE_LOW> + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x41 +#define GP_PCIE_DISABLE <&gpio4 26 GPIO_ACTIVE_LOW> + MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x41 >; }; - pinctrl_pcie: pciegrp { + pinctrl_pwm4: pwm4grp { fsl,pins = < -#define GP_PCIE_RESET <&gpio1 11 GPIO_ACTIVE_LOW> - MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x41 -/*#define GP_PCIE_DISABLE <&gpio4 26 GPIO_ACTIVE_LOW> - MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x41*/ + /* J31, pin 36 */ + MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 >; }; - pinctrl_pmic: pmicirq { + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { fsl,pins = < -#define GPIRQ_PMIC <&gpio3 0 IRQ_TYPE_LEVEL_LOW> - MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x41 +#define GP_REG_USB_OTG_VBUS <&gpio1 12 GPIO_ACTIVE_HIGH> + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x100 >; }; - pinctrl_edp_bridge: edpbridgegrp { + pinctrl_sai3: sai3grp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x100 + /* WM8960 */ + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 >; }; - pinctrl_uart1: uart1grp { + pinctrl_sound_wm8960: sound-wm8960grp { fsl,pins = < - MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 - MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 - MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 - MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 +#define GP_WM8960_MIC_DET <&gpio4 18 GPIO_ACTIVE_HIGH> + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x1c0 +#define GP_WM8960_HP_DET <&gpio1 14 GPIO_ACTIVE_HIGH> + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x80 >; }; @@ -226,6 +207,19 @@ >; }; + pinctrl_usb3_0: usb3-0grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO13__USB1_OC 0x1c0 + >; + }; + + pinctrl_usb3_1: usb3-1grp { + fsl,pins = < +#define GP_USB3_1_HUB_RESET <&gpio1 10 GPIO_ACTIVE_LOW> + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO10 0x100 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 @@ -234,7 +228,7 @@ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 - //MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT 0x116 + MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT 0x116 >; }; @@ -266,116 +260,37 @@ MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x1c4 >; }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 -#define GP_EMMC_RESET <&gpio3 1 IRQ_TYPE_LEVEL_LOW> - MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x140 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 - >; - }; }; / { model = "MNT Pocket Reform with i.MX8MP Module"; - compatible = "mntre,pocket-reform", "boundary,imx8mp-nitrogen8mp-som", "fsl,imx8mp"; - chassis-type = "laptop"; + compatible = "boundary,imx8mp-nitrogen8mp", "fsl,imx8mp"; - chosen { - stdout-path = &uart2; + aliases { + fb_hdmi = &lcdif3; + sound_hdmi = &sound_hdmi; }; - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; + chosen { + stdout-path = &uart2; }; - bt-rfkill { - compatible = "net,rfkill-gpio"; + gpio_keys: gpio-keys { + compatible = "gpio-keys"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bt_rfkill>; - name = "bt-rfkill"; - type = <2>; /* Bluetooth */ - reset-gpios = GP_BT_RFKILL_RESET; - status = "okay"; + pinctrl-0 = <&pinctrl_key_can1>, <&pinctrl_key_can2>; + + can1 { + label = "can1 detect"; + gpios = GP_CAN1_DETECT; + linux,code = <KEY_1>; + }; + + can2 { + label = "can2 detect"; + gpios = GP_CAN2_DETECT; + linux,code = <KEY_2>; + }; }; pcie0_refclk: pcie0-refclk { @@ -384,465 +299,273 @@ clock-frequency = <100000000>; }; - reg_main_5v: regulator-main-5v { + reg_can1_stby: regulator-can1-stby { compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_main_3v3: regulator-main-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3V3"; + regulator-name = "can1-stby"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_reg>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + gpio = GP_CAN1_STANDBY; + enable-active-high; }; - reg_main_usb: regulator-main-usb { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_main_5v>; - }; - - reg_main_1v8: regulator-main-1v8 { - compatible = "regulator-fixed"; - regulator-name = "1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <®_main_3v3>; - }; - - reg_main_1v2: regulator-main-1v2 { - compatible = "regulator-fixed"; - regulator-name = "1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - vin-supply = <®_main_5v>; - }; - - reg_wlan_vmmc: regulator-wlan-vmmc { + reg_can2_stby: regulator-can2-stby { compatible = "regulator-fixed"; + regulator-name = "can2-stby"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_wlan_vmmc>; - regulator-name = "reg_wlan_vmmc"; + pinctrl-0 = <&pinctrl_flexcan2_reg>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = GP_REG_WLAN_VMMC; - startup-delay-us = <70000>; + gpio = GP_CAN2_STANDBY; enable-active-high; }; - reg_pcie0: regulator-pcie { + reg_usb_otg_vbus: regulator-usb-otg-vbus { compatible = "regulator-fixed"; - regulator-name = "MPCIE_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <®_main_5v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_USB_OTG_VBUS; + enable-active-high; }; -}; - -&snvs_rtc { - status = "disabled"; -}; -&uart1 { /* BT */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clk IMX8MP_CLK_UART1>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; - uart-has-rtscts; - status = "okay"; + sound_hdmi: sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + model = "audio-hdmi"; +#ifndef UBOOT + audio-cpu = <&aud2htx>; +#endif + hdmi-out; + constraint-rate = <44100>, + <88200>, + <176400>, + <32000>, + <48000>, + <96000>, + <192000>; + status = "okay"; + }; }; -&uart2 { +&fec { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; + pinctrl-0 = <&pinctrl_fec>; +#if 0 + phy-reset-gpios = GP_FEC_RESET; +#endif + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; status = "okay"; -}; -&usb3_0 { - fsl,disable-port-power-control; - //fsl,permanently-attached; - fsl,over-current-active-low; - status = "okay"; -}; + mdio { + #address-cells = <1>; + #size-cells = <0>; -&usb3_1 { - fsl,disable-port-power-control; - //fsl,permanently-attached; - fsl,over-current-active-low; - status = "disabled"; + ethphy1: ethernet-phy { + compatible = "ethernet-phy-ieee802.3-c22"; + eee-broken-1000t; + interrupts-extended = GPIRQ_FEC_PHY; + reg-mask = <0x90>; + }; + }; }; -&usb3_phy0 { +&hdmi { status = "okay"; }; -&usb3_phy1 { - status = "disabled"; +&hdmiphy { + status = "okay"; }; -&usb_dwc3_0 { - dr_mode = "host"; +&hdmi_pavi { status = "okay"; }; -&usb_dwc3_1 { - dr_mode = "host"; - status = "disabled"; +&i2c3 { + rtc@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + }; }; -&pwm1 { - //pinctrl-names = "default"; - //pinctrl-0 = <&pinctrl_pwm1>; +#ifndef UBOOT +&pcie { + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; + assigned-clock-rates = <10000000>; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_PCIE_ROOT>, + <&clk IMX8MP_CLK_HSIO_AXI>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + disable-gpio = GP_PCIE_DISABLE; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = GP_PCIE_RESET; status = "okay"; }; -&pwm2 { - //pinctrl-names = "default"; - //pinctrl-0 = <&pinctrl_pwm2>; +&pcie_phy { + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; + clocks = <&pcie0_refclk>; + clock-names = "ref"; status = "okay"; }; +#endif -&wdog1 { +&pwm4 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - timeout-sec = <7200>; + pinctrl-0 = <&pinctrl_pwm4>; status = "okay"; }; -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_1>; - scl-gpios = GP_I2C1_SCL; - sda-gpios = GP_I2C1_SDA; +&uart2 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; status = "okay"; - - pmic: pca9450@25 { - reg = <0x25>; - compatible = "nxp,pca9450c"; - /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - regulators { - buck1: BUCK1 { - regulator-name = "BUCK1"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - buck2: BUCK2 { - regulator-name = "BUCK2"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-limit-microvolt = <1025000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; - }; - - buck4: BUCK4 { - regulator-name = "BUCK4"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5: BUCK5 { - regulator-name = "BUCK5"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6: BUCK6 { - regulator-name = "BUCK6"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2: LDO2 { - regulator-name = "LDO2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3: LDO3 { - regulator-name = "LDO3"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4: LDO4 { - regulator-name = "LDO4"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5: LDO5 { - regulator-name = "LDO5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&A53_0 { - cpu-supply = <&buck2>; -}; - -&A53_1 { - cpu-supply = <&buck2>; -}; - -&A53_2 { - cpu-supply = <&buck2>; -}; - -&A53_3 { - cpu-supply = <&buck2>; }; -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_1>; - scl-gpios = GP_I2C2_SCL; - sda-gpios = GP_I2C2_SDA; +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; status = "okay"; }; -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_1>; - scl-gpios = GP_I2C3_SCL; - sda-gpios = GP_I2C3_SDA; +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MP_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; status = "okay"; - - rtc@68 { - compatible = "nxp,pcf8523"; - reg = <0x68>; - }; -}; - -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c4>; - pinctrl-1 = <&pinctrl_i2c4_1>; - scl-gpios = GP_I2C4_SCL; - sda-gpios = GP_I2C4_SDA; - status = "disabled"; }; -&mipi_dsi { - #address-cells = <1>; - #size-cells = <0>; - samsung,burst-clock-frequency = <972000000>; - samsung,esc-clock-frequency = <48000000>; +&usb3_0 { + fsl,disable-port-power-control; + fsl,over-current-active-low; status = "okay"; - - panel@0 { - compatible = "jdi,lt070me05000"; - reg = <0>; - - pinctrl = <&pinctrl_panel>; - - // reset is driven by rp2040 - // dcdc en is also driven by rp2040 - // actually backlight enable - enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - - burst-mode; - - port { - panel_in: endpoint { - remote-endpoint = <&mipi_dsi_out>; - }; - }; - }; - - ports { - port@1 { - reg = <1>; - mipi_dsi_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; }; -&lcdif1 { +&usb3_1 { + fsl,disable-port-power-control; status = "okay"; }; -&lcdif3 { +&usb_dwc3_0 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3_0>; status = "okay"; }; -&eqos { +&usb_dwc3_1 { + dr_mode = "host"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; + pinctrl-0 = <&pinctrl_usb3_1>; + reset-gpios = GP_USB3_1_HUB_RESET; status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@4 { - reg = <4>; - compatible = "ethernet-phy-ieee802.3-c22"; - at803x,hib-disabled; - eee-broken-1000t; - interrupts-extended = GPIRQ_EQOS_PHY; -#if 0 - reset-gpios = GP_EQOS_RESET; -#endif - reg-mask = <0x90>; - }; - }; }; -// apparently FEC can be run via SAI1 pins?? -/*&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy1>; - fsl,magic-packet; +&usb3_phy0 { + fsl,phy-tx-preemp-amp-tune = <2>; status = "okay"; + vbus-supply = <®_vref_5v0>; +}; - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy { - compatible = "ethernet-phy-ieee802.3-c22"; - eee-broken-1000t; - interrupts-extended = GPIRQ_FEC_PHY; - reg-mask = <0x90>; - }; - }; -};*/ +&usb3_phy1 { + fsl,phy-tx-preemp-amp-tune = <2>; + status = "okay"; + vbus-supply = <®_vref_5v0>; +}; -// sdcard? &usdhc1 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC1_ROOT>; - assigned-clock-rates = <400000000>; - //max-frequency = <12000000>; bus-width = <4>; cd-gpios = GP_USDHC1_CD; - pinctrl-names = "default"; //, "state_100mhz", "state_200mhz"; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; + /*pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;*/ status = "okay"; - vmmc-supply = <®_main_3v3>; - vqmmc-supply = <®_main_3v3>; + vmmc-supply = <®_vref_3v3>; + vqmmc-supply = <®_vref_3v3>; }; -// sdio (wifi/bt qca9733) -&usdhc2 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC2_ROOT>; - assigned-clock-rates = <200000000>; - bus-width = <4>; - //max-clock = <12000000>; - //fsl,sdio-async-interrupt-enabled; // needs patch https://www.spinics.net/lists/linux-mmc/msg65247.html - keep-power-in-suspend; - no-sd-uhs-sdr104; - sd-uhs-ddr50; - no-mmc; - no-sd; - //no-cqe; - non-removable; - cap-sdio-irq; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - pm-ignore-notify; - status = "okay"; - vmmc-supply = <®_wlan_vmmc>; - vqmmc-1-8-v; - vqmmc-supply = <®_main_1v8>; -}; +/* J11 mipi display */ +#define MIPI_DSI mipi_dsi +#define MIPI_DISPLAY lcdif1 +#define MIPI_SUBSYSTEM display_subsystem +#define MIPI_I2C_BUS i2c2d +#define SKIP_LONTIUM_DAUGHTER_BOARDS /* MIPI_I2C_BUS is already behind i2cmux */ +#define MIPI_PHY_CLOCK <&mipi_dsi 0> +#define MIPI_PIXEL_CLOCK <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT> -// emmc -&usdhc3 { - bus-width = <4>; // FIXME was 8 - no-mmc-hs400; - non-removable; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - vmmc-supply = <®_main_3v3>; - vqmmc-1-8-v; - vqmmc-supply = <®_main_1v8>; - status = "okay"; -}; +#define MIPI_PWM pwm1 +#define GP_MIPI_PWM(a) <&gpio1 1 a> +#define PD_MIPI_PWM(a) MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 a /* Pin 7 */ +#define PD_MIPI_PWM_OUT(a) MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT a -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; - clocks = <&hsio_blk_ctrl>; - phy-supply = <®_pcie0>; - clock-names = "ref"; - status = "okay"; - fsl,clkreq-unsupported; -}; +#define GP_MIPI_IRQ(a) <&gpio4 0 a> +#define PD_MIPI_IRQ(a) MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 a /* Pin 8 */ -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = GP_PCIE_RESET; - //disable-gpio = GP_PCIE_DISABLE; - clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, - <&clk IMX8MP_CLK_PCIE_ROOT>, - <&clk IMX8MP_CLK_HSIO_AXI>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; - assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; - assigned-clock-rates = <10000000>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; - vpcie-supply = <®_pcie0>; - vph-supply = <®_pcie0>; - status = "okay"; +#define GP_MIPI_TS_IRQ(a) <&gpio4 25 a> +#define PD_MIPI_TS_IRQ(a) MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 a /* Pin 9 */ + +#define GP_MIPI_TS_RESET(a) <&gpio4 24 a> +#define PD_MIPI_TS_RESET(a) MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 a /* Pin 10 */ + +#define GP_MIPI_ENABLE(a) <&gpio4 27 a> +#define PD_MIPI_ENABLE(a) MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 a /* Pin 11 */ + +/* +#ifdef UBOOT +#include "bd-universal-mipi-dsi.dtsi" +#else +#include "../bd-universal-mipi-dsi.dtsi" +#endif + +#define LVDS_DISPLAY lcdif2 +#define LVDS_I2C_BUS i2c4 +#define LVDS_PWM pwm2 +#define LVDS2_PWM pwm2 +// J28 pin 20 LVDS display, J27 pin 20 LVDS2 display +#define PD_LVDS_PWM(a) MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT a MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT a + +#define GP_LVDS_BACKLIGHT(a) <&gpio4 22 a> +#define PD_LVDS_BACKLIGHT(a) MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 a + +#define GP_LVDS2_BACKLIGHT(a) <&gpio4 21 a> +#define PD_LVDS2_BACKLIGHT(a) MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 a + +#define GP_LVDS_TS_IRQ(a) <&gpio1 10 a> +#define PD_LVDS_TS_IRQ(a) MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 a + +// No pad associated with gpio3 30 +#define GP_LVDS_TS_RESET(a) <&gpio3 30 a> +#define PD_LVDS_TS_RESET(a) +#define LVDS_NO_TS_RESET +#ifdef UBOOT +#include "bd-universal-lvds.dtsi" +#else +#include "../bd-universal-lvds.dtsi" +#endif + +/ { + aliases { + // Old style aliases (without lvds) for older u-boots + // Delete upon next branch + ts_atmel_mt = &ts_lvds_atmel_mt; + ts_egalax = &ts_lvds_egalax; + ts_ft5x06_2 = &ts_lvds_ft5x06; + ts_goodix2 = &ts_lvds_goodix; + ts_goodix3 = &ts_lvds_goodix2; + ts_ili251x = &ts_lvds_ili251x; + }; }; +*/ diff --git a/imx8mp-mnt-reform2.dts b/imx8mp-mnt-reform2.dts index 33469162bf0a18129ee49be0b5c2c11d516d91b9..dc86db26b99157a62bb1cacfd3372001686e0787 100644 --- a/imx8mp-mnt-reform2.dts +++ b/imx8mp-mnt-reform2.dts @@ -1,44 +1,34 @@ // SPDX-License-Identifier: (GPL-2.0+ OR MIT) - /* - * Copyright 2019-2023 MNT Research GmbH - * Copyright 2021 Lucas Stach <dev@lynxeye.de> * Copyright 2020 Boundary Devices -*/ - -// see also: https://github.com/boundarydevices/linux/blob/boundary-imx_5.15.y/arch/arm64/boot/dts/freescale/imx8mp-nitrogen8mp.dts + */ /dts-v1/; +#ifdef CONFIG_DEFCONFIG +#define UBOOT +#endif +#define IMX8MP #include <dt-bindings/phy/phy-imx8-pcie.h> -#include "imx8mp.dtsi" +#include <dt-bindings/usb/pd.h> +#include "imx8mp-nitrogen8mp-som.dtsi" &iomuxc { - pinctrl_eqos: eqosgrp { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_ecspi2: ecspi2grp { fsl,pins = < - MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x20 - MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0xa0 - MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f - MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f - MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f - MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f - MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f - MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f - - MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 - MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 - MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 - MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 - MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 - MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 -#define GP_EQOS_RESET <&gpio3 16 GPIO_ACTIVE_LOW> - MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x100 -#define GPIRQ_EQOS_PHY <&gpio3 2 IRQ_TYPE_LEVEL_LOW> - MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02 0x10 + /* J31 */ + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 /* Pin 20 */ + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 /* Pin 10 */ + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 /* Pin 8 */ +#define GP_ECSPI2_CS <&gpio5 13 GPIO_ACTIVE_LOW> + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x143 /* Pin 6 */ >; }; - /*pinctrl_fec: fecgrp { + pinctrl_fec: fecgrp { fsl,pins = < MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x0 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0xa0 @@ -58,151 +48,141 @@ #define GP_FEC_RESET <&gpio5 8 GPIO_ACTIVE_LOW> MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x100 #define GPIRQ_FEC_PHY <&gpio1 7 IRQ_TYPE_LEVEL_LOW> - MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x10 - >; - };*/ - - pinctrl_hog: hoggrp { - fsl,pins = < - //MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x119 /* J31 */ - MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x41 /* Pin 17 */ - MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x41 /* Pin 19 */ - MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x41 /* Pin 21 */ - MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x41 /* Pin 23 */ - MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x41 /* Pin 25 */ - MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41 /* Pin 29 */ - MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41 /* Pin 31 */ - MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x16 /* Pin 2 */ - MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c4 /* Pin 4 */ + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x1c0 >; }; - pinctrl_bt_rfkill: bt-rfkillgrp { + pinctrl_flexcan1: flexcan1grp { fsl,pins = < -#define GP_BT_RFKILL_RESET <&gpio3 9 GPIO_ACTIVE_LOW> - MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x119 + MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154 >; }; - pinctrl_ecspi2: ecspi2grp { + pinctrl_flexcan1_reg: flexcan1reggrp { fsl,pins = < - /* J31 */ - MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 /* Pin 20 */ - MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 /* Pin 10 */ - MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 /* Pin 8 */ -#define GP_ECSPI2_CS <&gpio5 13 GPIO_ACTIVE_LOW> - MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x143 /* Pin 6 */ +#define GP_CAN1_STANDBY <&gpio3 20 GPIO_ACTIVE_HIGH> + MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x154 /* CAN1_STBY */ >; }; - pinctrl_i2c1: i2c1grp { + pinctrl_flexcan2: flexcan2grp { fsl,pins = < - MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 - MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 >; }; - pinctrl_i2c1_1: i2c1-1grp { + pinctrl_flexcan2_reg: flexcan2reggrp { fsl,pins = < -#define GP_I2C1_SCL <&gpio5 14 GPIO_OPEN_DRAIN> - MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3 -#define GP_I2C1_SDA <&gpio5 15 GPIO_OPEN_DRAIN> - MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3 +#define GP_CAN2_STANDBY <&gpio2 9 GPIO_ACTIVE_HIGH> + MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x154 /* CAN2_STBY */ >; }; - pinctrl_i2c2: i2c2grp { + pinctrl_key_can1: key-can1grp { fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 - MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 +#define GP_CAN1_DETECT <&gpio1 11 GPIO_ACTIVE_HIGH> + MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x16 >; }; - pinctrl_i2c2_1: i2c2-1grp { + pinctrl_key_can2: key-can2grp { fsl,pins = < -#define GP_I2C2_SCL <&gpio5 16 GPIO_OPEN_DRAIN> - MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c3 -#define GP_I2C2_SDA <&gpio5 17 GPIO_OPEN_DRAIN> - MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c3 +#define GP_CAN2_DETECT <&gpio4 23 GPIO_ACTIVE_HIGH> + MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x180 >; }; - pinctrl_i2c3: i2c3grp { + pinctrl_hog: hoggrp { fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 - MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019 + MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x119 + /* J31 */ + MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x41 /* Pin 17 */ + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x41 /* Pin 19 */ + MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x41 /* Pin 21 */ + MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x41 /* Pin 23 */ + MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x41 /* Pin 25 */ + MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x41 /* Pin 29 */ + MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x41 /* Pin 31 */ + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x16 /* Pin 2 */ + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c4 /* Pin 4 */ >; }; - pinctrl_i2c3_1: i2c3-1grp { + pinctrl_i2c2_pca9546: i2c2-pca9546grp { fsl,pins = < -#define GP_I2C3_SCL <&gpio5 18 GPIO_OPEN_DRAIN> - MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c3 -#define GP_I2C3_SDA <&gpio5 19 GPIO_OPEN_DRAIN> - MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c3 +#define GP_PCA9546_RESET <&gpio1 5 GPIO_ACTIVE_LOW> + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x100 >; }; - pinctrl_i2c4: i2c4grp { + pinctrl_i2c2d_rv3028: i2c2d-rv3028grp { fsl,pins = < - MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 - MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 +#define GPIRQ_RV3028 <&gpio1 4 IRQ_TYPE_LEVEL_LOW> + MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x1c0 >; }; - pinctrl_i2c4_1: i2c4-1grp { + pinctrl_i2c4_hd3ss3220: i2c4-hd3ss3220grp { fsl,pins = < -#define GP_I2C4_SCL <&gpio5 20 GPIO_OPEN_DRAIN> - MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x1c3 -#define GP_I2C4_SDA <&gpio5 21 GPIO_OPEN_DRAIN> - MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c3 +#define GPIRQ_HD3SS3220 <&gpio1 8 IRQ_TYPE_LEVEL_LOW> + MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x16 + MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x03 >; }; - pinctrl_reg_wlan_vmmc: reg-wlan-vmmcgrp { + pinctrl_pdm: pdmgrp { fsl,pins = < -#define GP_REG_WLAN_VMMC <&gpio2 19 GPIO_ACTIVE_HIGH> - MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x16 + MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_PDM_CLK 0xd6 + MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_PDM_BIT_STREAM00 0xd6 >; }; pinctrl_pcie: pciegrp { fsl,pins = < -#define GP_PCIE_RESET <&gpio1 11 GPIO_ACTIVE_LOW> - MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x41 -/*#define GP_PCIE_DISABLE <&gpio4 26 GPIO_ACTIVE_LOW> - MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x41*/ +#define GP_PCIE_RESET <&gpio4 29 GPIO_ACTIVE_LOW> + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x41 +#define GP_PCIE_DISABLE <&gpio4 26 GPIO_ACTIVE_LOW> + MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x41 >; }; - pinctrl_pmic: pmicirq { + pinctrl_pwm4: pwm4grp { fsl,pins = < -#define GPIRQ_PMIC <&gpio3 0 IRQ_TYPE_LEVEL_LOW> - MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x41 + /* J31, pin 36 */ + MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x116 >; }; - /* pinctrl_pwm1: pwm1grp { + pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp { fsl,pins = < - //MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x100 - //MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x149 - // backlight enable - //MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x100 +#define GP_REG_USB_OTG_VBUS <&gpio1 12 GPIO_ACTIVE_HIGH> + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x100 >; - };*/ + }; - pinctrl_edp_bridge: edpbridgegrp { + pinctrl_sai3: sai3grp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x100 + /* WM8960 */ + MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0xd6 + MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 >; }; - pinctrl_uart1: uart1grp { + pinctrl_sound_wm8960: sound-wm8960grp { fsl,pins = < - MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 - MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 - MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 - MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 +#define GP_WM8960_MIC_DET <&gpio4 18 GPIO_ACTIVE_HIGH> + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x1c0 +#define GP_WM8960_HP_DET <&gpio1 14 GPIO_ACTIVE_HIGH> + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x80 >; }; @@ -227,6 +207,19 @@ >; }; + pinctrl_usb3_0: usb3-0grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO13__USB1_OC 0x1c0 + >; + }; + + pinctrl_usb3_1: usb3-1grp { + fsl,pins = < +#define GP_USB3_1_HUB_RESET <&gpio1 10 GPIO_ACTIVE_LOW> + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO10 0x100 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 @@ -235,7 +228,7 @@ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 - //MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT 0x116 + MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT 0x116 >; }; @@ -267,140 +260,36 @@ MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x1c4 >; }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 - >; - }; - - pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 -#define GP_EMMC_RESET <&gpio3 1 IRQ_TYPE_LEVEL_LOW> - MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x140 - >; - }; - - pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { - fsl,pins = < - MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 - MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 - MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 - MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 - MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 - MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 - MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 - MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 - MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 - MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 - >; - }; }; / { - model = "MNT Reform with i.MX8MP Module"; - compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8mp-som", "fsl,imx8mp"; - chassis-type = "laptop"; + model = "MNT Reform 2 with i.MX8MP Module"; + compatible = "boundary,imx8mp-nitrogen8mp", "fsl,imx8mp"; - chosen { - stdout-path = &uart2; + aliases { + fb_hdmi = &lcdif3; + sound_hdmi = &sound_hdmi; }; - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0 0x80000000>; + chosen { + stdout-path = &uart2; }; - bt-rfkill { - compatible = "net,rfkill-gpio"; + gpio_keys: gpio-keys { + compatible = "gpio-keys"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_bt_rfkill>; - name = "bt-rfkill"; - type = <2>; /* Bluetooth */ - reset-gpios = GP_BT_RFKILL_RESET; - status = "okay"; - }; + pinctrl-0 = <&pinctrl_key_can1>, <&pinctrl_key_can2>; + + can1 { + label = "can1 detect"; + gpios = GP_CAN1_DETECT; + linux,code = <KEY_1>; + }; - backlight: backlight { - compatible = "pwm-backlight"; - // FIXME - pwms = <&pwm2 0 10000 0>; - power-supply = <®_main_usb>; - // FIXME - //enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - enable-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; - brightness-levels = <0 32 64 128 160 200 255>; - default-brightness-level = <6>; - }; - - panel { - compatible = "innolux,n125hce-gn1", "simple-panel"; - power-supply = <®_main_3v3>; - backlight = <&backlight>; - no-hpd; - - port { - panel_in: endpoint { - remote-endpoint = <&edp_bridge_out>; - }; + can2 { + label = "can2 detect"; + gpios = GP_CAN2_DETECT; + linux,code = <KEY_2>; }; }; @@ -410,483 +299,273 @@ clock-frequency = <100000000>; }; - reg_main_5v: regulator-main-5v { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_main_3v3: regulator-main-3v3 { + reg_can1_stby: regulator-can1-stby { compatible = "regulator-fixed"; - regulator-name = "3V3"; + regulator-name = "can1-stby"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_reg>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + gpio = GP_CAN1_STANDBY; + enable-active-high; }; - reg_main_usb: regulator-main-usb { - compatible = "regulator-fixed"; - regulator-name = "USB_PWR"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <®_main_5v>; - }; - - reg_main_1v8: regulator-main-1v8 { - compatible = "regulator-fixed"; - regulator-name = "1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <®_main_3v3>; - }; - - reg_main_1v2: regulator-main-1v2 { - compatible = "regulator-fixed"; - regulator-name = "1V2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - vin-supply = <®_main_5v>; - }; - - reg_wlan_vmmc: regulator-wlan-vmmc { + reg_can2_stby: regulator-can2-stby { compatible = "regulator-fixed"; + regulator-name = "can2-stby"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_wlan_vmmc>; - regulator-name = "reg_wlan_vmmc"; + pinctrl-0 = <&pinctrl_flexcan2_reg>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = GP_REG_WLAN_VMMC; - startup-delay-us = <70000>; + gpio = GP_CAN2_STANDBY; enable-active-high; }; - reg_pcie0: regulator-pcie { + reg_usb_otg_vbus: regulator-usb-otg-vbus { compatible = "regulator-fixed"; - regulator-name = "MPCIE_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <®_main_5v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = GP_REG_USB_OTG_VBUS; + enable-active-high; }; -}; -&snvs_rtc { - status = "disabled"; + sound_hdmi: sound-hdmi { + compatible = "fsl,imx-audio-hdmi"; + model = "audio-hdmi"; +#ifndef UBOOT + audio-cpu = <&aud2htx>; +#endif + hdmi-out; + constraint-rate = <44100>, + <88200>, + <176400>, + <32000>, + <48000>, + <96000>, + <192000>; + status = "okay"; + }; }; -&uart1 { /* BT */ +&fec { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - assigned-clocks = <&clk IMX8MP_CLK_UART1>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; - uart-has-rtscts; + pinctrl-0 = <&pinctrl_fec>; +#if 0 + phy-reset-gpios = GP_FEC_RESET; +#endif + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; status = "okay"; -}; -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; + mdio { + #address-cells = <1>; + #size-cells = <0>; -&usb3_phy0 { - status = "okay"; + ethphy1: ethernet-phy { + compatible = "ethernet-phy-ieee802.3-c22"; + eee-broken-1000t; + interrupts-extended = GPIRQ_FEC_PHY; + reg-mask = <0x90>; + }; + }; }; -&usb3_phy1 { +&hdmi { status = "okay"; }; -&usb_dwc3_0 { - dr_mode = "host"; +&hdmiphy { status = "okay"; }; -&usb_dwc3_1 { - dr_mode = "host"; +&hdmi_pavi { status = "okay"; }; -&pwm1 { - //pinctrl-names = "default"; - //pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; +&i2c3 { + rtc@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + }; }; -&pwm2 { - //pinctrl-names = "default"; - //pinctrl-0 = <&pinctrl_pwm2>; +#ifndef UBOOT +&pcie { + assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; + assigned-clock-rates = <10000000>; + clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, + <&clk IMX8MP_CLK_PCIE_ROOT>, + <&clk IMX8MP_CLK_HSIO_AXI>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + disable-gpio = GP_PCIE_DISABLE; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = GP_PCIE_RESET; status = "okay"; }; -&usb3_0 { +&pcie_phy { + fsl,clkreq-unsupported; + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; + clocks = <&pcie0_refclk>; + clock-names = "ref"; status = "okay"; }; +#endif -&usb3_1 { +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; status = "okay"; }; -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - timeout-sec = <7200>; - status = "ok"; -}; -&wdog2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - timeout-sec = <7200>; - status = "ok"; -}; -&wdog3 { +&uart2 { + /* console */ pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - fsl,ext-reset-output; - timeout-sec = <7200>; - status = "ok"; -}; - -&i2c1 { - clock-frequency = <400000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c1>; - pinctrl-1 = <&pinctrl_i2c1_1>; - scl-gpios = GP_I2C1_SCL; - sda-gpios = GP_I2C1_SDA; + pinctrl-0 = <&pinctrl_uart2>; status = "okay"; - - pmic: pca9450@25 { - reg = <0x25>; - compatible = "nxp,pca9450c"; - /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ - pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - regulators { - buck1: BUCK1 { - regulator-name = "BUCK1"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - }; - - buck2: BUCK2 { - regulator-name = "BUCK2"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; - regulator-limit-microvolt = <1025000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <950000>; - nxp,dvs-standby-voltage = <850000>; - }; - - buck4: BUCK4 { - regulator-name = "BUCK4"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck5: BUCK5 { - regulator-name = "BUCK5"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - buck6: BUCK6 { - regulator-name = "BUCK6"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1: LDO1 { - regulator-name = "LDO1"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2: LDO2 { - regulator-name = "LDO2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3: LDO3 { - regulator-name = "LDO3"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4: LDO4 { - regulator-name = "LDO4"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5: LDO5 { - regulator-name = "LDO5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; - -&A53_0 { - cpu-supply = <&buck2>; -}; - -&A53_1 { - cpu-supply = <&buck2>; -}; - -&A53_2 { - cpu-supply = <&buck2>; }; -&A53_3 { - cpu-supply = <&buck2>; -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c2>; - pinctrl-1 = <&pinctrl_i2c2_1>; - scl-gpios = GP_I2C2_SCL; - sda-gpios = GP_I2C2_SDA; +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MP_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; status = "okay"; }; -&i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c3>; - pinctrl-1 = <&pinctrl_i2c3_1>; - scl-gpios = GP_I2C3_SCL; - sda-gpios = GP_I2C3_SDA; +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + assigned-clocks = <&clk IMX8MP_CLK_UART4>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; status = "okay"; - - rtc@68 { - compatible = "nxp,pcf8523"; - reg = <0x68>; - }; }; -&i2c4 { - clock-frequency = <100000>; - pinctrl-names = "default", "gpio"; - pinctrl-0 = <&pinctrl_i2c4>; - pinctrl-1 = <&pinctrl_i2c4_1>; - scl-gpios = GP_I2C4_SCL; - sda-gpios = GP_I2C4_SDA; +&usb3_0 { + fsl,disable-port-power-control; + fsl,over-current-active-low; status = "okay"; - - edp_bridge: bridge@2c { - compatible = "ti,sn65dsi86"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_edp_bridge>; - reg = <0x2c>; - enable-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; - vccio-supply = <®_main_1v8>; - vpll-supply = <®_main_1v8>; - vcca-supply = <®_main_1v2>; - vcc-supply = <®_main_1v2>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - edp_bridge_in: endpoint { - remote-endpoint = <&mipi_dsi_out>; - }; - }; - - port@1 { - reg = <1>; - - edp_bridge_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; - }; }; -&mipi_dsi { +&usb3_1 { + fsl,disable-port-power-control; status = "okay"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - mipi_dsi_out: endpoint { - remote-endpoint = <&edp_bridge_in>; - }; - }; - }; }; -&lcdif1 { +&usb_dwc3_0 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3_0>; status = "okay"; }; -&lcdif3 { +&usb_dwc3_1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3_1>; + reset-gpios = GP_USB3_1_HUB_RESET; status = "okay"; }; -&eqos { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy0>; +&usb3_phy0 { + fsl,phy-tx-preemp-amp-tune = <2>; status = "okay"; - - mdio { - compatible = "snps,dwmac-mdio"; - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@4 { - reg = <4>; - compatible = "ethernet-phy-ieee802.3-c22"; - at803x,hib-disabled; - eee-broken-1000t; - interrupts-extended = GPIRQ_EQOS_PHY; -#if 0 - reset-gpios = GP_EQOS_RESET; -#endif - reg-mask = <0x90>; - }; - }; + vbus-supply = <®_vref_5v0>; }; -// apparently FEC can be run via SAI1 pins -/*&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec>; - phy-mode = "rgmii-id"; - phy-handle = <ðphy1>; - fsl,magic-packet; +&usb3_phy1 { + fsl,phy-tx-preemp-amp-tune = <2>; status = "okay"; + vbus-supply = <®_vref_5v0>; +}; - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy { - compatible = "ethernet-phy-ieee802.3-c22"; - eee-broken-1000t; - interrupts-extended = GPIRQ_FEC_PHY; - reg-mask = <0x90>; - }; - }; -};*/ - -// SD Card &usdhc1 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC1_ROOT>; - assigned-clock-rates = <400000000>; bus-width = <4>; cd-gpios = GP_USDHC1_CD; - pinctrl-names = "default"; //, "state_100mhz", "state_200mhz"; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; + /*pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;*/ status = "okay"; - vmmc-supply = <®_main_3v3>; - vqmmc-supply = <®_main_3v3>; + vmmc-supply = <®_vref_3v3>; + vqmmc-supply = <®_vref_3v3>; }; -// SDIO (wifi/bt qca9733) -&usdhc2 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC2_ROOT>; - assigned-clock-rates = <200000000>; - bus-width = <4>; - //fsl,sdio-async-interrupt-enabled; // needs patch https://www.spinics.net/lists/linux-mmc/msg65247.html - keep-power-in-suspend; - no-sd-uhs-sdr104; - sd-uhs-ddr50; - no-mmc; - no-sd; - //no-cqe; - non-removable; - cap-sdio-irq; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - pm-ignore-notify; - status = "okay"; - vmmc-supply = <®_wlan_vmmc>; - vqmmc-1-8-v; - vqmmc-supply = <®_main_1v8>; -}; +/* J11 mipi display */ +#define MIPI_DSI mipi_dsi +#define MIPI_DISPLAY lcdif1 +#define MIPI_SUBSYSTEM display_subsystem +#define MIPI_I2C_BUS i2c2d +#define SKIP_LONTIUM_DAUGHTER_BOARDS /* MIPI_I2C_BUS is already behind i2cmux */ +#define MIPI_PHY_CLOCK <&mipi_dsi 0> +#define MIPI_PIXEL_CLOCK <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT> -// emmc -&usdhc3 { - bus-width = <4>; // FIXME was 8 - no-mmc-hs400; - non-removable; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - vmmc-supply = <®_main_3v3>; - vqmmc-1-8-v; - vqmmc-supply = <®_main_1v8>; - status = "okay"; -}; +#define MIPI_PWM pwm1 +#define GP_MIPI_PWM(a) <&gpio1 1 a> +#define PD_MIPI_PWM(a) MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 a /* Pin 7 */ +#define PD_MIPI_PWM_OUT(a) MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT a -&pcie_phy { - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; - clocks = <&hsio_blk_ctrl>; - phy-supply = <®_pcie0>; - clock-names = "ref"; - status = "okay"; - fsl,clkreq-unsupported; -}; +#define GP_MIPI_IRQ(a) <&gpio4 0 a> +#define PD_MIPI_IRQ(a) MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 a /* Pin 8 */ -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; - reset-gpio = GP_PCIE_RESET; - //disable-gpio = GP_PCIE_DISABLE; - clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, - <&clk IMX8MP_CLK_PCIE_ROOT>, - <&clk IMX8MP_CLK_HSIO_AXI>; - clock-names = "pcie", "pcie_aux", "pcie_bus"; - assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; - assigned-clock-rates = <10000000>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; - vpcie-supply = <®_pcie0>; - vph-supply = <®_pcie0>; - status = "okay"; +#define GP_MIPI_TS_IRQ(a) <&gpio4 25 a> +#define PD_MIPI_TS_IRQ(a) MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 a /* Pin 9 */ + +#define GP_MIPI_TS_RESET(a) <&gpio4 24 a> +#define PD_MIPI_TS_RESET(a) MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 a /* Pin 10 */ + +#define GP_MIPI_ENABLE(a) <&gpio4 27 a> +#define PD_MIPI_ENABLE(a) MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 a /* Pin 11 */ + +/* +#ifdef UBOOT +#include "bd-universal-mipi-dsi.dtsi" +#else +#include "../bd-universal-mipi-dsi.dtsi" +#endif + +#define LVDS_DISPLAY lcdif2 +#define LVDS_I2C_BUS i2c4 +#define LVDS_PWM pwm2 +#define LVDS2_PWM pwm2 +// J28 pin 20 LVDS display, J27 pin 20 LVDS2 display +#define PD_LVDS_PWM(a) MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT a MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT a + +#define GP_LVDS_BACKLIGHT(a) <&gpio4 22 a> +#define PD_LVDS_BACKLIGHT(a) MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 a + +#define GP_LVDS2_BACKLIGHT(a) <&gpio4 21 a> +#define PD_LVDS2_BACKLIGHT(a) MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 a + +#define GP_LVDS_TS_IRQ(a) <&gpio1 10 a> +#define PD_LVDS_TS_IRQ(a) MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 a + +// No pad associated with gpio3 30 +#define GP_LVDS_TS_RESET(a) <&gpio3 30 a> +#define PD_LVDS_TS_RESET(a) +#define LVDS_NO_TS_RESET +#ifdef UBOOT +#include "bd-universal-lvds.dtsi" +#else +#include "../bd-universal-lvds.dtsi" +#endif + +/ { + aliases { + // Old style aliases (without lvds) for older u-boots + // Delete upon next branch + ts_atmel_mt = &ts_lvds_atmel_mt; + ts_egalax = &ts_lvds_egalax; + ts_ft5x06_2 = &ts_lvds_ft5x06; + ts_goodix2 = &ts_lvds_goodix; + ts_goodix3 = &ts_lvds_goodix2; + ts_ili251x = &ts_lvds_ili251x; + }; }; +*/