[a311d] internal display (dsi) cannot be used at the same time as hdmi output

Currently only either the internal display or hdmi can be used individually but not at the same time. HDMI can be enabled using:

swaymsg output eDP-1 disable; swaymsg output HDMI-A-1 enable
swaymsg output HDMI-A-1 modeline 148.50 1920 2448 2492 2640 1080 1084 1089 1125 +hsync +vsync

You can switch back to the internal display and disable hdmi by running:

swaymsg output eDP-1 enable
swaymsg output HDMI-A-1 disable
swaymsg output eDP-1 enable
swaymsg output HDMI-A-1 disable

Driving both the internal display via dsi as well as hdmi at the same time is possible. There is a vendor kernel that can do it but zero documentation so somebody would have to investigate using the vendor kernel, dump all registers and go from there.

Another proof that this is working is the dreambox2 using a vendor kernel: https://www.amazon.co.uk/UHD4K-2xDVB-2X-Tuner-2160p-Linux/dp/B08HVNB3GD The sources seem to be here https://github.com/emanuel4you/linux-meson64 and dreambox seem to have been supportive of community efforts to run mainline kernels on their hardware: https://github.com/opendreambox/opendreambox

Quoting Neil Armstrong from #linux-amlogic (May 31 2024):

13:19 < narmstrong> minute: it must be possible, but there’s 0 documentation and no good source 
                    for reference, and I have 0 time to look into it, first step would be to make 
                    this use case work using an amlogic’s kernel and dump all registers
13:20 < narmstrong> Then we can try to replicate on upstream
13:44 < narmstrong> It’s on the pixel generation part (crtc & planes) the hdmi/dsi part won’t 
                    change, so the work it to understand how to enable the second vpp/viu and set 
                    the mux to forward the pixels to the hdmi or dsi encoders
13:48 < narmstrong> A key register is VPU_VIU_VENC_MUX_CTRL
13:48 < narmstrong> Where is connects the encoders to VIU1 and VIU2
13:50 < narmstrong> The clock goes from the encoder to the pixel generator, so the actual hdmi and 
                    dsi code won’t change since we already support clocking for HDMI and dsi at 
                    the same time
13:51 < narmstrong> So we must figure how vpp2 and viu2 works (like is there separate planes or 
                    shared planes, separate or shared scalers), the power domains clocks to 
                    enable, and the corresponding drm plumbing to expose a second crtc and setup 
                    VPU_VIU_VENC_MUX_CTRL accordingly