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arch/arm/dts/imx8mm-nitrogen8mm_rev2.dts 0 → 100644
View file @ 8e809399
/*
* Copyright 2018 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "imx8mm-nitrogen8mm.dts"
/ {
model = "Boundary Devices i.MX8MMini Nitrogen8MM Rev2";
compatible = "boundary,imx8mm-nitrogen8mm_rev2", "fsl,imx8mm";
};
&wdog1 {
/delete-property/ reset-gpios;
};
arch/arm/dts/imx8mm-nitrogen8mm_som.dts 0 → 100644
View file @ 8e809399
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 Boundary Devices
*/
#include "imx8mm-nitrogen8mm.dts"
&iomuxc_pinctrl {
pinctrl_i2c2_sn65dsi83: i2c2-sn65dsi83grp {
fsl,pins = <
#define GPIRQ_I2C2_SN65DSI83 <&gpio1 1 IRQ_TYPE_LEVEL_HIGH>
MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x04
#undef GP_I2C2_SN65DSI83_EN
#define GP_I2C2_SN65DSI83_EN <&gpio5 0 GPIO_ACTIVE_HIGH>
MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0 0x106
>;
};
/delete-node/ i2c3a-rv4162grp;
/delete-node/ i2c3b-csi1grp;
pinctrl_i2c2_rv4162: i2c2-rv4162grp {
fsl,pins = <
#undef GPIRQ_RV4162
#define GPIRQ_RV4162 <&gpio1 3 IRQ_TYPE_LEVEL_LOW>
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
>;
};
pinctrl_i2c3_csi1: i2c3-csi1grp {
fsl,pins = <
#undef GP_CSI1_MIPI_PWDN
#define GP_CSI1_MIPI_PWDN <&gpio1 11 GPIO_ACTIVE_HIGH>
MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x141
#undef GP_CSI1_MIPI_RESET
#define GP_CSI1_MIPI_RESET <&gpio1 9 GPIO_ACTIVE_LOW>
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x101
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x16
>;
};
pinctrl_usbotg2: usbotg2grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO14_USB2_OTG_PWR 0x16
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16
>;
};
};
/ {
model = "Boundary Devices i.MX8MMini Nitrogen8MM Som";
compatible = "boundary,imx8mm-nitrogen8mm_som", "fsl,imx8mm";
};
&i2c2 {
rtc@68 {
compatible = "microcrystal,rv4162";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_rv4162>;
reg = <0x68>;
interrupts-extended = GPIRQ_RV4162;
wakeup-source;
};
};
&i2c3 {
/delete-node/ i2cmux@70;
};
&usbotg2 {
disable-over-current;
};
arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi 0 → 100644
View file @ 8e809399
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
*/
&{/soc@0} {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
&clk {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&osc_24m {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&aips1 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&aips2 {
u-boot,dm-spl;
};
&aips3 {
u-boot,dm-spl;
};
&iomuxc {
u-boot,dm-spl;
};
&pinctrl_reg_usdhc2_vmmc {
u-boot,dm-spl;
};
&pinctrl_uart2 {
u-boot,dm-spl;
};
&pinctrl_usdhc2_gpio {
u-boot,dm-spl;
};
&pinctrl_usdhc2 {
u-boot,dm-spl;
};
&pinctrl_usdhc3 {
u-boot,dm-spl;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&uart2 {
u-boot,dm-spl;
};
&usdhc1 {
u-boot,dm-spl;
};
&usdhc2 {
u-boot,dm-spl;
};
&usdhc3 {
u-boot,dm-spl;
};
arch/arm/dts/imx8mn-ddr4-evk.dts 0 → 100644
View file @ 8e809399
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 NXP
*/
/dts-v1/;
#include "imx8mn.dtsi"
/ {
model = "NXP i.MX8MNano DDR4 EVK board";
compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn";
chosen {
stdout-path = &uart2;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
>;
};
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
fsl,pins = <
MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
pinctrl_usdhc2_gpio: usdhc2grpgpio {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
at803x,led-act-blind-workaround;
at803x,eee-disabled;
at803x,vddio-1p8v;
};
};
};
&snvs_pwrkey {
status = "okay";
};
&uart2 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
arch/arm/dts/imx8mn-pinfunc.h 0 → 100644
View file @ 8e809399
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2019 NXP
*
*/
#ifndef __DTS_IMX8MN_PINFUNC_H
#define __DTS_IMX8MN_PINFUNC_H
/*
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x0020 0x025C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x0020 0x025C 0x055C 0x1 0x3
#define MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x0024 0x0260 0x0000 0x0 0x0
#define MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x0024 0x0260 0x056C 0x1 0x3
#define MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x0028 0x0290 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x0028 0x0290 0x0000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x0028 0x0290 0x0000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x0028 0x0290 0x0000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x002C 0x0294 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x002C 0x0294 0x0000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x002C 0x0294 0x0000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x002C 0x0294 0x0000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x0030 0x0298 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x0030 0x0298 0x0000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x0030 0x0298 0x0000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x0034 0x029C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x0034 0x029C 0x0000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x0034 0x029C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK 0x0034 0x029C 0x0000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x0038 0x02A0 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0038 0x02A0 0x0000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x0038 0x02A0 0x0000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV 0x0038 0x02A0 0x0000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x003C 0x02A4 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO05_M4_NMI 0x003C 0x02A4 0x0000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY 0x003C 0x02A4 0x04BC 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT 0x003C 0x02A4 0x0000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x0040 0x02A8 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO06_ENET1_MDC 0x0040 0x02A8 0x0000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x0040 0x02A8 0x0000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3 0x0040 0x02A8 0x0000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x0044 0x02AC 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO07_ENET1_MDIO 0x0044 0x02AC 0x04C0 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO07_USDHC1_WP 0x0044 0x02AC 0x0000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4 0x0044 0x02AC 0x0000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x0048 0x02B0 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x0048 0x02B0 0x0000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO08_PWM1_OUT 0x0048 0x02B0 0x0000 0x2 0x0
#define MX8MN_IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x0048 0x02B0 0x0000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT 0x0048 0x02B0 0x0000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x004C 0x02B4 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x004C 0x02B4 0x0000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO09_PWM2_OUT 0x004C 0x02B4 0x0000 0x2 0x0
#define MX8MN_IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x004C 0x02B4 0x0000 0x4 0x0
#define MX8MN_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x004C 0x02B4 0x0000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP 0x004C 0x02B4 0x0000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0050 0x02B8 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x0050 0x02B8 0x0000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO10_PWM3_OUT 0x0050 0x02B8 0x0000 0x2 0x0
#define MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x0054 0x02BC 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO11_PWM2_OUT 0x0054 0x02BC 0x0000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x0054 0x02BC 0x0000 0x4 0x0
#define MX8MN_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY 0x0054 0x02BC 0x04BC 0x5 0x1
#define MX8MN_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0 0x0054 0x02BC 0x0000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x0058 0x02C0 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x0058 0x02C0 0x0000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x0058 0x02C0 0x0000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1 0x0058 0x02C0 0x0000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x005C 0x02C4 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x005C 0x02C4 0x0000 0x1 0x0
#define MX8MN_IOMUXC_GPIO1_IO13_PWM2_OUT 0x005C 0x02C4 0x0000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2 0x005C 0x02C4 0x0000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x0060 0x02C8 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x0060 0x02C8 0x0598 0x4 0x2
#define MX8MN_IOMUXC_GPIO1_IO14_PWM3_OUT 0x0060 0x02C8 0x0000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x0060 0x02C8 0x0000 0x6 0x0
#define MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x0064 0x02CC 0x0000 0x0 0x0
#define MX8MN_IOMUXC_GPIO1_IO15_USDHC3_WP 0x0064 0x02CC 0x05B8 0x4 0x2
#define MX8MN_IOMUXC_GPIO1_IO15_PWM4_OUT 0x0064 0x02CC 0x0000 0x5 0x0
#define MX8MN_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x0064 0x02CC 0x0000 0x6 0x0
#define MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x0068 0x02D0 0x0000 0x0 0x0
#define MX8MN_IOMUXC_ENET_MDC_SAI6_TX_DATA0 0x0068 0x02D0 0x0000 0x2 0x0
#define MX8MN_IOMUXC_ENET_MDC_PDM_BIT_STREAM3 0x0068 0x02D0 0x0540 0x3 0x1
#define MX8MN_IOMUXC_ENET_MDC_SPDIF1_OUT 0x0068 0x02D0 0x0000 0x4 0x0
#define MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x0068 0x02D0 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ENET_MDC_USDHC3_STROBE 0x0068 0x02D0 0x059C 0x6 0x1
#define MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x006C 0x02D4 0x04C0 0x0 0x1
#define MX8MN_IOMUXC_ENET_MDIO_SAI6_TX_SYNC 0x006C 0x02D4 0x0000 0x2 0x0
#define MX8MN_IOMUXC_ENET_MDIO_PDM_BIT_STREAM2 0x006C 0x02D4 0x053C 0x3 0x1
#define MX8MN_IOMUXC_ENET_MDIO_SPDIF1_IN 0x006C 0x02D4 0x05CC 0x4 0x1
#define MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x006C 0x02D4 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ENET_MDIO_USDHC3_DATA5 0x006C 0x02D4 0x0550 0x6 0x1
#define MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x0070 0x02D8 0x0000 0x0 0x0
#define MX8MN_IOMUXC_ENET_TD3_SAI6_TX_BCLK 0x0070 0x02D8 0x0000 0x2 0x0
#define MX8MN_IOMUXC_ENET_TD3_PDM_BIT_STREAM1 0x0070 0x02D8 0x0538 0x3 0x1
#define MX8MN_IOMUXC_ENET_TD3_SPDIF1_EXT_CLK 0x0070 0x02D8 0x0568 0x4 0x1
#define MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x0070 0x02D8 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ENET_TD3_USDHC3_DATA6 0x0070 0x02D8 0x0584 0x6 0x1
#define MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x0074 0x02DC 0x0000 0x0 0x0
#define MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x0074 0x02DC 0x05A4 0x1 0x0
#define MX8MN_IOMUXC_ENET_TD2_CCMSRCGPCMIX_ENET_REF_CLK_ROOT 0x0074 0x02DC 0x05A4 0x1 0x0
#define MX8MN_IOMUXC_ENET_TD2_SAI6_RX_DATA0 0x0074 0x02DC 0x0000 0x2 0x0
#define MX8MN_IOMUXC_ENET_TD2_PDM_BIT_STREAM3 0x0074 0x02DC 0x0540 0x3 0x2
#define MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x0074 0x02DC 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ENET_TD2_USDHC3_DATA7 0x0074 0x02DC 0x054C 0x6 0x1
#define MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x0078 0x02E0 0x0000 0x0 0x0
#define MX8MN_IOMUXC_ENET_TD1_SAI6_RX_SYNC 0x0078 0x02E0 0x0000 0x2 0x0
#define MX8MN_IOMUXC_ENET_TD1_PDM_BIT_STREAM2 0x0078 0x02E0 0x053C 0x3 0x2
#define MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x0078 0x02E0 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ENET_TD1_USDHC3_CD_B 0x0078 0x02E0 0x0598 0x6 0x3
#define MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x007C 0x02E4 0x0000 0x0 0x0
#define MX8MN_IOMUXC_ENET_TD0_SAI6_RX_BCLK 0x007C 0x02E4 0x0000 0x2 0x0
#define MX8MN_IOMUXC_ENET_TD0_PDM_BIT_STREAM1 0x007C 0x02E4 0x0538 0x3 0x2
#define MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x007C 0x02E4 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ENET_TD0_USDHC3_WP 0x007C 0x02E4 0x05B8 0x6 0x3
#define MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x0080 0x02E8 0x0000 0x0 0x0
#define MX8MN_IOMUXC_ENET_TX_CTL_SAI6_MCLK 0x0080 0x02E8 0x0000 0x2 0x0
#define MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x0080 0x02E8 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ENET_TX_CTL_USDHC3_DATA0 0x0080 0x02E8 0x05B4 0x6 0x1
#define MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x0084 0x02EC 0x0000 0x0 0x0
#define MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER 0x0084 0x02EC 0x0000 0x1 0x0
#define MX8MN_IOMUXC_ENET_TXC_SAI7_TX_DATA0 0x0084 0x02EC 0x0000 0x2 0x0
#define MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x0084 0x02EC 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ENET_TXC_USDHC3_DATA1 0x0084 0x02EC 0x05B0 0x6 0x1
#define MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x0088 0x02F0 0x0574 0x0 0x0
#define MX8MN_IOMUXC_ENET_RX_CTL_SAI7_TX_SYNC 0x0088 0x02F0 0x0000 0x2 0x0
#define MX8MN_IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM3 0x0088 0x02F0 0x0540 0x3 0x3
#define MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x0088 0x02F0 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ENET_RX_CTL_USDHC3_DATA2 0x0088 0x02F0 0x05E4 0x6 0x1
#define MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x008C 0x02F4 0x0000 0x0 0x0
#define MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 0x008C 0x02F4 0x05C8 0x1 0x0
#define MX8MN_IOMUXC_ENET_RXC_SAI7_TX_BCLK 0x008C 0x02F4 0x0000 0x2 0x0
#define MX8MN_IOMUXC_ENET_RXC_PDM_BIT_STREAM2 0x008C 0x02F4 0x053C 0x3 0x3
#define MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x008C 0x02F4 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ENET_RXC_USDHC3_DATA3 0x008C 0x02F4 0x05E0 0x6 0x1
#define MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x0090 0x02F8 0x057C 0x0 0x0
#define MX8MN_IOMUXC_ENET_RD0_SAI7_RX_DATA0 0x0090 0x02F8 0x0000 0x2 0x0
#define MX8MN_IOMUXC_ENET_RD0_PDM_BIT_STREAM1 0x0090 0x02F8 0x0538 0x3 0x3
#define MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x0090 0x02F8 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ENET_RD0_USDHC3_DATA4 0x0090 0x02F8 0x0558 0x6 0x1
#define MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x0094 0x02FC 0x0554 0x0 0x0
#define MX8MN_IOMUXC_ENET_RD1_SAI7_RX_SYNC 0x0094 0x02FC 0x0000 0x2 0x0
#define MX8MN_IOMUXC_ENET_RD1_PDM_BIT_STREAM0 0x0094 0x02FC 0x0534 0x3 0x1
#define MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x0094 0x02FC 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ENET_RD1_USDHC3_RESET_B 0x0094 0x02FC 0x0000 0x6 0x0
#define MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x0098 0x0300 0x0000 0x0 0x0
#define MX8MN_IOMUXC_ENET_RD2_SAI7_RX_BCLK 0x0098 0x0300 0x0000 0x2 0x0
#define MX8MN_IOMUXC_ENET_RD2_PDM_CLK 0x0098 0x0300 0x0000 0x3 0x0
#define MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x0098 0x0300 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ENET_RD2_USDHC3_CLK 0x0098 0x0300 0x05A0 0x6 0x1
#define MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x009C 0x0304 0x0000 0x0 0x0
#define MX8MN_IOMUXC_ENET_RD3_SAI7_MCLK 0x009C 0x0304 0x0000 0x2 0x0
#define MX8MN_IOMUXC_ENET_RD3_SPDIF1_IN 0x009C 0x0304 0x05CC 0x3 0x5
#define MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x009C 0x0304 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ENET_RD3_USDHC3_CMD 0x009C 0x0304 0x05DC 0x6 0x1
#define MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x00A0 0x0308 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD1_CLK_ENET1_MDC 0x00A0 0x0308 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SD1_CLK_UART1_DCE_TX 0x00A0 0x0308 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SD1_CLK_UART1_DTE_RX 0x00A0 0x0308 0x04F4 0x4 0x4
#define MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x00A0 0x0308 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x00A4 0x030C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD1_CMD_ENET1_MDIO 0x00A4 0x030C 0x04C0 0x1 0x3
#define MX8MN_IOMUXC_SD1_CMD_UART1_DCE_RX 0x00A4 0x030C 0x04F4 0x4 0x5
#define MX8MN_IOMUXC_SD1_CMD_UART1_DTE_TX 0x00A4 0x030C 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x00A4 0x030C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x00A8 0x0310 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD1_DATA0_ENET1_RGMII_TD1 0x00A8 0x0310 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SD1_DATA0_UART1_DCE_RTS_B 0x00A8 0x0310 0x04F0 0x4 0x4
#define MX8MN_IOMUXC_SD1_DATA0_UART1_DTE_CTS_B 0x00A8 0x0310 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SD1_DATA0_GPIO2_IO2 0x00A8 0x0310 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x00AC 0x0314 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD1_DATA1_ENET1_RGMII_TD0 0x00AC 0x0314 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SD1_DATA1_UART1_DCE_CTS_B 0x00AC 0x0314 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SD1_DATA1_UART1_DTE_RTS_B 0x00AC 0x0314 0x04F0 0x4 0x5
#define MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3 0x00AC 0x0314 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x00B0 0x0318 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD1_DATA2_ENET1_RGMII_RD0 0x00B0 0x0318 0x057C 0x1 0x1
#define MX8MN_IOMUXC_SD1_DATA2_UART2_DCE_TX 0x00B0 0x0318 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SD1_DATA2_UART2_DTE_RX 0x00B0 0x0318 0x04FC 0x4 0x4
#define MX8MN_IOMUXC_SD1_DATA2_GPIO2_IO4 0x00B0 0x0318 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x00B4 0x031C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD1_DATA3_ENET1_RGMII_RD1 0x00B4 0x031C 0x0554 0x1 0x1
#define MX8MN_IOMUXC_SD1_DATA3_UART2_DCE_RX 0x00B4 0x031C 0x04FC 0x4 0x5
#define MX8MN_IOMUXC_SD1_DATA3_UART2_DTE_TX 0x00B4 0x031C 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SD1_DATA3_GPIO2_IO5 0x00B4 0x031C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x00B8 0x0320 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD1_DATA4_ENET1_RGMII_TX_CTL 0x00B8 0x0320 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SD1_DATA4_I2C1_SCL 0x00B8 0x0320 0x055C 0x3 0x1
#define MX8MN_IOMUXC_SD1_DATA4_UART2_DCE_RTS_B 0x00B8 0x0320 0x04F8 0x4 0x4
#define MX8MN_IOMUXC_SD1_DATA4_UART2_DTE_CTS_B 0x00B8 0x0320 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00B8 0x0320 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x00BC 0x0324 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD1_DATA5_ENET1_TX_ER 0x00BC 0x0324 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SD1_DATA5_I2C1_SDA 0x00BC 0x0324 0x056C 0x3 0x1
#define MX8MN_IOMUXC_SD1_DATA5_UART2_DCE_CTS_B 0x00BC 0x0324 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SD1_DATA5_UART2_DTE_RTS_B 0x00BC 0x0324 0x04F8 0x4 0x5
#define MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x00BC 0x0324 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x00C0 0x0328 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD1_DATA6_ENET1_RGMII_RX_CTL 0x00C0 0x0328 0x0574 0x1 0x1
#define MX8MN_IOMUXC_SD1_DATA6_I2C2_SCL 0x00C0 0x0328 0x05D0 0x3 0x1
#define MX8MN_IOMUXC_SD1_DATA6_UART3_DCE_TX 0x00C0 0x0328 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SD1_DATA6_UART3_DTE_RX 0x00C0 0x0328 0x0504 0x4 0x4
#define MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00C0 0x0328 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x00C4 0x032C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD1_DATA7_ENET1_RX_ER 0x00C4 0x032C 0x05C8 0x1 0x1
#define MX8MN_IOMUXC_SD1_DATA7_I2C2_SDA 0x00C4 0x032C 0x0560 0x3 0x1
#define MX8MN_IOMUXC_SD1_DATA7_UART3_DCE_RX 0x00C4 0x032C 0x0504 0x4 0x5
#define MX8MN_IOMUXC_SD1_DATA7_UART3_DTE_TX 0x00C4 0x032C 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00C4 0x032C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x00C8 0x0330 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD1_RESET_B_ENET1_TX_CLK 0x00C8 0x0330 0x05A4 0x1 0x1
#define MX8MN_IOMUXC_SD1_RESET_B_CCMSRCGPCMIX_ENET_REF_CLK_ROOT 0x00C8 0x0330 0x05A4 0x1 0x0
#define MX8MN_IOMUXC_SD1_RESET_B_I2C3_SCL 0x00C8 0x0330 0x0588 0x3 0x1
#define MX8MN_IOMUXC_SD1_RESET_B_UART3_DCE_RTS_B 0x00C8 0x0330 0x0500 0x4 0x2
#define MX8MN_IOMUXC_SD1_RESET_B_UART3_DTE_CTS_B 0x00C8 0x0330 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x00C8 0x0330 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x00CC 0x0334 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD1_STROBE_I2C3_SDA 0x00CC 0x0334 0x05BC 0x3 0x1
#define MX8MN_IOMUXC_SD1_STROBE_UART3_DCE_CTS_B 0x00CC 0x0334 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SD1_STROBE_UART3_DTE_RTS_B 0x00CC 0x0334 0x0500 0x4 0x3
#define MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x00CC 0x0334 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x00D0 0x0338 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x00D0 0x0338 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD2_CD_B_CCMSRCGPCMIX_TESTER_ACK 0x00D0 0x0338 0x0000 0x6 0x0
#define MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x00D4 0x033C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD2_CLK_SAI5_RX_SYNC 0x00D4 0x033C 0x04E4 0x1 0x1
#define MX8MN_IOMUXC_SD2_CLK_ECSPI2_SCLK 0x00D4 0x033C 0x0580 0x2 0x1
#define MX8MN_IOMUXC_SD2_CLK_UART4_DCE_RX 0x00D4 0x033C 0x050C 0x3 0x4
#define MX8MN_IOMUXC_SD2_CLK_UART4_DTE_TX 0x00D4 0x033C 0x0000 0x3 0x0
#define MX8MN_IOMUXC_SD2_CLK_SAI5_MCLK 0x00D4 0x033C 0x0594 0x4 0x1
#define MX8MN_IOMUXC_SD2_CLK_GPIO2_IO13 0x00D4 0x033C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 0x00D4 0x033C 0x0000 0x6 0x0
#define MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x00D8 0x0340 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD2_CMD_SAI5_RX_BCLK 0x00D8 0x0340 0x04D0 0x1 0x1
#define MX8MN_IOMUXC_SD2_CMD_ECSPI2_MOSI 0x00D8 0x0340 0x0590 0x2 0x1
#define MX8MN_IOMUXC_SD2_CMD_UART4_DCE_TX 0x00D8 0x0340 0x0000 0x3 0x0
#define MX8MN_IOMUXC_SD2_CMD_UART4_DTE_RX 0x00D8 0x0340 0x050C 0x3 0x5
#define MX8MN_IOMUXC_SD2_CMD_PDM_CLK 0x00D8 0x0340 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SD2_CMD_GPIO2_IO14 0x00D8 0x0340 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 0x00D8 0x0340 0x0000 0x6 0x0
#define MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x00DC 0x0344 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD2_DATA0_SAI5_RX_DATA0 0x00DC 0x0344 0x04D4 0x1 0x1
#define MX8MN_IOMUXC_SD2_DATA0_I2C4_SDA 0x00DC 0x0344 0x058C 0x2 0x1
#define MX8MN_IOMUXC_SD2_DATA0_UART2_DCE_RX 0x00DC 0x0344 0x04FC 0x3 0x6
#define MX8MN_IOMUXC_SD2_DATA0_UART2_DTE_TX 0x00DC 0x0344 0x0000 0x3 0x0
#define MX8MN_IOMUXC_SD2_DATA0_PDM_BIT_STREAM0 0x00DC 0x0344 0x0534 0x4 0x2
#define MX8MN_IOMUXC_SD2_DATA0_GPIO2_IO15 0x00DC 0x0344 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 0x00DC 0x0344 0x0000 0x6 0x0
#define MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x00E0 0x0348 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD2_DATA1_SAI5_TX_SYNC 0x00E0 0x0348 0x04EC 0x1 0x1
#define MX8MN_IOMUXC_SD2_DATA1_I2C4_SCL 0x00E0 0x0348 0x05D4 0x2 0x1
#define MX8MN_IOMUXC_SD2_DATA1_UART2_DCE_TX 0x00E0 0x0348 0x0000 0x3 0x0
#define MX8MN_IOMUXC_SD2_DATA1_UART2_DTE_RX 0x00E0 0x0348 0x04FC 0x3 0x7
#define MX8MN_IOMUXC_SD2_DATA1_PDM_BIT_STREAM1 0x00E0 0x0348 0x0538 0x4 0x4
#define MX8MN_IOMUXC_SD2_DATA1_GPIO2_IO16 0x00E0 0x0348 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT 0x00E0 0x0348 0x0000 0x6 0x0
#define MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x00E4 0x034C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD2_DATA2_SAI5_TX_BCLK 0x00E4 0x034C 0x04E8 0x1 0x1
#define MX8MN_IOMUXC_SD2_DATA2_ECSPI2_SS0 0x00E4 0x034C 0x0570 0x2 0x2
#define MX8MN_IOMUXC_SD2_DATA2_SPDIF1_OUT 0x00E4 0x034C 0x0000 0x3 0x0
#define MX8MN_IOMUXC_SD2_DATA2_PDM_BIT_STREAM2 0x00E4 0x034C 0x053C 0x4 0x4
#define MX8MN_IOMUXC_SD2_DATA2_GPIO2_IO17 0x00E4 0x034C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP 0x00E4 0x034C 0x0000 0x6 0x0
#define MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x00E8 0x0350 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD2_DATA3_SAI5_TX_DATA0 0x00E8 0x0350 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SD2_DATA3_ECSPI2_MISO 0x00E8 0x0350 0x0578 0x2 0x1
#define MX8MN_IOMUXC_SD2_DATA3_SPDIF1_IN 0x00E8 0x0350 0x05CC 0x3 0x2
#define MX8MN_IOMUXC_SD2_DATA3_PDM_BIT_STREAM3 0x00E8 0x0350 0x0540 0x4 0x4
#define MX8MN_IOMUXC_SD2_DATA3_GPIO2_IO18 0x00E8 0x0350 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET 0x00E8 0x0350 0x0000 0x6 0x0
#define MX8MN_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x00EC 0x0354 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x00EC 0x0354 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET 0x00EC 0x0354 0x0000 0x6 0x0
#define MX8MN_IOMUXC_SD2_WP_USDHC2_WP 0x00F0 0x0358 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x00F0 0x0358 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SD2_WP_CORESIGHT_EVENTI 0x00F0 0x0358 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00F4 0x035C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x00F4 0x035C 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_ALE_PDM_BIT_STREAM0 0x00F4 0x035C 0x0534 0x3 0x3
#define MX8MN_IOMUXC_NAND_ALE_UART3_DCE_RX 0x00F4 0x035C 0x0504 0x4 0x6
#define MX8MN_IOMUXC_NAND_ALE_UART3_DTE_TX 0x00F4 0x035C 0x0000 0x4 0x0
#define MX8MN_IOMUXC_NAND_ALE_GPIO3_IO0 0x00F4 0x035C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK 0x00F4 0x035C 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00F8 0x0360 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x00F8 0x0360 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_CE0_B_PDM_BIT_STREAM1 0x00F8 0x0360 0x0538 0x3 0x5
#define MX8MN_IOMUXC_NAND_CE0_B_UART3_DCE_TX 0x00F8 0x0360 0x0000 0x4 0x0
#define MX8MN_IOMUXC_NAND_CE0_B_UART3_DTE_RX 0x00F8 0x0360 0x0504 0x4 0x7
#define MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x00F8 0x0360 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL 0x00F8 0x0360 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x00FC 0x0364 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x00FC 0x0364 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x00FC 0x0364 0x059C 0x2 0x0
#define MX8MN_IOMUXC_NAND_CE1_B_PDM_BIT_STREAM0 0x00FC 0x0364 0x0534 0x3 0x4
#define MX8MN_IOMUXC_NAND_CE1_B_I2C4_SCL 0x00FC 0x0364 0x05D4 0x4 0x2
#define MX8MN_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x00FC 0x0364 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_CE1_B_CORESIGHT_TRACE0 0x00FC 0x0364 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B 0x0100 0x0368 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x0100 0x0368 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x0100 0x0368 0x0550 0x2 0x0
#define MX8MN_IOMUXC_NAND_CE2_B_PDM_BIT_STREAM1 0x0100 0x0368 0x0538 0x3 0x6
#define MX8MN_IOMUXC_NAND_CE2_B_I2C4_SDA 0x0100 0x0368 0x058C 0x4 0x2
#define MX8MN_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x0100 0x0368 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_CE2_B_CORESIGHT_TRACE1 0x0100 0x0368 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B 0x0104 0x036C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x0104 0x036C 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x0104 0x036C 0x0584 0x2 0x0
#define MX8MN_IOMUXC_NAND_CE3_B_PDM_BIT_STREAM2 0x0104 0x036C 0x053C 0x3 0x5
#define MX8MN_IOMUXC_NAND_CE3_B_I2C3_SDA 0x0104 0x036C 0x05BC 0x4 0x2
#define MX8MN_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x0104 0x036C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_CE3_B_CORESIGHT_TRACE2 0x0104 0x036C 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_CLE_RAWNAND_CLE 0x0108 0x0370 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x0108 0x0370 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x0108 0x0370 0x054C 0x2 0x0
#define MX8MN_IOMUXC_NAND_CLE_GPIO3_IO5 0x0108 0x0370 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_CLE_CORESIGHT_TRACE3 0x0108 0x0370 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x010C 0x0374 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x010C 0x0374 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_DATA00_PDM_BIT_STREAM2 0x010C 0x0374 0x053C 0x3 0x6
#define MX8MN_IOMUXC_NAND_DATA00_UART4_DCE_RX 0x010C 0x0374 0x050C 0x4 0x6
#define MX8MN_IOMUXC_NAND_DATA00_UART4_DTE_TX 0x010C 0x0374 0x0000 0x4 0x0
#define MX8MN_IOMUXC_NAND_DATA00_GPIO3_IO6 0x010C 0x0374 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_DATA00_CORESIGHT_TRACE4 0x010C 0x0374 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x0110 0x0378 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x0110 0x0378 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_DATA01_PDM_BIT_STREAM3 0x0110 0x0378 0x0540 0x3 0x5
#define MX8MN_IOMUXC_NAND_DATA01_UART4_DCE_TX 0x0110 0x0378 0x0000 0x4 0x0
#define MX8MN_IOMUXC_NAND_DATA01_UART4_DTE_RX 0x0110 0x0378 0x050C 0x4 0x7
#define MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x0110 0x0378 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_DATA01_CORESIGHT_TRACE5 0x0110 0x0378 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x0114 0x037C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x0114 0x037C 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_DATA02_USDHC3_CD_B 0x0114 0x037C 0x0598 0x2 0x0
#define MX8MN_IOMUXC_NAND_DATA02_I2C4_SDA 0x0114 0x037C 0x058C 0x4 0x3
#define MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8 0x0114 0x037C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_DATA02_CORESIGHT_TRACE6 0x0114 0x037C 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x0118 0x0380 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x0118 0x0380 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_DATA03_USDHC3_WP 0x0118 0x0380 0x05B8 0x2 0x0
#define MX8MN_IOMUXC_NAND_DATA03_GPIO3_IO9 0x0118 0x0380 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_DATA03_CORESIGHT_TRACE7 0x0118 0x0380 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x011C 0x0384 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x011C 0x0384 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x011C 0x0384 0x05B4 0x2 0x0
#define MX8MN_IOMUXC_NAND_DATA04_GPIO3_IO10 0x011C 0x0384 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_DATA04_CORESIGHT_TRACE8 0x011C 0x0384 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x0120 0x0388 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x0120 0x0388 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x0120 0x0388 0x05B0 0x2 0x0
#define MX8MN_IOMUXC_NAND_DATA05_GPIO3_IO11 0x0120 0x0388 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_DATA05_CORESIGHT_TRACE9 0x0120 0x0388 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x0124 0x038C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x0124 0x038C 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x0124 0x038C 0x05E4 0x2 0x0
#define MX8MN_IOMUXC_NAND_DATA06_GPIO3_IO12 0x0124 0x038C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_DATA06_CORESIGHT_TRACE10 0x0124 0x038C 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x0128 0x0390 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x0128 0x0390 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x0128 0x0390 0x05E0 0x2 0x0
#define MX8MN_IOMUXC_NAND_DATA07_GPIO3_IO13 0x0128 0x0390 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_DATA07_CORESIGHT_TRACE11 0x0128 0x0390 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_DQS_RAWNAND_DQS 0x012C 0x0394 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_DQS_QSPI_A_DQS 0x012C 0x0394 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_DQS_PDM_CLK 0x012C 0x0394 0x0000 0x3 0x0
#define MX8MN_IOMUXC_NAND_DQS_I2C3_SCL 0x012C 0x0394 0x0588 0x4 0x2
#define MX8MN_IOMUXC_NAND_DQS_GPIO3_IO14 0x012C 0x0394 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_DQS_CORESIGHT_TRACE12 0x012C 0x0394 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x0130 0x0398 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_RE_B_QSPI_B_DQS 0x0130 0x0398 0x0000 0x1 0x0
#define MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x0130 0x0398 0x0558 0x2 0x0
#define MX8MN_IOMUXC_NAND_RE_B_PDM_BIT_STREAM1 0x0130 0x0398 0x0538 0x3 0x7
#define MX8MN_IOMUXC_NAND_RE_B_GPIO3_IO15 0x0130 0x0398 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_RE_B_CORESIGHT_TRACE13 0x0130 0x0398 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x0134 0x039C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x0134 0x039C 0x0000 0x2 0x0
#define MX8MN_IOMUXC_NAND_READY_B_PDM_BIT_STREAM3 0x0134 0x039C 0x0540 0x3 0x6
#define MX8MN_IOMUXC_NAND_READY_B_I2C3_SCL 0x0134 0x039C 0x0588 0x4 0x3
#define MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x0134 0x039C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_READY_B_CORESIGHT_TRACE14 0x0134 0x039C 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x0138 0x03A0 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x0138 0x03A0 0x05A0 0x2 0x0
#define MX8MN_IOMUXC_NAND_WE_B_I2C3_SDA 0x0138 0x03A0 0x05BC 0x4 0x3
#define MX8MN_IOMUXC_NAND_WE_B_GPIO3_IO17 0x0138 0x03A0 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_WE_B_CORESIGHT_TRACE15 0x0138 0x03A0 0x0000 0x6 0x0
#define MX8MN_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x013C 0x03A4 0x0000 0x0 0x0
#define MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x013C 0x03A4 0x05DC 0x2 0x0
#define MX8MN_IOMUXC_NAND_WP_B_I2C4_SDA 0x013C 0x03A4 0x058C 0x4 0x4
#define MX8MN_IOMUXC_NAND_WP_B_GPIO3_IO18 0x013C 0x03A4 0x0000 0x5 0x0
#define MX8MN_IOMUXC_NAND_WP_B_CORESIGHT_EVENTO 0x013C 0x03A4 0x0000 0x6 0x0
#define MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x0140 0x03A8 0x04E4 0x0 0x0
#define MX8MN_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x0140 0x03A8 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x0144 0x03AC 0x04D0 0x0 0x0
#define MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 0x0144 0x03AC 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x0144 0x03AC 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x0148 0x03B0 0x04D4 0x0 0x0
#define MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x0148 0x03B0 0x0534 0x4 0x0
#define MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x0148 0x03B0 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x014C 0x03B4 0x04D8 0x0 0x0
#define MX8MN_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x014C 0x03B4 0x04EC 0x3 0x0
#define MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x014C 0x03B4 0x0538 0x4 0x0
#define MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x014C 0x03B4 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x0150 0x03B8 0x04DC 0x0 0x0
#define MX8MN_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x0150 0x03B8 0x04E8 0x3 0x0
#define MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x0150 0x03B8 0x053C 0x4 0x0
#define MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x0150 0x03B8 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x0154 0x03BC 0x04E0 0x0 0x0
#define MX8MN_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x0154 0x03BC 0x0000 0x3 0x0
#define MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x0154 0x03BC 0x0540 0x4 0x0
#define MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x0154 0x03BC 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x0158 0x03C0 0x0594 0x0 0x0
#define MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x0158 0x03C0 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x01B0 0x0418 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x01B0 0x0418 0x04EC 0x1 0x2
#define MX8MN_IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x01B0 0x0418 0x0000 0x2 0x0
#define MX8MN_IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x01B0 0x0418 0x05AC 0x3 0x0
#define MX8MN_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x01B0 0x0418 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SAI2_RXFS_UART1_DTE_RX 0x01B0 0x0418 0x04F4 0x4 0x2
#define MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x01B0 0x0418 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI2_RXFS_PDM_BIT_STREAM2 0x01B0 0x0418 0x053C 0x6 0x7
#define MX8MN_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x01B4 0x041C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x01B4 0x041C 0x04E8 0x1 0x2
#define MX8MN_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x01B4 0x041C 0x04F4 0x4 0x3
#define MX8MN_IOMUXC_SAI2_RXC_UART1_DTE_TX 0x01B4 0x041C 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x01B4 0x041C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI2_RXC_PDM_BIT_STREAM1 0x01B4 0x041C 0x0538 0x6 0x8
#define MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x01B8 0x0420 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x01B8 0x0420 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SAI2_RXD0_SAI2_TX_DATA1 0x01B8 0x0420 0x0000 0x3 0x0
#define MX8MN_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x01B8 0x0420 0x04F0 0x4 0x2
#define MX8MN_IOMUXC_SAI2_RXD0_UART1_DTE_CTS_B 0x01B8 0x0420 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x01B8 0x0420 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI2_RXD0_PDM_BIT_STREAM3 0x01B8 0x0420 0x0540 0x6 0x7
#define MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x01BC 0x0424 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x01BC 0x0424 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x01BC 0x0424 0x0000 0x3 0x0
#define MX8MN_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x01BC 0x0424 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SAI2_TXFS_UART1_DTE_RTS_B 0x01BC 0x0424 0x04F0 0x4 0x3
#define MX8MN_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x01BC 0x0424 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI2_TXFS_PDM_BIT_STREAM2 0x01BC 0x0424 0x053C 0x6 0x8
#define MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x01C0 0x0428 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x01C0 0x0428 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25 0x01C0 0x0428 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI2_TXC_PDM_BIT_STREAM1 0x01C0 0x0428 0x0538 0x6 0x9
#define MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x01C4 0x042C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x01C4 0x042C 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x01C4 0x042C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI2_TXD0_CCMSRCGPCMIX_BOOT_MODE4 0x01C4 0x042C 0x0540 0x6 0x8
#define MX8MN_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x01C8 0x0430 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SAI2_MCLK_SAI5_MCLK 0x01C8 0x0430 0x0594 0x1 0x2
#define MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x01C8 0x0430 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI2_MCLK_SAI3_MCLK 0x01C8 0x0430 0x05C0 0x6 0x1
#define MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x01CC 0x0434 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x01CC 0x0434 0x05F0 0x1 0x0
#define MX8MN_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x01CC 0x0434 0x04E4 0x2 0x2
#define MX8MN_IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x01CC 0x0434 0x0000 0x3 0x0
#define MX8MN_IOMUXC_SAI3_RXFS_SPDIF1_IN 0x01CC 0x0434 0x05CC 0x4 0x3
#define MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x01CC 0x0434 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI3_RXFS_PDM_BIT_STREAM0 0x01CC 0x0434 0x0534 0x6 0x5
#define MX8MN_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x01D0 0x0438 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SAI3_RXC_GPT1_CLK 0x01D0 0x0438 0x05E8 0x1 0x0
#define MX8MN_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x01D0 0x0438 0x04D0 0x2 0x2
#define MX8MN_IOMUXC_SAI3_RXC_SAI2_RX_DATA1 0x01D0 0x0438 0x05AC 0x3 0x2
#define MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x01D0 0x0438 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x01D0 0x0438 0x04F8 0x4 0x2
#define MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x01D0 0x0438 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI3_RXC_PDM_CLK 0x01D0 0x0438 0x0000 0x6 0x0
#define MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x01D4 0x043C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x01D4 0x043C 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x01D4 0x043C 0x04D4 0x2 0x2
#define MX8MN_IOMUXC_SAI3_RXD_SAI3_TX_DATA1 0x01D4 0x043C 0x0000 0x3 0x0
#define MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x01D4 0x043C 0x04F8 0x4 0x3
#define MX8MN_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x01D4 0x043C 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SAI3_RXD_GPIO4_IO30 0x01D4 0x043C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI3_RXD_PDM_BIT_STREAM1 0x01D4 0x043C 0x0538 0x6 0x10
#define MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x01D8 0x0440 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x01D8 0x0440 0x05EC 0x1 0x0
#define MX8MN_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x01D8 0x0440 0x04D8 0x2 0x1
#define MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x01D8 0x0440 0x0000 0x3 0x0
#define MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x01D8 0x0440 0x04FC 0x4 0x2
#define MX8MN_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x01D8 0x0440 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x01D8 0x0440 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI3_TXFS_PDM_BIT_STREAM3 0x01D8 0x0440 0x0540 0x6 0x9
#define MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x01DC 0x0444 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x01DC 0x0444 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x01DC 0x0444 0x04DC 0x2 0x1
#define MX8MN_IOMUXC_SAI3_TXC_SAI2_TX_DATA1 0x01DC 0x0444 0x0000 0x3 0x0
#define MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x01DC 0x0444 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x01DC 0x0444 0x04FC 0x4 0x3
#define MX8MN_IOMUXC_SAI3_TXC_GPIO5_IO0 0x01DC 0x0444 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI3_TXC_PDM_BIT_STREAM2 0x01DC 0x0444 0x053C 0x6 0x9
#define MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x01E0 0x0448 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x01E0 0x0448 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x01E0 0x0448 0x04E0 0x2 0x1
#define MX8MN_IOMUXC_SAI3_TXD_SPDIF1_EXT_CLK 0x01E0 0x0448 0x0568 0x4 0x2
#define MX8MN_IOMUXC_SAI3_TXD_GPIO5_IO1 0x01E0 0x0448 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI3_TXD_CCMSRCGPCMIX_BOOT_MODE5 0x01E0 0x0448 0x0000 0x6 0x0
#define MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0x01E4 0x044C 0x05C0 0x0 0x0
#define MX8MN_IOMUXC_SAI3_MCLK_PWM4_OUT 0x01E4 0x044C 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SAI3_MCLK_SAI5_MCLK 0x01E4 0x044C 0x0594 0x2 0x3
#define MX8MN_IOMUXC_SAI3_MCLK_SPDIF1_OUT 0x01E4 0x044C 0x0000 0x4 0x0
#define MX8MN_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x01E4 0x044C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SAI3_MCLK_SPDIF1_IN 0x01E4 0x044C 0x05CC 0x6 0x4
#define MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0x01E8 0x0450 0x0000 0x0 0x0
#define MX8MN_IOMUXC_SPDIF_TX_PWM3_OUT 0x01E8 0x0450 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x01E8 0x0450 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0x01EC 0x0454 0x05CC 0x0 0x0
#define MX8MN_IOMUXC_SPDIF_RX_PWM2_OUT 0x01EC 0x0454 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x01EC 0x0454 0x0000 0x5 0x0
#define MX8MN_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x01F0 0x0458 0x0568 0x0 0x0
#define MX8MN_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x01F0 0x0458 0x0000 0x1 0x0
#define MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x01F0 0x0458 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x01F4 0x045C 0x05D8 0x0 0x0
#define MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x01F4 0x045C 0x0504 0x1 0x0
#define MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX 0x01F4 0x045C 0x0000 0x1 0x0
#define MX8MN_IOMUXC_ECSPI1_SCLK_I2C1_SCL 0x01F4 0x045C 0x055C 0x2 0x2
#define MX8MN_IOMUXC_ECSPI1_SCLK_SAI5_RX_SYNC 0x01F4 0x045C 0x04DC 0x3 0x2
#define MX8MN_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x01F4 0x045C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x01F8 0x0460 0x05A8 0x0 0x0
#define MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x01F8 0x0460 0x0000 0x1 0x0
#define MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX 0x01F8 0x0460 0x0504 0x1 0x1
#define MX8MN_IOMUXC_ECSPI1_MOSI_I2C1_SDA 0x01F8 0x0460 0x056C 0x2 0x2
#define MX8MN_IOMUXC_ECSPI1_MOSI_SAI5_RX_BCLK 0x01F8 0x0460 0x04D0 0x3 0x3
#define MX8MN_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x01F8 0x0460 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x01FC 0x0464 0x05C4 0x0 0x0
#define MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x01FC 0x0464 0x0000 0x1 0x0
#define MX8MN_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B 0x01FC 0x0464 0x0500 0x1 0x0
#define MX8MN_IOMUXC_ECSPI1_MISO_I2C2_SCL 0x01FC 0x0464 0x05D0 0x2 0x2
#define MX8MN_IOMUXC_ECSPI1_MISO_SAI5_RX_DATA0 0x01FC 0x0464 0x04D4 0x3 0x3
#define MX8MN_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x01FC 0x0464 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x0200 0x0468 0x0564 0x0 0x0
#define MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x0200 0x0468 0x0500 0x1 0x1
#define MX8MN_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B 0x0200 0x0468 0x0000 0x1 0x0
#define MX8MN_IOMUXC_ECSPI1_SS0_I2C2_SDA 0x0200 0x0468 0x0560 0x2 0x2
#define MX8MN_IOMUXC_ECSPI1_SS0_SAI5_RX_DATA1 0x0200 0x0468 0x04D8 0x3 0x2
#define MX8MN_IOMUXC_ECSPI1_SS0_SAI5_TX_SYNC 0x0200 0x0468 0x04EC 0x4 0x3
#define MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x0200 0x0468 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x0204 0x046C 0x0580 0x0 0x0
#define MX8MN_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x0204 0x046C 0x050C 0x1 0x0
#define MX8MN_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX 0x0204 0x046C 0x0000 0x1 0x0
#define MX8MN_IOMUXC_ECSPI2_SCLK_I2C3_SCL 0x0204 0x046C 0x0588 0x2 0x4
#define MX8MN_IOMUXC_ECSPI2_SCLK_SAI5_RX_DATA2 0x0204 0x046C 0x0000 0x3 0x0
#define MX8MN_IOMUXC_ECSPI2_SCLK_SAI5_TX_BCLK 0x0204 0x046C 0x04E8 0x4 0x3
#define MX8MN_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x0204 0x046C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x0208 0x0470 0x0590 0x0 0x0
#define MX8MN_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x0208 0x0470 0x0000 0x1 0x0
#define MX8MN_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX 0x0208 0x0470 0x050C 0x1 0x1
#define MX8MN_IOMUXC_ECSPI2_MOSI_I2C3_SDA 0x0208 0x0470 0x05BC 0x2 0x4
#define MX8MN_IOMUXC_ECSPI2_MOSI_SAI5_RX_DATA3 0x0208 0x0470 0x04E0 0x3 0x2
#define MX8MN_IOMUXC_ECSPI2_MOSI_SAI5_TX_DATA0 0x0208 0x0470 0x0000 0x4 0x0
#define MX8MN_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x0208 0x0470 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x020C 0x0474 0x0578 0x0 0x0
#define MX8MN_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x020C 0x0474 0x0000 0x1 0x0
#define MX8MN_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B 0x020C 0x0474 0x0508 0x1 0x0
#define MX8MN_IOMUXC_ECSPI2_MISO_I2C4_SCL 0x020C 0x0474 0x05D4 0x2 0x3
#define MX8MN_IOMUXC_ECSPI2_MISO_SAI5_MCLK 0x020C 0x0474 0x0594 0x3 0x4
#define MX8MN_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x020C 0x0474 0x0000 0x5 0x0
#define MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x0210 0x0478 0x0570 0x0 0x0
#define MX8MN_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x0210 0x0478 0x0508 0x1 0x1
#define MX8MN_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B 0x0210 0x0478 0x0000 0x1 0x0
#define MX8MN_IOMUXC_ECSPI2_SS0_I2C4_SDA 0x0210 0x0478 0x058C 0x2 0x5
#define MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x0210 0x0478 0x0000 0x5 0x0
#define MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x0214 0x047C 0x055C 0x0 0x0
#define MX8MN_IOMUXC_I2C1_SCL_ENET1_MDC 0x0214 0x047C 0x0000 0x1 0x0
#define MX8MN_IOMUXC_I2C1_SCL_ECSPI1_SCLK 0x0214 0x047C 0x05D8 0x3 0x1
#define MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x0214 0x047C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x0218 0x0480 0x056C 0x0 0x0
#define MX8MN_IOMUXC_I2C1_SDA_ENET1_MDIO 0x0218 0x0480 0x04C0 0x1 0x2
#define MX8MN_IOMUXC_I2C1_SDA_ECSPI1_MOSI 0x0218 0x0480 0x05A8 0x3 0x1
#define MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x0218 0x0480 0x0000 0x5 0x0
#define MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x021C 0x0484 0x05D0 0x0 0x0
#define MX8MN_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x021C 0x0484 0x0000 0x1 0x0
#define MX8MN_IOMUXC_I2C2_SCL_USDHC3_CD_B 0x021C 0x0484 0x0598 0x2 0x1
#define MX8MN_IOMUXC_I2C2_SCL_ECSPI1_MISO 0x021C 0x0484 0x05C4 0x3 0x1
#define MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x021C 0x0484 0x0000 0x5 0x0
#define MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x0220 0x0488 0x0560 0x0 0x0
#define MX8MN_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x0220 0x0488 0x0000 0x1 0x0
#define MX8MN_IOMUXC_I2C2_SDA_USDHC3_WP 0x0220 0x0488 0x05B8 0x2 0x1
#define MX8MN_IOMUXC_I2C2_SDA_ECSPI1_SS0 0x0220 0x0488 0x0564 0x3 0x1
#define MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x0220 0x0488 0x0000 0x5 0x0
#define MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x0224 0x048C 0x0588 0x0 0x0
#define MX8MN_IOMUXC_I2C3_SCL_PWM4_OUT 0x0224 0x048C 0x0000 0x1 0x0
#define MX8MN_IOMUXC_I2C3_SCL_GPT2_CLK 0x0224 0x048C 0x0000 0x2 0x0
#define MX8MN_IOMUXC_I2C3_SCL_ECSPI2_SCLK 0x0224 0x048C 0x0580 0x3 0x2
#define MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x0224 0x048C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x0228 0x0490 0x05BC 0x0 0x0
#define MX8MN_IOMUXC_I2C3_SDA_PWM3_OUT 0x0228 0x0490 0x0000 0x1 0x0
#define MX8MN_IOMUXC_I2C3_SDA_GPT3_CLK 0x0228 0x0490 0x0000 0x2 0x0
#define MX8MN_IOMUXC_I2C3_SDA_ECSPI2_MOSI 0x0228 0x0490 0x0590 0x3 0x2
#define MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x0228 0x0490 0x0000 0x5 0x0
#define MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x022C 0x0494 0x05D4 0x0 0x0
#define MX8MN_IOMUXC_I2C4_SCL_PWM2_OUT 0x022C 0x0494 0x0000 0x1 0x0
#define MX8MN_IOMUXC_I2C4_SCL_ECSPI2_MISO 0x022C 0x0494 0x0578 0x3 0x2
#define MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x022C 0x0494 0x0000 0x5 0x0
#define MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x0230 0x0498 0x058C 0x0 0x0
#define MX8MN_IOMUXC_I2C4_SDA_PWM1_OUT 0x0230 0x0498 0x0000 0x1 0x0
#define MX8MN_IOMUXC_I2C4_SDA_ECSPI2_SS0 0x0230 0x0498 0x0570 0x3 0x1
#define MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x0230 0x0498 0x0000 0x5 0x0
#define MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x0234 0x049C 0x04F4 0x0 0x0
#define MX8MN_IOMUXC_UART1_RXD_UART1_DTE_TX 0x0234 0x049C 0x0000 0x0 0x0
#define MX8MN_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x0234 0x049C 0x0000 0x1 0x0
#define MX8MN_IOMUXC_UART1_RXD_GPIO5_IO22 0x0234 0x049C 0x0000 0x5 0x0
#define MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x0238 0x04A0 0x0000 0x0 0x0
#define MX8MN_IOMUXC_UART1_TXD_UART1_DTE_RX 0x0238 0x04A0 0x04F4 0x0 0x1
#define MX8MN_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x0238 0x04A0 0x0000 0x1 0x0
#define MX8MN_IOMUXC_UART1_TXD_GPIO5_IO23 0x0238 0x04A0 0x0000 0x5 0x0
#define MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x023C 0x04A4 0x04FC 0x0 0x0
#define MX8MN_IOMUXC_UART2_RXD_UART2_DTE_TX 0x023C 0x04A4 0x0000 0x0 0x0
#define MX8MN_IOMUXC_UART2_RXD_ECSPI3_MISO 0x023C 0x04A4 0x0000 0x1 0x0
#define MX8MN_IOMUXC_UART2_RXD_GPT1_COMPARE3 0x023C 0x04A4 0x0000 0x3 0x0
#define MX8MN_IOMUXC_UART2_RXD_GPIO5_IO24 0x023C 0x04A4 0x0000 0x5 0x0
#define MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x0240 0x04A8 0x0000 0x0 0x0
#define MX8MN_IOMUXC_UART2_TXD_UART2_DTE_RX 0x0240 0x04A8 0x04FC 0x0 0x1
#define MX8MN_IOMUXC_UART2_TXD_ECSPI3_SS0 0x0240 0x04A8 0x0000 0x1 0x0
#define MX8MN_IOMUXC_UART2_TXD_GPT1_COMPARE2 0x0240 0x04A8 0x0000 0x3 0x0
#define MX8MN_IOMUXC_UART2_TXD_GPIO5_IO25 0x0240 0x04A8 0x0000 0x5 0x0
#define MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x0244 0x04AC 0x0504 0x0 0x2
#define MX8MN_IOMUXC_UART3_RXD_UART3_DTE_TX 0x0244 0x04AC 0x0000 0x0 0x0
#define MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x0244 0x04AC 0x0000 0x1 0x0
#define MX8MN_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x0244 0x04AC 0x04F0 0x1 0x0
#define MX8MN_IOMUXC_UART3_RXD_USDHC3_RESET_B 0x0244 0x04AC 0x0000 0x2 0x0
#define MX8MN_IOMUXC_UART3_RXD_GPT1_CAPTURE2 0x0244 0x04AC 0x05EC 0x3 0x1
#define MX8MN_IOMUXC_UART3_RXD_GPIO5_IO26 0x0244 0x04AC 0x0000 0x5 0x0
#define MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x0248 0x04B0 0x0000 0x0 0x0
#define MX8MN_IOMUXC_UART3_TXD_UART3_DTE_RX 0x0248 0x04B0 0x0504 0x0 0x3
#define MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x0248 0x04B0 0x04F0 0x1 0x1
#define MX8MN_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x0248 0x04B0 0x0000 0x1 0x0
#define MX8MN_IOMUXC_UART3_TXD_USDHC3_VSELECT 0x0248 0x04B0 0x0000 0x2 0x0
#define MX8MN_IOMUXC_UART3_TXD_GPT1_CLK 0x0248 0x04B0 0x05E8 0x3 0x1
#define MX8MN_IOMUXC_UART3_TXD_GPIO5_IO27 0x0248 0x04B0 0x0000 0x5 0x0
#define MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x024C 0x04B4 0x050C 0x0 0x2
#define MX8MN_IOMUXC_UART4_RXD_UART4_DTE_TX 0x024C 0x04B4 0x0000 0x0 0x0
#define MX8MN_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x024C 0x04B4 0x0000 0x1 0x0
#define MX8MN_IOMUXC_UART4_RXD_UART2_DTE_RTS_B 0x024C 0x04B4 0x04F8 0x1 0x0
#define MX8MN_IOMUXC_UART4_RXD_GPT1_COMPARE1 0x024C 0x04B4 0x0000 0x3 0x0
#define MX8MN_IOMUXC_UART4_RXD_GPIO5_IO28 0x024C 0x04B4 0x0000 0x5 0x0
#define MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x0250 0x04B8 0x0000 0x0 0x0
#define MX8MN_IOMUXC_UART4_TXD_UART4_DTE_RX 0x0250 0x04B8 0x050C 0x0 0x3
#define MX8MN_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x0250 0x04B8 0x04F8 0x1 0x1
#define MX8MN_IOMUXC_UART4_TXD_UART2_DTE_CTS_B 0x0250 0x04B8 0x0000 0x1 0x0
#define MX8MN_IOMUXC_UART4_TXD_GPT1_CAPTURE1 0x0250 0x04B8 0x05F0 0x3 0x1
#define MX8MN_IOMUXC_UART4_TXD_GPIO5_IO29 0x0250 0x04B8 0x0000 0x5 0x0
#endif /* __DTS_IMX8MN_PINFUNC_H */
arch/arm/dts/imx8mn.dtsi 0 → 100644
View file @ 8e809399
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 NXP
*/
#include <dt-bindings/clock/imx8mn-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "imx8mn-pinfunc.h"
/ {
compatible = "fsl,imx8mn";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
ethernet0 = &fec1;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
i2c3 = &i2c4;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
mmc2 = &usdhc3;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
spi0 = &ecspi1;
spi1 = &ecspi2;
spi2 = &ecspi3;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
A53_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
clock-latency = <61036>;
clocks = <&clk IMX8MN_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
};
A53_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
clock-latency = <61036>;
clocks = <&clk IMX8MN_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
};
A53_2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
clock-latency = <61036>;
clocks = <&clk IMX8MN_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
};
A53_3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
clock-latency = <61036>;
clocks = <&clk IMX8MN_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
};
A53_L2: l2-cache0 {
compatible = "cache";
};
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
osc_32k: clock-osc-32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "osc_32k";
};
osc_24m: clock-osc-24m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "osc_24m";
};
clk_ext1: clock-ext1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <133000000>;
clock-output-names = "clk_ext1";
};
clk_ext2: clock-ext2 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <133000000>;
clock-output-names = "clk_ext2";
};
clk_ext3: clock-ext3 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <133000000>;
clock-output-names = "clk_ext3";
};
clk_ext4: clock-ext4 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency= <133000000>;
clock-output-names = "clk_ext4";
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <8000000>;
arm,no-tick-in-suspend;
};
soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x3e000000>;
aips1: bus@30000000 {
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x30000000 0x400000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio1: gpio@30200000 {
compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
reg = <0x30200000 0x10000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@30210000 {
compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
reg = <0x30210000 0x10000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@30220000 {
compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
reg = <0x30220000 0x10000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@30230000 {
compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
reg = <0x30230000 0x10000>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio5: gpio@30240000 {
compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
reg = <0x30240000 0x10000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
wdog1: watchdog@30280000 {
compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
reg = <0x30280000 0x10000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>;
status = "disabled";
};
wdog2: watchdog@30290000 {
compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
reg = <0x30290000 0x10000>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>;
status = "disabled";
};
wdog3: watchdog@302a0000 {
compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
reg = <0x302a0000 0x10000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>;
status = "disabled";
};
sdma3: dma-controller@302b0000 {
compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
reg = <0x302b0000 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
<&clk IMX8MN_CLK_SDMA3_ROOT>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
};
sdma2: dma-controller@302c0000 {
compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
reg = <0x302c0000 0x10000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
<&clk IMX8MN_CLK_SDMA2_ROOT>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
};
iomuxc: pinctrl@30330000 {
compatible = "fsl,imx8mn-iomuxc";
reg = <0x30330000 0x10000>;
};
gpr: iomuxc-gpr@30340000 {
compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
reg = <0x30340000 0x10000>;
};
ocotp: ocotp-ctrl@30350000 {
compatible = "fsl,imx8mn-ocotp", "fsl,imx7d-ocotp", "syscon";
reg = <0x30350000 0x10000>;
clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
};
anatop: anatop@30360000 {
compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
"syscon", "simple-bus";
reg = <0x30360000 0x10000>;
};
snvs: snvs@30370000 {
compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
reg = <0x30370000 0x10000>;
snvs_rtc: snvs-rtc-lp {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
regmap = <&snvs>;
offset = <0x34>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "snvs-rtc";
};
snvs_pwrkey: snvs-powerkey {
compatible = "fsl,sec-v4.0-pwrkey";
regmap = <&snvs>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
linux,keycode = <KEY_POWER>;
wakeup-source;
status = "disabled";
};
};
clk: clock-controller@30380000 {
compatible = "fsl,imx8mn-ccm";
reg = <0x30380000 0x10000>;
#clock-cells = <1>;
clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
<&clk_ext3>, <&clk_ext4>;
clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
"clk_ext3", "clk_ext4";
};
src: reset-controller@30390000 {
compatible = "fsl,imx8mn-src", "syscon";
reg = <0x30390000 0x10000>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
};
};
aips2: bus@30400000 {
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x30400000 0x400000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
pwm1: pwm@30660000 {
compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
reg = <0x30660000 0x10000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
<&clk IMX8MN_CLK_PWM1_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
status = "disabled";
};
pwm2: pwm@30670000 {
compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
reg = <0x30670000 0x10000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
<&clk IMX8MN_CLK_PWM2_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
status = "disabled";
};
pwm3: pwm@30680000 {
compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
reg = <0x30680000 0x10000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
<&clk IMX8MN_CLK_PWM3_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
status = "disabled";
};
pwm4: pwm@30690000 {
compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
reg = <0x30690000 0x10000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
<&clk IMX8MN_CLK_PWM4_ROOT>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
status = "disabled";
};
};
aips3: bus@30800000 {
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x30800000 0x400000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
ecspi1: spi@30820000 {
compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x30820000 0x10000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
<&clk IMX8MN_CLK_ECSPI1_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
ecspi2: spi@30830000 {
compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x30830000 0x10000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
<&clk IMX8MN_CLK_ECSPI2_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
ecspi3: spi@30840000 {
compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x30840000 0x10000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
<&clk IMX8MN_CLK_ECSPI3_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
uart1: serial@30860000 {
compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
reg = <0x30860000 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
<&clk IMX8MN_CLK_UART1_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
uart3: serial@30880000 {
compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
reg = <0x30880000 0x10000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
<&clk IMX8MN_CLK_UART3_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
uart2: serial@30890000 {
compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
reg = <0x30890000 0x10000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
<&clk IMX8MN_CLK_UART2_ROOT>;
clock-names = "ipg", "per";
status = "disabled";
};
i2c1: i2c@30a20000 {
compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x30a20000 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_I2C1_ROOT>;
status = "disabled";
};
i2c2: i2c@30a30000 {
compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x30a30000 0x10000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_I2C2_ROOT>;
status = "disabled";
};
i2c3: i2c@30a40000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
reg = <0x30a40000 0x10000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_I2C3_ROOT>;
status = "disabled";
};
i2c4: i2c@30a50000 {
compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x30a50000 0x10000>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_I2C4_ROOT>;
status = "disabled";
};
uart4: serial@30a60000 {
compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
reg = <0x30a60000 0x10000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_UART4_ROOT>,
<&clk IMX8MN_CLK_UART4_ROOT>;
clock-names = "ipg", "per";
dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
dma-names = "rx", "tx";
status = "disabled";
};
usdhc1: mmc@30b40000 {
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b40000 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_DUMMY>,
<&clk IMX8MN_CLK_NAND_USDHC_BUS>,
<&clk IMX8MN_CLK_USDHC1_ROOT>;
clock-names = "ipg", "ahb", "per";
assigned-clocks = <&clk IMX8MN_CLK_USDHC1>;
assigned-clock-rates = <400000000>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
bus-width = <4>;
status = "disabled";
};
usdhc2: mmc@30b50000 {
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b50000 0x10000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_DUMMY>,
<&clk IMX8MN_CLK_NAND_USDHC_BUS>,
<&clk IMX8MN_CLK_USDHC2_ROOT>;
clock-names = "ipg", "ahb", "per";
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
bus-width = <4>;
status = "disabled";
};
usdhc3: mmc@30b60000 {
compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
reg = <0x30b60000 0x10000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_DUMMY>,
<&clk IMX8MN_CLK_NAND_USDHC_BUS>,
<&clk IMX8MN_CLK_USDHC3_ROOT>;
clock-names = "ipg", "ahb", "per";
assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
assigned-clock-rates = <400000000>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
bus-width = <4>;
status = "disabled";
};
sdma1: dma-controller@30bd0000 {
compatible = "fsl,imx8mn-sdma", "fsl,imx7d-sdma";
reg = <0x30bd0000 0x10000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
<&clk IMX8MN_CLK_SDMA1_ROOT>;
clock-names = "ipg", "ahb";
#dma-cells = <3>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
};
fec1: ethernet@30be0000 {
compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec";
reg = <0x30be0000 0x10000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
<&clk IMX8MN_CLK_ENET1_ROOT>,
<&clk IMX8MN_CLK_ENET_TIMER>,
<&clk IMX8MN_CLK_ENET_REF>,
<&clk IMX8MN_CLK_ENET_PHY_REF>;
clock-names = "ipg", "ahb", "ptp",
"enet_clk_ref", "enet_out";
assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
<&clk IMX8MN_CLK_ENET_TIMER>,
<&clk IMX8MN_CLK_ENET_REF>,
<&clk IMX8MN_CLK_ENET_TIMER>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
<&clk IMX8MN_SYS_PLL2_100M>,
<&clk IMX8MN_SYS_PLL2_125M>;
assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
fsl,num-tx-queues = <3>;
fsl,num-rx-queues = <3>;
status = "disabled";
};
};
aips4: bus@32c00000 {
compatible = "fsl,aips-bus", "simple-bus";
reg = <0x32c00000 0x400000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
usbotg1: usb@32e40000 {
compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
reg = <0x32e40000 0x200>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
clock-names = "usb1_ctrl_root_clk";
assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>,
<&clk IMX8MN_CLK_USB_CORE_REF>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>,
<&clk IMX8MN_SYS_PLL1_100M>;
fsl,usbphy = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
status = "disabled";
};
usbmisc1: usbmisc@32e40200 {
compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
#index-cells = <1>;
reg = <0x32e40200 0x200>;
};
usbotg2: usb@32e50000 {
compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
reg = <0x32e50000 0x200>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
clock-names = "usb1_ctrl_root_clk";
assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>,
<&clk IMX8MN_CLK_USB_CORE_REF>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>,
<&clk IMX8MN_SYS_PLL1_100M>;
fsl,usbphy = <&usbphynop2>;
fsl,usbmisc = <&usbmisc2 0>;
status = "disabled";
};
usbmisc2: usbmisc@32e50200 {
compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
#index-cells = <1>;
reg = <0x32e50200 0x200>;
};
};
dma_apbh: dma-controller@33000000 {
compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
reg = <0x33000000 0x2000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
#dma-cells = <1>;
dma-channels = <4>;
clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
};
gpmi: nand-controller@33002000 {
compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
reg-names = "gpmi-nand", "bch";
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "bch";
clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
<&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
clock-names = "gpmi_io", "gpmi_bch_apb";
dmas = <&dma_apbh 0>;
dma-names = "rx-tx";
status = "disabled";
};
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";
reg = <0x38800000 0x10000>,
<0x38880000 0xc0000>;
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
};
usbphynop1: usbphynop1 {
compatible = "usb-nop-xceiv";
clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
clock-names = "main_clk";
};
usbphynop2: usbphynop2 {
compatible = "usb-nop-xceiv";
clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
clock-names = "main_clk";
};
};
arch/arm/dts/imx8mq-bio.dts 0 → 100644
View file @ 8e809399
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2018 Boundary Devices
*/
/dts-v1/;
/* First 128KB is for PSCI ATF. */
/memreserve/ 0x40000000 0x00020000;
#include "fsl-imx8mq.dtsi"
#if 0
#define MIPI_ON_DCSS
#endif
#if 0
#define RM68200
#endif
#if 1
#define HDMI_STATUS "okay"
#else
#define HDMI_STATUS "disabled"
#endif
#if 0
#define MIPI_DSI_STATUS "okay"
#else
#define MIPI_DSI_STATUS "disabled"
#endif
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
iomuxc_pinctrl: iomuxc-pinctrlgrp {
};
};
&iomuxc_pinctrl {
pinctrl_backlight: backlightgrp {
fsl,pins = <
#define GPIRQ_BKLIT_ERR <&gpio4 19 IRQ_TYPE_LEVEL_HIGH>
MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19
>;
};
pinctrl_bt_rfkill: bt-rfkillgrp {
fsl,pins = <
#define GP_BT_RFKILL_RESET <&gpio3 19 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19
>;
};
pinctrl_gpio_keys: gpio_keysgrp {
fsl,pins = <
#define GP_GPIOKEY_POWER <&gpio1 7 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 /* sw3 */
/* J1 connector */
#define GP_GPIOKEY_J1_P2 <&gpio4 1 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 /* Pin 2 */
#define GP_GPIOKEY_J1_P3 <&gpio5 5 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 /* Pin 3 */
#define GP_GPIOKEY_J1_P4 <&gpio4 3 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x19 /* Pin 4 */
#define GP_GPIOKEY_J1_P5 <&gpio4 4 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* Pin 5 */
#define GP_GPIOKEY_J1_P6 <&gpio4 5 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* Pin 6 */
#define GP_GPIOKEY_J1_P7 <&gpio4 6 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* Pin 7 */
#define GP_GPIOKEY_J1_P8 <&gpio4 7 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19 /* Pin 8 */
#define GP_GPIOKEY_J1_P9 <&gpio4 8 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19 /* Pin 9 */
/* J17 connector */
#define GP_GPIOKEY_J17_P2 <&gpio4 0 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* Pin 2 */
#define GP_GPIOKEY_J17_P3 <&gpio1 3 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* Pin 3 */
#define GP_GPIOKEY_J17_P4 <&gpio1 10 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* Pin 4 */
#define GP_GPIOKEY_J17_P5 <&gpio5 10 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x19 /* Pin 5 */
#define GP_GPIOKEY_J17_P6 <&gpio1 1 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 /* pin 6 */
/* J21 connector */
#define GP_GPIOKEY_J21_P2 <&gpio3 4 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* Pin 2 */
#define GP_GPIOKEY_J21_P3 <&gpio3 15 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19 /* Pin 3 */
#define GP_GPIOKEY_J21_P4 <&gpio3 11 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* Pin 4 */
#define GP_GPIOKEY_J21_P5 <&gpio3 10 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* Pin 5 */
#define GP_GPIOKEY_J21_P6 <&gpio3 9 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* Pin 6 */
#define GP_GPIOKEY_J21_P7 <&gpio3 8 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 /* Pin 7 */
#define GP_GPIOKEY_J21_P8 <&gpio3 7 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 /* Pin 8 */
#define GP_GPIOKEY_J21_P9 <&gpio3 6 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19 /* Pin 9 */
#define GP_GPIOKEY_J21_P10 <&gpio1 5 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* Pin 10 */
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
/* J19 Pin 2, WL_WAKE */
MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0xd6
/* J19 Pin 4, WL_IRQ, not needed for Silex */
MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0xd6
/* J19 Pin 41, BT_CLK_REQ */
MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0xd6
/* J19 Pin 42, BT_HOST_WAKE */
MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0xd6
/* test points */
MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* TP29 */
MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 /* TP30 */
MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 /* TP31 */
MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x19 /* TP32 */
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
>;
};
pinctrl_i2c2_csi1: i2c2-csi1grp {
fsl,pins = <
#define GP_CSI1_MIPI_PWDN <&gpio4 25 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25 0x61
#define GP_CSI1_MIPI_RESET <&gpio4 24 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x61
/* Clock for CSI1 */
MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x59
>;
};
pinctrl_i2c2_sn65dsi83: i2c2-sn65dsi83 {
fsl,pins = <
#define GPIRQ_I2C2_SN65DSI83 <&gpio4 28 IRQ_TYPE_LEVEL_LOW>
MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x16
#define GP_I2C2_SN65DSI83_EN <&gpio3 14 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x26
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
>;
};
pinctrl_i2c3_rv4162: i2c3-rv4162grp {
fsl,pins = <
#define GPIRQ_RV4162 <&gpio1 6 IRQ_TYPE_LEVEL_LOW>
MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x49
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
>;
};
pinctrl_i2c4_gt911: i2c4-gt911grp {
fsl,pins = <
#define GPIRQ_GT911 <&gpio3 12 IRQ_TYPE_LEVEL_HIGH>
#define GP_GT911_IRQ <&gpio3 12 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0xd6
/* driver writes levels, instead of active/inactive */
#define GP_GT911_RESET <&gpio3 13 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x49
>;
};
pinctrl_i2c4_ft5x06: i2c4-ft5x06grp {
fsl,pins = <
#define GPIRQ_I2C4_FT5X06 <&gpio3 12 IRQ_TYPE_EDGE_FALLING>
#define GP_I2C4_FT5X06_WAKE <&gpio3 12 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x49
#define GP_I2C4_FT5X06_RESET <&gpio3 13 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x49
>;
};
pinctrl_i2c4_st1633: i2c4-st1633grp {
fsl,pins = <
#define GPIRQ_ST1633 <&gpio3 12 IRQ_TYPE_EDGE_FALLING>
#define GP_ST1633_IRQ <&gpio3 12 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0xd6
#define GP_ST1633_RESET <&gpio3 13 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x49
>;
};
pinctrl_mipi_com50h5n03ulc: mipi-com50h5n03ulcgrp {
fsl,pins = <
#define GP_MIPI_RESET <&gpio3 14 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x16
>;
};
pinctrl_mipi_ltk0680ytmdb: mipi-ltk0680ytmdbgrp {
fsl,pins = <
#define GP_MIPI_RESET <&gpio3 14 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x16
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x16
>;
};
pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp {
fsl,pins = <
#define GP_REG_USB_OTG_VBUS <&gpio1 12 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x16
>;
};
pinctrl_reg_wlan_vmmc: reg-wlan-vmmcgrp {
fsl,pins = <
#define GP_REG_WLAN_VMMC <&gpio3 20 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x16
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
/* wm8960 */
MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6
MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6
MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
/* Bluetooth PCM */
MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
>;
};
pinctrl_sound_wm8960: souncd-wm8960grp {
fsl,pins = <
#define GPIRQ_MIC_DET <&gpio5 12 IRQ_TYPE_LEVEL_HIGH>
MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x01
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x45
MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x45
MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x45
MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x45
>;
};
pinctrl_usb3_0: usb3-0grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x16
>;
};
pinctrl_usb3_1: usb3-1grp {
fsl,pins = <
#define GP_USB3_1_HUB_RESET <&gpio1 14 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
#define GP_USB3_1_DN3_SD_RESET <&gpio3 17 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x61
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
#if 0
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
#else
#define GP_EMMC_RESET <&gpio2 10 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
#endif
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
/* Bluetooth slow clock */
MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x03
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 /* J19 pin 9 */
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};
/ {
model = "Boundary Devices i.MX8MQ BIO";
compatible = "boundary,imx8mq-bio", "fsl,imx8mq";
chosen {
bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
#if 0
stdout-path = &uart1;
#endif
};
#if 0
backlight_mipi: backlight-mipi {
brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>;
compatible = "pwm-backlight";
default-brightness-level = <8>;
display = <&lcdif>;
pwms = <&pwm3 0 30000>; /* 33.3 Khz */
status = "disabled";
};
#endif
bt-rfkill {
compatible = "net,rfkill-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_bt_rfkill>;
name = "bt-rfkill";
type = <2>; /* Bluetooth */
reset-gpios = GP_BT_RFKILL_RESET;
status = "okay";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
power {
label = "Power Button";
gpios = GP_GPIOKEY_POWER;
linux,code = <KEY_POWER>;
gpio-key,wakeup;
};
j1-p2 {
label = "j1-p2";
gpios = GP_GPIOKEY_J1_P2;
linux,code = <KEY_2>;
};
j1-p3 {
label = "j1-p3";
gpios = GP_GPIOKEY_J1_P3;
linux,code = <KEY_3>;
};
j1-p4 {
label = "j1-p4";
gpios = GP_GPIOKEY_J1_P4;
linux,code = <KEY_4>;
};
j1-p5 {
label = "j1-p5";
gpios = GP_GPIOKEY_J1_P5;
linux,code = <KEY_5>;
};
j1-p6 {
label = "j1-p6";
gpios = GP_GPIOKEY_J1_P6;
linux,code = <KEY_6>;
};
j1-p7 {
label = "j1-p7";
gpios = GP_GPIOKEY_J1_P7;
linux,code = <KEY_7>;
};
j1-p8 {
label = "j1-p8";
gpios = GP_GPIOKEY_J1_P8;
linux,code = <KEY_8>;
};
j1-p9 {
label = "j1-p9";
gpios = GP_GPIOKEY_J1_P9;
linux,code = <KEY_9>;
};
j17-p2 {
label = "j17-p2";
gpios = GP_GPIOKEY_J17_P2;
linux,code = <KEY_F2>;
};
j17-p3 {
label = "j17-p3";
gpios = GP_GPIOKEY_J17_P3;
linux,code = <KEY_F3>;
};
j17-p4 {
label = "j17-p4";
gpios = GP_GPIOKEY_J17_P4;
linux,code = <KEY_F4>;
};
j17-p5 {
label = "j17-p5";
gpios = GP_GPIOKEY_J17_P5;
linux,code = <KEY_F5>;
};
j17-p6 {
label = "j17-p6";
gpios = GP_GPIOKEY_J17_P6;
linux,code = <KEY_F6>;
};
j21-p2 {
label = "j21-p2";
gpios = GP_GPIOKEY_J21_P2;
linux,code = <KEY_B>;
};
j21-p3 {
label = "j21-p3";
gpios = GP_GPIOKEY_J21_P3;
linux,code = <KEY_C>;
};
j21-p4 {
label = "j21-p4";
gpios = GP_GPIOKEY_J21_P4;
linux,code = <KEY_D>;
};
j21-p5 {
label = "j21-p5";
gpios = GP_GPIOKEY_J21_P5;
linux,code = <KEY_E>;
};
j21-p6 {
label = "j21-p6";
gpios = GP_GPIOKEY_J21_P6;
linux,code = <KEY_F>;
};
j21-p7 {
label = "j21-p7";
gpios = GP_GPIOKEY_J21_P7;
linux,code = <KEY_G>;
};
j21-p8 {
label = "j21-p8";
gpios = GP_GPIOKEY_J21_P8;
linux,code = <KEY_H>;
};
j21-p9 {
label = "j21-p9";
gpios = GP_GPIOKEY_J21_P9;
linux,code = <KEY_I>;
};
j21-p10 {
label = "j21-p10";
gpios = GP_GPIOKEY_J21_P10;
linux,code = <KEY_J>;
};
};
mipi_mclk: mipi-mclk {
compatible = "pwm-clock";
#clock-cells = <0>;
clock-frequency = <22000000>;
clock-output-names = "mipi_mclk";
#if 0
pwms = <&pwm1 0 45>; /* 1 / 45 ns = 22 MHz */
#endif
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usbotg_vbus>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = GP_REG_USB_OTG_VBUS;
enable-active-high;
};
reg_vref_0v9: regulator-vref-0v9 {
compatible = "regulator-fixed";
regulator-name = "vref-0v9";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
};
reg_vref_1v8: regulator-vref-1v8 {
compatible = "regulator-fixed";
regulator-name = "vref-1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_vref_2v5: regulator-vref-2v5 {
compatible = "regulator-fixed";
regulator-name = "vref-2v5";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
};
reg_vref_3v3: regulator-vref-3v3 {
compatible = "regulator-fixed";
regulator-name = "vref-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_vref_5v: regulator-vref-5v {
compatible = "regulator-fixed";
regulator-name = "vref-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_wlan_vmmc: regulator-wlan-vmmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_wlan_vmmc>;
regulator-name = "reg_wlan_vmmc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = GP_REG_WLAN_VMMC;
startup-delay-us = <70000>;
enable-active-high;
};
#if 0
sound-wm8960 {
compatible = "fsl,imx-audio-wm8960";
model = "wm8960-audio";
cpu-dai = <&sai1>;
codec-master;
audio-codec = <&wm8960>;
audio-routing =
"Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"Ext Spk", "SPK_LP",
"Ext Spk", "SPK_LN",
"Ext Spk", "SPK_RP",
"Ext Spk", "SPK_RN",
"LINPUT1", "Main MIC",
"Main MIC", "MICB";
/* JD2: hp detect high for headphone*/
hp-det = <2 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sound_wm8960>;
};
sound_hdmi: sound-hdmi {
compatible = "fsl,imx-audio-cdnhdmi";
model = "imx-audio-hdmi";
audio-cpu = <&sai4>;
constraint-rate = <32000 44100 48000 96000 192000>;
protocol = <1>;
status = HDMI_STATUS;
};
#endif
};
&A53_0 {
operating-points = <
/* kHz uV */
1500000 1000000
1300000 1000000
1000000 900000
800000 900000
>;
};
&clk {
assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>;
assigned-clock-rates = <786432000>, <722534400>;
};
#if 0
&csi1_bridge {
fsl,mipi-mode;
fsl,two-8bit-sensor-mode;
status = "okay";
port {
csi1_ep: endpoint {
remote-endpoint = <&csi1_mipi_ep>;
};
};
};
&dcss {
#ifdef MIPI_ON_DCSS
status = MIPI_DSI_STATUS;
disp-dev = "mipi_disp";
clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
<&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
<&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
<&clk IMX8MQ_CLK_DC_PIXEL_DIV>,
<&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_DISP_DTRC_DIV>;
clock-names = "apb", "axi", "rtrm", "pix_div", "pix_out", "dtrc";
assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL_SRC>,
<&clk IMX8MQ_CLK_DISP_AXI_SRC>,
<&clk IMX8MQ_CLK_DISP_RTRM_SRC>,
<&clk IMX8MQ_CLK_DISP_RTRM_PRE_DIV>,
<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
<&clk IMX8MQ_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
<&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_VIDEO_PLL1_OUT>,
<&clk IMX8MQ_CLK_25M>;
assigned-clock-rates = <600000000>,
<800000000>,
<400000000>,
<400000000>,
<0>,
<599999999>;
dcss_disp0: port@0 {
reg = <0>;
dcss_disp0_mipi_dsi: mipi_dsi {
remote-endpoint = <&mipi_dsi_in>;
};
};
#else
status = HDMI_STATUS;
disp-dev = "hdmi_disp";
#endif
};
#endif
#if 0
&gpu {
status = "okay";
};
&hdmi {
assigned-clocks = <&clk IMX8MQ_CLK_CLK2>;
assigned-clock-parents = <&clk IMX8MQ_CLK_27M>;
clocks = <&clk IMX8MQ_CLK_CLK2_CG>;
clock-names = "refclk";
status = HDMI_STATUS;
};
&hdmi_cec {
status = HDMI_STATUS;
};
#endif
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
#if 0
mipi_to_lvds: mipi-to-lvds@2c {
clocks = <&mipi_dsi_phy 0>;
clock-names = "mipi_clk";
compatible = "ti,sn65dsi83";
display = <&lcdif>;
display-dsi = <&fb_mipi>;
enable-gpios = GP_I2C2_SN65DSI83_EN;
interrupts-extended = GPIRQ_I2C2_SN65DSI83;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_sn65dsi83>;
reg = <0x2c>;
status = "disabled";
};
#endif
#if 0
ov5640-mipi1@3c {
compatible = "ov5640_mipisubdev";
reg = <0x3c>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_csi1>;
clocks = <&clk IMX8MQ_CLK_CLKO2>;
clock-names = "csi_mclk";
assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>;
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>;
assigned-clock-rates = <25000000>;
csi_id = <0>;
AVDD-supply = <&reg_vref_2v5>;
DVDD-supply = <&reg_vref_3v3>;
DOVDD-supply = <&reg_vref_1v8>;
pwn-gpios = GP_CSI1_MIPI_PWDN;
rst-gpios = GP_CSI1_MIPI_RESET;
mclk = <25000000>;
mipi_csi;
port {
ov5640_mipi1_ep: endpoint {
remote-endpoint = <&mipi1_sensor_ep>;
};
};
};
#endif
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
rtc@68 {
compatible = "microcrystal,rv4162";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_rv4162>;
reg = <0x68>;
interrupts-extended = GPIRQ_RV4162;
wakeup-source;
};
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
i2cmux@70 {
compatible = "pca9540";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c4a: i2c4@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c4b: i2c4@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
};
touchscreen@14 {
compatible = "goodix,gt9271";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4_gt911>;
reg = <0x14>;
esd-recovery-timeout-ms = <2000>;
interrupts-extended = GPIRQ_GT911;
irq-gpios = GP_GT911_IRQ;
reset-gpios = GP_GT911_RESET;
};
wm8960: codec@1a {
compatible = "wlf,wm8960";
reg = <0x1a>;
clocks = <&clk IMX8MQ_CLK_SAI1_ROOT>;
clock-names = "mclk";
wlf,shared-lrclk;
};
touchscreen@38 {
compatible = "ft5x06-ts";
interrupts-extended = GPIRQ_I2C4_FT5X06;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4_ft5x06>;
reg = <0x38>;
wakeup-gpios = GP_I2C4_FT5X06_WAKE;
reset-gpios = GP_I2C4_FT5X06_RESET;
};
touchscreen@55 {
compatible = "sitronix,st1633i";
reg = <0x55>;
interrupts-extended = GPIRQ_ST1633;
/* pins used by touchscreen */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4_st1633>;
reset-gpios = GP_ST1633_RESET;
wakeup-gpios = GP_ST1633_IRQ;
};
};
&lcdif {
#if 0
#ifndef MIPI_ON_DCSS
status = "okay";
assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_SRC>,
<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
<&clk IMX8MQ_CLK_25M>;
max-res = <1920>, <1920>;
port@0 {
lcdif_mipi_dsi: mipi-dsi-endpoint {
remote-endpoint = <&mipi_dsi_in>;
};
};
#endif
#endif
};
#if 0
&mipi_csi_1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port {
mipi1_sensor_ep: endpoint1 {
remote-endpoint = <&ov5640_mipi1_ep>;
data-lanes = <1 2>;
};
csi1_mipi_ep: endpoint2 {
remote-endpoint = <&csi1_ep>;
};
};
};
&mipi_dsi_phy {
status = MIPI_DSI_STATUS;
};
&mipi_dsi {
/delete-property/ no_clk_reset;
status = MIPI_DSI_STATUS;
#ifndef MIPI_ON_DCSS
as_bridge;
#endif
assigned-clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
<&clk IMX8MQ_CLK_DSI_PHY_REF>,
<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
<&clk IMX8MQ_VIDEO_PLL1_OUT>,
<&clk IMX8MQ_CLK_25M>;
assigned-clock-rates = <266000000>;
port@1 {
mipi_dsi_in: endpoint {
#ifdef MIPI_ON_DCSS
remote-endpoint = <&dcss_disp0_mipi_dsi>;
#else
remote-endpoint = <&lcdif_mipi_dsi>;
#endif
};
};
};
&mipi_dsi_bridge {
/delete-property/ no_clk_reset;
status = MIPI_DSI_STATUS;
fb_mipi: panel@0 {
bits-per-color = <8>;
bridge-de-active = <0>;
#if 0
bridge-sync-active = <1>;
#endif
bus-format = "rgb888";
compatible = "panel,simple";
delay-power-up = <2>;
dsi-format = "rgb888";
dsi-lanes = <4>;
mode-skip-eot;
mode-video;
mode-video-burst;
panel-height-mm = <136>;
panel-width-mm = <217>;
power-supply = <&reg_vref_5v>;
reg = <0>;
spwg;
display-timings {
t_mipi: t-dsi-default {
/* m101nwwb by default */
clock-frequency = <70000000>;
hactive = <1280>;
vactive = <800>;
hback-porch = <5>;
hfront-porch = <123>;
vback-porch = <3>;
vfront-porch = <24>;
hsync-len = <1>;
vsync-len = <1>;
hsync-active = <1>;
vsync-active = <1>;
de-active = <1>;
};
};
port {
panel1_in: endpoint {
remote-endpoint = <&mipi_dsi_bridge_out>;
};
};
};
port@1 {
mipi_dsi_bridge_out: endpoint {
remote-endpoint = <&panel1_in>;
};
};
};
#endif
#if 0
&mu {
status = "okay";
};
#endif
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
#if 0
&resmem {
limit3g@0x100000000 {
no-map;
reg = <1 0x00000000 0 0x40000000>;
};
};
&sai1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
assigned-clocks = <&clk IMX8MQ_CLK_SAI1>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <12288000>;
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
status = "okay";
};
&sai4 {
assigned-clocks = <&clk IMX8MQ_CLK_SAI4>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_SAI4_ROOT>, <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>,
<&clk IMX8MQ_AUDIO_PLL2_OUT>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
status = "okay";
};
#endif
#if 0
&uart1 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
assigned-clocks = <&clk IMX8MQ_CLK_UART2_SRC>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
uart-has-rtscts;
status = "okay";
};
#endif
&usb3_phy0 {
status = "okay";
};
&usb3_0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb3_0>;
status = "okay";
};
&usb_dwc3_0 {
#if 0
status = "okay";
#endif
dr_mode = "otg";
vbus-supply = <&reg_usb_otg_vbus>;
};
&usb3_phy1 {
status = "okay";
};
&usb3_1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb3_1>;
reset-gpios = GP_USB3_1_HUB_RESET, GP_USB3_1_DN3_SD_RESET;
status = "okay";
};
&usb_dwc3_1 {
#if 0
status = "okay";
#endif
dr_mode = "host";
};
&usdhc1 {
cap-mmc-highspeed;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
no-mmc-hs400;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
reset-gpios = GP_EMMC_RESET;
non-removable;
vqmmc-1-8-v;
vmmc-supply = <&reg_vref_1v8>;
status = "okay";
};
#if 0
&usdhc2 {
bus-width = <4>;
no-sd-uhs-sdr104;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
non-removable;
status = "okay";
vmmc-supply = <&reg_wlan_vmmc>;
vqmmc-1-8-v;
};
&vpu {
regulator-supply = <&reg_vref_0v9>;
status = "okay";
};
#endif
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
status = "okay";
};
arch/arm/dts/imx8mq-nitrogen8m.dts 0 → 100644
View file @ 8e809399
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2018 Boundary Devices
*/
/dts-v1/;
/* First 128KB is for PSCI ATF. */
/memreserve/ 0x40000000 0x00020000;
#include "fsl-imx8mq.dtsi"
#if 0
#define MIPI_ON_DCSS
#endif
#if 0
#define RM68200
#endif
#if 1
#define HDMI_STATUS "okay"
#else
#define HDMI_STATUS "disabled"
#endif
#if 0
#define MIPI_DSI_STATUS "okay"
#else
#define MIPI_DSI_STATUS "disabled"
#endif
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
iomuxc_pinctrl: iomuxc-pinctrlgrp {
};
};
&iomuxc_pinctrl {
pinctrl_bt_rfkill: bt-rfkillgrp {
fsl,pins = <
#define GP_BT_RFKILL_RESET <&gpio3 19 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
/* J17 */
#define GP_ECSPI2_CS0 <&gpio5 13 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 /* Pin 1 */
MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x19 /* Pin 3 */
MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x19 /* Pin 5 */
MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x19 /* Pin 7 */
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
#define GP_FEC1_RESET <&gpio1 9 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
#define GPIRQ_FEC1_PHY <&gpio1 11 IRQ_TYPE_LEVEL_LOW>
MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59
>;
};
pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
#define GP_GPIOKEY_POWER <&gpio1 7 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
/* J17 connector, odd */
MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* Pin 19 */
MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 /* Pin 21 */
MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x19 /* Pin 23 */
MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* Pin 25 */
MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* Pin 27 */
MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* Pin 29 */
MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19 /* Pin 31 */
MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19 /* Pin 33 */
MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19 /* Pin 35 */
MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x19 /* Pin 39 */
MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 /* Pin 41 */
MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* Pin 43 */
MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 /* Pin 45 */
MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 /* Pin 47 */
MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* Pin 49 */
MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* Pin 51 */
/* J17 connector, even */
MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 /* Pin 44 */
MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 /* Pin 48 */
MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* Pin 50 */
MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* Pin 54 */
MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* Pin 56 */
/* J18 connector, odd */
MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* Pin 41 */
MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* Pin 43 */
MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* Pin 45 */
MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* Pin 47 */
MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* Pin 49 */
MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* Pin 53 */
/* J18 connector, even */
MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 /* Pin 32 */
MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x19 /* Pin 36 */
MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19 /* Pin 38 */
MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 /* Pin 40 */
MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 /* Pin 42 */
MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* Pin 44 */
MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* Pin 46 */
/* J13 Pin 2, WL_WAKE */
MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0xd6
/* J13 Pin 4, WL_IRQ, not needed for Silex */
MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0xd6
/* J13 pin 9, unused */
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
/* J13 Pin 41, BT_CLK_REQ */
MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0xd6
/* J13 Pin 42, BT_HOST_WAKE */
MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0xd6
/* Clock for both CSI1 and CSI2 */
MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x07
/* test points */
MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc1 /* TP87 */
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_i2c1_pca9546: i2c1-pca9546grp {
fsl,pins = <
#define GP_I2C1_PCA9546_RESET <&gpio1 8 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49
>;
};
pinctrl_i2c1d_rv4162: i2c1d-rv4162grp {
fsl,pins = <
#define GPIRQ_RV4162 <&gpio1 6 IRQ_TYPE_LEVEL_LOW>
MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x49
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
>;
};
pinctrl_i2c2_csi1: i2c2-csi1grp {
fsl,pins = <
#define GP_CSI1_MIPI_PWDN <&gpio3 3 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x61
#define GP_CSI1_MIPI_RESET <&gpio3 17 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x61
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
>;
};
pinctrl_i2c3_csi2: i2c3-csi2grp {
fsl,pins = <
#define GP_CSI2_MIPI_PWDN <&gpio3 2 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x61
#define GP_CSI2_MIPI_RESET <&gpio2 19 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x61
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
>;
};
pinctrl_i2c4_ft5x06: i2c4-ft5x06grp {
fsl,pins = <
#define GPIRQ_I2C4_FT5X06 <&gpio3 12 IRQ_TYPE_EDGE_FALLING>
#define GP_I2C4_FT5X06_WAKE <&gpio3 12 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x49
#define GP_I2C4_FT5X06_RESET <&gpio3 13 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x49
>;
};
pinctrl_i2c4_gt911: i2c4-gt911grp {
fsl,pins = <
#define GPIRQ_GT911 <&gpio3 12 IRQ_TYPE_LEVEL_HIGH>
#define GP_GT911_IRQ <&gpio3 12 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0xd6
/* driver writes levels, instead of active/inactive */
#define GP_GT911_RESET <&gpio3 13 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x49
>;
};
pinctrl_i2c4_sn65dsi83: i2c4-sn65dsi83grp {
fsl,pins = <
#define GPIRQ_I2C4_SN65DSI83 <&gpio1 1 IRQ_TYPE_LEVEL_HIGH>
MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x04
#define GP_I2C4_SN65DSI83_EN <&gpio3 15 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x06
>;
};
pinctrl_i2c4_st1633: i2c4-st1633grp {
fsl,pins = <
#define GPIRQ_ST1633 <&gpio3 12 IRQ_TYPE_EDGE_FALLING>
#define GP_ST1633_IRQ <&gpio3 12 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0xd6
#define GP_ST1633_RESET <&gpio3 13 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x49
>;
};
pinctrl_mipi_com50h5n03ulc: mipi-com50h5n03ulcgrp {
fsl,pins = <
#define GP_MIPI_RESET <&gpio3 15 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16
>;
};
pinctrl_mipi_lcm_jm430: mipi-lcm-jm430grp {
fsl,pins = <
#define GP_TC358762_EN <&gpio3 15 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16
>;
};
pinctrl_mipi_ltk0680ytmdb: mipi-ltk0680ytmdbgrp {
fsl,pins = <
#define GP_MIPI_RESET <&gpio3 15 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16
>;
};
pinctrl_mipi_ltk080a60a004t: mipi-ltk080a60a004tgrp {
fsl,pins = <
#define GP_LTK08_MIPI_EN <&gpio1 1 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
#define GP_PCIE0_RESET <&gpio5 7 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x16
#define GP_PCIE0_DISABLE <&gpio5 6 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x16
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x16
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x16
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x16
>;
};
pinctrl_reg_arm_dram: reg-arm-dram {
fsl,pins = <
#define GP_ARM_DRAM_VSEL <&gpio3 24 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16
>;
};
pinctrl_reg_dram_1p1v: reg-dram-1p1v {
fsl,pins = <
#define GP_DRAM_1P1_VSEL <&gpio2 11 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x16
>;
};
pinctrl_reg_soc_gpu_vpu: reg-soc-gpu-vpu {
fsl,pins = <
#define GP_SOC_GPU_VPU_VSEL <&gpio2 20 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x16
>;
};
pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp {
fsl,pins = <
#define GP_REG_USB_OTG_VBUS <&gpio1 12 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x16
>;
};
pinctrl_reg_wlan_vmmc: reg-wlan-vmmcgrp {
fsl,pins = <
#define GP_REG_WLAN_VMMC <&gpio3 20 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x16
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
/* wm8960 */
MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6
MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6
MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
/* J17 */
MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 /* Pin 22 */
MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0xd6 /* Pin 24 */
MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 /* Pin 26 */
MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 /* Pin 28 */
MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0xd6 /* Pin 30 */
MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 /* Pin 32 */
MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 /* Pin 34 */
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
/* Bluetooth PCM */
MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x45
MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x45
MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x45
MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x45
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x45
MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x45
>;
};
pinctrl_usb3_0: usb3-0grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x16
>;
};
pinctrl_usb3_1: usb3-1grp {
fsl,pins = <
#define GP_USB3_1_HUB_RESET <&gpio1 14 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
#if 0
MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
#else
#define GP_EMMC_RESET <&gpio2 10 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
#endif
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
/* Bluetooth slow clock */
MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x03
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};
/ {
model = "Boundary Devices i.MX8MQ Nitrogen8M";
compatible = "boundary,imx8mq-nitrogen8m", "fsl,imx8mq";
chosen {
bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
#if 0
stdout-path = &uart1;
#endif
};
#if 0
backlight_mipi: backlight-mipi {
brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>;
compatible = "pwm-backlight";
default-brightness-level = <8>;
display = <&lcdif>;
pwms = <&pwm3 0 30000>; /* 33.3 Khz */
status = "disabled";
};
#endif
bt-rfkill {
compatible = "net,rfkill-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_bt_rfkill>;
name = "bt-rfkill";
type = <2>; /* Bluetooth */
reset-gpios = GP_BT_RFKILL_RESET;
status = "okay";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
power {
label = "Power Button";
gpios = GP_GPIOKEY_POWER;
linux,code = <KEY_POWER>;
gpio-key,wakeup;
};
};
mipi_mclk: mipi-mclk {
compatible = "pwm-clock";
#clock-cells = <0>;
clock-frequency = <22000000>;
clock-output-names = "mipi_mclk";
#if 0
pwms = <&pwm1 0 45>; /* 1 / 45 ns = 22 MHz */
#endif
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usbotg_vbus>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = GP_REG_USB_OTG_VBUS;
enable-active-high;
};
reg_vref_0v9: regulator-vref-0v9 {
compatible = "regulator-fixed";
regulator-name = "vref-0v9";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
};
reg_vref_1v8: regulator-vref-1v8 {
compatible = "regulator-fixed";
regulator-name = "vref-1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_vref_2v5: regulator-vref-2v5 {
compatible = "regulator-fixed";
regulator-name = "vref-2v5";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
};
reg_vref_3v3: regulator-vref-3v3 {
compatible = "regulator-fixed";
regulator-name = "vref-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_vref_5v: regulator-vref-5v {
compatible = "regulator-fixed";
regulator-name = "vref-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_wlan_vmmc: regulator-wlan-vmmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_wlan_vmmc>;
regulator-name = "reg_wlan_vmmc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = GP_REG_WLAN_VMMC;
startup-delay-us = <70000>;
enable-active-high;
};
#if 0
sound-wm8960 {
compatible = "fsl,imx-audio-wm8960";
model = "wm8960-audio";
cpu-dai = <&sai1>;
codec-master;
audio-codec = <&wm8960>;
audio-routing =
"Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"Ext Spk", "SPK_LP",
"Ext Spk", "SPK_LN",
"Ext Spk", "SPK_RP",
"Ext Spk", "SPK_RN",
"LINPUT1", "Main MIC",
"Main MIC", "MICB";
/* JD2: hp detect high for headphone*/
hp-det = <2 0>;
};
sound_hdmi: sound-hdmi {
compatible = "fsl,imx-audio-cdnhdmi";
model = "imx-audio-hdmi";
audio-cpu = <&sai4>;
constraint-rate = <32000 44100 48000 96000 192000>;
protocol = <1>;
status = HDMI_STATUS;
};
#endif
};
&A53_0 {
operating-points = <
/* kHz uV */
1500000 1000000
1300000 1000000
1000000 900000
800000 900000
>;
};
&clk {
assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>;
assigned-clock-rates = <786432000>, <722534400>;
};
#if 0
&csi1_bridge {
fsl,mipi-mode;
fsl,two-8bit-sensor-mode;
status = "okay";
port {
csi1_ep: endpoint {
remote-endpoint = <&csi1_mipi_ep>;
};
};
};
&csi2_bridge {
fsl,mipi-mode;
fsl,two-8bit-sensor-mode;
status = "okay";
port {
csi2_ep: endpoint {
remote-endpoint = <&csi2_mipi_ep>;
};
};
};
&dcss {
#ifdef MIPI_ON_DCSS
status = MIPI_DSI_STATUS;
disp-dev = "mipi_disp";
clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
<&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
<&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
<&clk IMX8MQ_CLK_DC_PIXEL_DIV>,
<&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_DISP_DTRC_DIV>;
clock-names = "apb", "axi", "rtrm", "pix_div", "pix_out", "dtrc";
assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL_SRC>,
<&clk IMX8MQ_CLK_DISP_AXI_SRC>,
<&clk IMX8MQ_CLK_DISP_RTRM_SRC>,
<&clk IMX8MQ_CLK_DISP_RTRM_PRE_DIV>,
<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
<&clk IMX8MQ_VIDEO_PLL1>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
<&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_SYS1_PLL_800M>,
<&clk IMX8MQ_VIDEO_PLL1_OUT>,
<&clk IMX8MQ_CLK_25M>;
assigned-clock-rates = <600000000>,
<800000000>,
<400000000>,
<400000000>,
<0>,
<599999999>;
dcss_disp0: port@0 {
reg = <0>;
dcss_disp0_mipi_dsi: mipi_dsi {
remote-endpoint = <&mipi_dsi_in>;
};
};
#else
status = HDMI_STATUS;
disp-dev = "hdmi_disp";
#endif
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
fsl,spi-num-chipselects = <1>;
cs-gpios = GP_ECSPI2_CS0;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
spidev@0 {
compatible = "spidev";
spi-max-frequency = <2000000>;
reg = <0>;
};
};
#endif
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
#if 0
phy-reset-gpios = GP_FEC1_RESET;
#endif
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
interrupts-extended = GPIRQ_FEC1_PHY;
};
};
};
#if 0
&gpu {
status = "okay";
};
&hdmi {
status = HDMI_STATUS;
};
#endif
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
i2cmux@70 {
compatible = "pca9546";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_pca9546>;
reg = <0x70>;
reset-gpios = GP_I2C1_PCA9546_RESET;
#address-cells = <1>;
#size-cells = <0>;
i2c1a: i2c1@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c1b: i2c1@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c1c: i2c1@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c1d: i2c1@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
&i2c1a {
reg_arm_dram: fan53555@60 {
compatible = "fcs,fan53555";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_arm_dram>;
reg = <0x60>;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
vsel-gpios = GP_ARM_DRAM_VSEL;
};
};
&i2c1b {
reg_dram_1p1v: fan53555@60 {
compatible = "fcs,fan53555";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_dram_1p1v>;
reg = <0x60>;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
vsel-gpios = GP_DRAM_1P1_VSEL;
};
};
&i2c1c {
reg_soc_gpu_vpu: fan53555@60 {
compatible = "fcs,fan53555";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>;
reg = <0x60>;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
vsel-gpios = GP_SOC_GPU_VPU_VSEL;
};
};
&i2c1d {
rtc@68 {
compatible = "microcrystal,rv4162";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1d_rv4162>;
reg = <0x68>;
interrupts-extended = GPIRQ_RV4162;
wakeup-source;
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
#if 0
ov5640-mipi1@3c {
compatible = "ov5640_mipisubdev";
reg = <0x3c>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_csi1>;
clocks = <&clk IMX8MQ_CLK_CLKO2>;
clock-names = "csi_mclk";
assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>;
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>;
assigned-clock-rates = <25000000>;
csi_id = <0>;
AVDD-supply = <&reg_vref_2v5>;
DVDD-supply = <&reg_vref_3v3>;
DOVDD-supply = <&reg_vref_1v8>;
pwn-gpios = GP_CSI1_MIPI_PWDN;
rst-gpios = GP_CSI1_MIPI_RESET;
mclk = <25000000>;
mipi_csi;
port {
ov5640_mipi1_ep: endpoint {
remote-endpoint = <&mipi1_sensor_ep>;
};
};
};
#endif
pcie-clock@6a {
compatible = "idt,9FGV0241AKILF";
/* TODO */
reg = <0x6a>;
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
#if 0
ov5640-mipi2@3c {
compatible = "ov5640_mipisubdev";
reg = <0x3c>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_csi2>;
clocks = <&clk IMX8MQ_CLK_CLKO2>;
clock-names = "csi_mclk";
assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>;
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>;
assigned-clock-rates = <25000000>;
csi_id = <1>;
AVDD-supply = <&reg_vref_2v5>;
DVDD-supply = <&reg_vref_3v3>;
DOVDD-supply = <&reg_vref_1v8>;
pwn-gpios = GP_CSI2_MIPI_PWDN;
rst-gpios = GP_CSI2_MIPI_RESET;
mclk = <25000000>;
mipi_csi;
port {
ov5640_mipi2_ep: endpoint {
remote-endpoint = <&mipi2_sensor_ep>;
};
};
};
#endif
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
touchscreen@5d {
compatible = "goodix,gt9271";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4_gt911>;
reg = <0x5d>;
esd-recovery-timeout-ms = <2000>;
interrupts-extended = GPIRQ_GT911;
irq-gpios = GP_GT911_IRQ;
reset-gpios = GP_GT911_RESET;
};
wm8960: codec@1a {
compatible = "wlf,wm8960";
reg = <0x1a>;
clocks = <&clk IMX8MQ_CLK_SAI1_ROOT>;
clock-names = "mclk";
wlf,shared-lrclk;
};
#if 0
mipi_to_lvds: mipi-to-lvds@2c {
clocks = <&mipi_dsi_phy 0>;
clock-names = "mipi_clk";
compatible = "ti,sn65dsi83";
display = <&lcdif>;
display-dsi = <&fb_mipi>;
enable-gpios = GP_I2C4_SN65DSI83_EN;
interrupts-extended = GPIRQ_I2C4_SN65DSI83;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4_sn65dsi83>;
reg = <0x2c>;
status = "disabled";
};
#endif
touchscreen@38 {
compatible = "ft5x06-ts";
interrupts-extended = GPIRQ_I2C4_FT5X06;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4_ft5x06>;
reg = <0x38>;
wakeup-gpios = GP_I2C4_FT5X06_WAKE;
reset-gpios = GP_I2C4_FT5X06_RESET;
};
touchscreen@55 {
compatible = "sitronix,st1633i";
reg = <0x55>;
interrupts-extended = GPIRQ_ST1633;
/* pins used by touchscreen */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4_st1633>;
reset-gpios = GP_ST1633_RESET;
wakeup-gpios = GP_ST1633_IRQ;
};
};
&lcdif {
#if 0
#ifndef MIPI_ON_DCSS
status = "disabled";
assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>,
<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
<&clk IMX8MQ_CLK_25M>;
max-res = <1920>, <1920>;
port@0 {
lcdif_mipi_dsi: mipi-dsi-endpoint {
remote-endpoint = <&mipi_dsi_in>;
};
};
#endif
#endif
};
#if 0
&mipi_csi_1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port {
mipi1_sensor_ep: endpoint1 {
remote-endpoint = <&ov5640_mipi1_ep>;
data-lanes = <1 2>;
};
csi1_mipi_ep: endpoint2 {
remote-endpoint = <&csi1_ep>;
};
};
};
&mipi_csi_2 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port {
mipi2_sensor_ep: endpoint1 {
remote-endpoint = <&ov5640_mipi2_ep>;
data-lanes = <1 2>;
};
csi2_mipi_ep: endpoint2 {
remote-endpoint = <&csi2_ep>;
};
};
};
&mipi_dsi_phy {
status = MIPI_DSI_STATUS;
};
&mipi_dsi {
/delete-property/ no_clk_reset;
status = MIPI_DSI_STATUS;
#ifndef MIPI_ON_DCSS
as_bridge;
#endif
assigned-clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
<&clk IMX8MQ_CLK_DSI_PHY_REF>,
<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
<&clk IMX8MQ_VIDEO_PLL1_OUT>,
<&clk IMX8MQ_CLK_25M>;
assigned-clock-rates = <266000000>;
port@1 {
mipi_dsi_in: endpoint {
#ifdef MIPI_ON_DCSS
remote-endpoint = <&dcss_disp0_mipi_dsi>;
#else
remote-endpoint = <&lcdif_mipi_dsi>;
#endif
};
};
};
&mipi_dsi_bridge {
/delete-property/ no_clk_reset;
status = MIPI_DSI_STATUS;
fb_mipi: panel@0 {
bits-per-color = <8>;
bridge-de-active = <0>;
#if 0
bridge-sync-active = <1>;
#endif
bus-format = "rgb888";
compatible = "panel,simple";
delay-power-up = <2>;
dsi-format = "rgb888";
dsi-lanes = <4>;
mode-skip-eot;
mode-video;
mode-video-burst;
panel-height-mm = <136>;
panel-width-mm = <217>;
power-supply = <&reg_vref_5v>;
reg = <0>;
spwg;
display-timings {
t_mipi: t-dsi-default {
/* m101nwwb by default */
clock-frequency = <70000000>;
hactive = <1280>;
vactive = <800>;
hback-porch = <5>;
hfront-porch = <123>;
vback-porch = <3>;
vfront-porch = <24>;
hsync-len = <1>;
vsync-len = <1>;
hsync-active = <1>;
vsync-active = <1>;
de-active = <1>;
};
};
port {
panel1_in: endpoint {
remote-endpoint = <&mipi_dsi_bridge_out>;
};
};
};
port@1 {
mipi_dsi_bridge_out: endpoint {
remote-endpoint = <&panel1_in>;
};
};
};
#endif
#if 0
&mu {
status = "okay";
};
&pcie0 {
#if 1
clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
<&clk IMX8MQ_CLK_PCIE1_AUX_CG>,
<&clk IMX8MQ_CLK_PCIE1_PHY_CG>,
<&clk IMX8MQ_CLK_CLK2_CG>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_ext_src";
ext_osc = <0>;
#else
ext_osc = <1>;
#endif
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
/* TODO check clock */
disable-gpio = GP_PCIE0_DISABLE;
reset-gpio = GP_PCIE0_RESET;
status = "okay";
};
#endif
#if 0
&pcie1 {
/* TODO check clock */
ext_osc = <1>;
hard-wired = <1>;
status = "disabled";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
#endif
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
#if 0
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
#endif
#if 0
&resmem {
limit3g@0x100000000 {
no-map;
reg = <1 0x00000000 0 0x40000000>;
};
};
&sai1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
assigned-clocks = <&clk IMX8MQ_CLK_SAI1>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <12288000>;
status = "okay";
};
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
status = "okay";
};
&sai4 {
assigned-clocks = <&clk IMX8MQ_CLK_SAI4>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_SAI4_ROOT>, <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>,
<&clk IMX8MQ_AUDIO_PLL2_OUT>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
status = "okay";
};
#endif
#if 0
&uart1 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
uart-has-rtscts;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
assigned-clocks = <&clk IMX8MQ_CLK_UART4>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
status = "okay";
};
#endif
&usb3_phy0 {
status = "okay";
};
&usb3_0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb3_0>;
status = "okay";
};
&usb_dwc3_0 {
#if 0
status = "okay";
#endif
dr_mode = "otg";
vbus-supply = <&reg_usb_otg_vbus>;
};
&usb3_phy1 {
status = "okay";
};
&usb3_1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb3_1>;
reset-gpios = GP_USB3_1_HUB_RESET;
status = "okay";
};
&usb_dwc3_1 {
#if 0
status = "okay";
#endif
dr_mode = "host";
};
&usdhc1 {
cap-mmc-highspeed;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
no-mmc-hs400;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
reset-gpios = GP_EMMC_RESET;
non-removable;
vqmmc-1-8-v;
vmmc-supply = <&reg_vref_1v8>;
status = "okay";
};
#if 0
&usdhc2 {
bus-width = <4>;
no-sd-uhs-sdr104;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
non-removable;
status = "okay";
vmmc-supply = <&reg_wlan_vmmc>;
vqmmc-1-8-v;
};
&vpu {
regulator-supply = <&reg_vref_0v9>;
status = "okay";
};
#endif
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
arch/arm/dts/imx8mq-nitrogen8m_som.dts 0 → 100644
View file @ 8e809399
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2018 Boundary Devices
*/
/dts-v1/;
#include "fsl-imx8mq.dtsi"
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
iomuxc_pinctrl: iomuxc-pinctrlgrp {
};
};
&iomuxc_pinctrl {
pinctrl_bt_rfkill: bt-rfkillgrp {
fsl,pins = <
#define GP_BT_RFKILL_RESET <&gpio3 19 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
/* unused on our carrier */
#define GP_ECSPI2_CS0 <&gpio5 13 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 /* Pin 89 */
MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x19 /* Pin 91 */
MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x19 /* Pin 93 */
MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x19 /* Pin 97 */
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
#define GP_FEC1_RESET <&gpio1 9 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
#define GPIRQ_FEC1_PHY <&gpio1 11 IRQ_TYPE_LEVEL_LOW>
MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59
>;
};
pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
#define GP_GPIOKEY_POWER <&gpio1 7 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 /* Pin 139 */
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
/* J1 connector, odd */
MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* Pin 105 */
MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* Pin 143 */
MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* Pin 145 */
MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* Pin 149 */
MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* Pin 153 */
MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* Pin 155 */
MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* Pin 157 */
/* J1 connector, even */
MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* Pin 82 */
MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* Pin 84 */
MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 /* Pin 86 */
MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 /* Pin 88 */
MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19 /* Pin 90 */
MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x19 /* Pin 92 */
MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 /* Pin 96 */
MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x19 /* Pin 132 */
MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 /* Pin 134 */
MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* Pin 136 */
MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 /* Pin 138 */
MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 /* Pin 140 */
MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* Pin 142 */
MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* Pin 144 */
MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x19 /* Pin 146 */
MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* Pin 148 */
MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* Pin 150 */
MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* Pin 152 */
MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19 /* Pin 154 */
MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19 /* Pin 156 */
MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19 /* Pin 158 */
MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 /* Pin 160 */
MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* Pin 162 */
MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 /* Pin 198 */
MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 /* Pin 200 */
/* J13 Pin 2, BT_FUNC5 (TiWI only) */
MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0xd6
/* J13 Pin 4, WL_IRQ, not needed for Silex */
MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0xd6
/* J13 pin 9, unused */
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
/* J13 Pin 41, BT_CLK_REQ */
MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0xd6
/* J13 Pin 42, BT_HOST_WAKE */
MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0xd6
MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 /* TP79 */
MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49 /* TP80 */
/* Clock for both CSI1 and CSI2 */
MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x07
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_i2c1_pca9546: i2c1-pca9546grp {
fsl,pins = <
#define GP_I2C1_PCA9546_RESET <&gpio1 4 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
>;
};
pinctrl_i2c2_csi1: i2c2-csi1grp {
fsl,pins = <
#define GP_CSI1_MIPI_PWDN <&gpio3 3 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x61
#define GP_CSI1_MIPI_RESET <&gpio3 17 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x61
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
>;
};
pinctrl_i2c3_csi2: i2c3-csi2grp {
fsl,pins = <
#define GP_CSI2_MIPI_PWDN <&gpio3 2 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x61
#define GP_CSI2_MIPI_RESET <&gpio2 19 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x61
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
>;
};
pinctrl_i2c4_gt911: i2c4-gt911grp {
fsl,pins = <
#define GPIRQ_GT911 <&gpio3 12 IRQ_TYPE_LEVEL_HIGH>
#define GP_GT911_IRQ <&gpio3 12 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0xd6
/* driver writes levels, instead of active/inactive */
#define GP_GT911_RESET <&gpio3 13 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x49
>;
};
pinctrl_i2c4_ft5x06: i2c4-ft5x06grp {
fsl,pins = <
#define GPIRQ_I2C4_FT5X06 <&gpio3 12 IRQ_TYPE_EDGE_FALLING>
#define GP_I2C4_FT5X06_WAKE <&gpio3 12 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x49
#define GP_I2C4_FT5X06_RESET <&gpio3 13 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x49
>;
};
pinctrl_i2c4_st1633: i2c4-st1633grp {
fsl,pins = <
#define GPIRQ_ST1633 <&gpio3 12 IRQ_TYPE_EDGE_FALLING>
#define GP_ST1633_IRQ <&gpio3 12 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0xd6
#define GP_ST1633_RESET <&gpio3 13 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x49
>;
};
pinctrl_i2c4_sn65dsi83: i2c4-sn65dsi83grp {
fsl,pins = <
#define GPIRQ_I2C4_SN65DSI83 <&gpio1 1 IRQ_TYPE_LEVEL_HIGH>
MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x04
#define GP_I2C4_SN65DSI83_EN <&gpio3 15 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x06
>;
};
pinctrl_i2c4_pca9546: i2c4-pca9546grp {
fsl,pins = <
#define GP_I2C4_PCA9546_RESET <&gpio3 5 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x49 /* Pin 151 */
>;
};
pinctrl_i2c4b_wm8960: i2c4b-wm8960grp {
fsl,pins = <
#define GP_WM8960_HP_DET <&gpio3 14 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* Pin 53 */
>;
};
pinctrl_i2c4d_rv4162: i2c4d-rv4162grp {
fsl,pins = <
#define GPIRQ_RV4162 <&gpio1 6 IRQ_TYPE_LEVEL_LOW>
MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x49
>;
};
pinctrl_lcm_jm430: lcm-jm430grp {
fsl,pins = <
#define GP_TC358762_EN <&gpio3 15 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16
>;
};
pinctrl_ltk0680ytmdb: ltk0680ytmdbgrp {
fsl,pins = <
#define GP_MIPI_RESET <&gpio1 1 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16
>;
};
pinctrl_ltk080a60a004t: ltk080a60a004tgrp {
fsl,pins = <
#define GP_LTK08_MIPI_EN <&gpio1 1 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
#define GP_PCIE0_RESET <&gpio5 7 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x16
#define GP_PCIE0_DISABLE <&gpio5 6 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x16
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x16
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x16
>;
};
pinctrl_reg_arm_dram: reg-arm-dram {
fsl,pins = <
#define GP_ARM_DRAM_VSEL <&gpio3 24 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16
>;
};
pinctrl_reg_dram_1p1v: reg-dram-1p1v {
fsl,pins = <
#define GP_DRAM_1P1_VSEL <&gpio2 11 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x16
>;
};
pinctrl_reg_soc_gpu_vpu: reg-soc-gpu-vpu {
fsl,pins = <
#define GP_SOC_GPU_VPU_VSEL <&gpio2 20 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x16
>;
};
pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp {
fsl,pins = <
#define GP_REG_USB_OTG_VBUS <&gpio1 12 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x16
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
/* wm8960 */
MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6
MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6
MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
/* our carrier, unused */
MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 /* Pin 166 */
MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0xd6 /* Pin 168 */
MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 /* Pin 170 */
MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 /* Pin 172 */
MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0xd6 /* Pin 174 */
MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 /* Pin 176 */
MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 /* Pin 168 */
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
/* Bluetooth PCM */
MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x45
MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x45
MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x45
MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x45
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x45
MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x45
>;
};
pinctrl_usb3_0: usb3-0grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x16
>;
};
pinctrl_usb3_1: usb3-1grp {
fsl,pins = <
#define GP_USB3_1_HUB_RESET <&gpio1 14 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x03
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x0d
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x1e
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xce
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xce
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xce
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xce
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xce
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};
/ {
model = "Boundary Devices i.MX8MQ Nitrogen8M_som";
compatible = "boundary,imx8mq-nitrogen8m_som", "fsl,imx8mq";
#if 0
aliases {
backlight_mipi = &backlight_mipi;
dcss = &dcss;
fb_mipi = &fb_mipi;
fb_hdmi = &hdmi;
lcdif = &lcdif;
mipi = &fb_mipi;
mipi_cmds_lcm_jm430 = &mipi_cmds_lcm_jm430;
mipi_cmds_ltk0680ytmdb = &mipi_cmds_ltk0680ytmdb;
mipi_cmds_ltk080a60a004t = &mipi_cmds_ltk080a60a004t;
mipi_cmds_m101nwwb = &mipi_cmds_ltk080a60a004t; /* Same commands work for both */
mipi_dsi = &mipi_dsi;
mipi_dsi_bridge = &mipi_dsi_bridge;
mipi_dsi_phy = &mipi_dsi_phy;
mipi_to_lvds = &mipi_to_lvds;
pinctrl_lcm_jm430 = &pinctrl_lcm_jm430;
pinctrl_ltk0680ytmdb = &pinctrl_ltk0680ytmdb;
pinctrl_ltk080a60a004t = &pinctrl_ltk080a60a004t;
sound_hdmi = &sound_hdmi;
t_mipi = &t_mipi;
};
alias_create_phandles {
p1 = <&mipi_cmds_lcm_jm430>;
p2 = <&mipi_cmds_ltk0680ytmdb>;
p3 = <&mipi_cmds_ltk080a60a004t>;
p4 = <&mipi_to_lvds>;
p5 = <&pinctrl_lcm_jm430>;
p6 = <&pinctrl_ltk0680ytmdb>;
p7 = <&pinctrl_ltk080a60a004t>;
};
backlight_mipi: backlight-mipi {
brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>;
compatible = "pwm-backlight";
default-brightness-level = <8>;
display = <&lcdif>;
pwms = <&pwm3 0 30000>; /* 33.3 Khz */
status = "disabled";
};
#endif
bt-rfkill {
compatible = "net,rfkill-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_bt_rfkill>;
name = "bt-rfkill";
type = <2>; /* Bluetooth */
reset-gpios = GP_BT_RFKILL_RESET;
status = "okay";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
power {
label = "Power Button";
gpios = GP_GPIOKEY_POWER;
linux,code = <KEY_POWER>;
gpio-key,wakeup;
};
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usbotg_vbus>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = GP_REG_USB_OTG_VBUS;
enable-active-high;
};
reg_vref_0v9: regulator-vref-0v9 {
compatible = "regulator-fixed";
regulator-name = "vref-0v9";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
};
reg_vref_1v8: regulator-vref-1v8 {
compatible = "regulator-fixed";
regulator-name = "vref-1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_vref_2v5: regulator-vref-2v5 {
compatible = "regulator-fixed";
regulator-name = "vref-2v5";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
};
reg_vref_3v3: regulator-vref-3v3 {
compatible = "regulator-fixed";
regulator-name = "vref-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_vref_5v: regulator-vref-5v {
compatible = "regulator-fixed";
regulator-name = "vref-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
#if 0
sound-wm8960 {
compatible = "fsl,imx-audio-wm8960";
model = "wm8960-audio";
cpu-dai = <&sai1>;
codec-master;
audio-codec = <&wm8960>;
audio-routing =
"Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"Ext Spk", "SPK_LP",
"Ext Spk", "SPK_LN",
"Ext Spk", "SPK_RP",
"Ext Spk", "SPK_RN",
"LINPUT1", "Main MIC",
"Main MIC", "MICB";
/* JD2: hp detect high for headphone*/
hp-det = <2 0>;
hp-det-gpios = GP_WM8960_HP_DET;
};
sound_hdmi: sound-hdmi {
compatible = "fsl,imx-audio-cdnhdmi";
model = "imx-audio-hdmi";
audio-cpu = <&sai4>;
constraint-rate = <32000 44100 48000 96000 192000>;
protocol = <1>;
status = "okay";
};
#endif
};
&A53_0 {
operating-points = <
/* kHz uV */
1500000 1000000
1300000 1000000
1000000 900000
800000 900000
>;
};
&clk {
assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>;
assigned-clock-rates = <786432000>, <722534400>;
};
#if 0
&csi1_bridge {
fsl,mipi-mode;
fsl,two-8bit-sensor-mode;
status = "okay";
port {
csi1_ep: endpoint {
remote-endpoint = <&csi1_mipi_ep>;
};
};
};
&csi2_bridge {
fsl,mipi-mode;
fsl,two-8bit-sensor-mode;
status = "okay";
port {
csi2_ep: endpoint {
remote-endpoint = <&csi2_mipi_ep>;
};
};
};
&dcss {
status = "okay";
disp-dev = "hdmi_disp";
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
fsl,spi-num-chipselects = <1>;
cs-gpios = GP_ECSPI2_CS0;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
spidev@0 {
compatible = "spidev";
spi-max-frequency = <2000000>;
reg = <0>;
};
};
#endif
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
#if 0
phy-reset-gpios = GP_FEC1_RESET;
#endif
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
interrupts-extended = GPIRQ_FEC1_PHY;
};
};
};
#if 0
&gpu {
#if 0
clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
<&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
<&clk IMX8MQ_CLK_GPU_AXI_DIV>,
<&clk IMX8MQ_CLK_GPU_AHB_DIV>;
clock-names = "gpu3d_clk", "gpu3d_shader_clk", "gpu3d_axi_clk", "gpu3d_ahb_clk";
assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
<&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
<&clk IMX8MQ_CLK_GPU_AXI_SRC>,
<&clk IMX8MQ_CLK_GPU_AHB_SRC>;
assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
<&clk IMX8MQ_SYS2_PLL_1000M>,
<&clk IMX8MQ_GPU_PLL_OUT>,
<&clk IMX8MQ_GPU_PLL_OUT>;
assigned-clock-rates = <800000000>,
<1000000000>,
<800000000>,
<800000000>;
#endif
status = "okay";
};
&hdmi {
status = "okay";
};
#endif
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
i2cmux@70 {
compatible = "pca9546";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_pca9546>;
reg = <0x70>;
reset-gpios = GP_I2C1_PCA9546_RESET;
#address-cells = <1>;
#size-cells = <0>;
i2c1a: i2c1@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c1b: i2c1@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c1c: i2c1@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c1d: i2c1@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
&i2c1a {
reg_arm_dram: fan53555@60 {
compatible = "fcs,fan53555";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_arm_dram>;
reg = <0x60>;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
vsel-gpios = GP_ARM_DRAM_VSEL;
};
};
&i2c1b {
reg_dram_1p1v: fan53555@60 {
compatible = "fcs,fan53555";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_dram_1p1v>;
reg = <0x60>;
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
vsel-gpios = GP_DRAM_1P1_VSEL;
};
};
&i2c1c {
reg_soc_gpu_vpu: fan53555@60 {
compatible = "fcs,fan53555";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>;
reg = <0x60>;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
vsel-gpios = GP_SOC_GPU_VPU_VSEL;
};
};
&i2c1d {
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
#if 0
ov5640-mipi1@3c {
compatible = "ov5640_mipisubdev";
reg = <0x3c>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_csi1>;
clocks = <&clk IMX8MQ_CLK_CLKO2_DIV>;
clock-names = "csi_mclk";
assigned-clocks = <&clk IMX8MQ_CLK_CLKO2_SRC>,
<&clk IMX8MQ_CLK_CLKO2_DIV>;
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>;
assigned-clock-rates = <0>, <25000000>;
csi_id = <0>;
AVDD-supply = <&reg_vref_2v5>;
DVDD-supply = <&reg_vref_3v3>;
DOVDD-supply = <&reg_vref_1v8>;
pwn-gpios = GP_CSI1_MIPI_PWDN;
rst-gpios = GP_CSI1_MIPI_RESET;
mclk = <25000000>;
mipi_csi;
port {
ov5640_mipi1_ep: endpoint {
remote-endpoint = <&mipi1_sensor_ep>;
};
};
};
#endif
pcie-clock@6a {
compatible = "idt,9FGV0241AKILF";
/* TODO */
reg = <0x6a>;
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
#if 0
ov5640-mipi2@3c {
compatible = "ov5640_mipisubdev";
reg = <0x3c>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_csi2>;
clocks = <&clk IMX8MQ_CLK_CLKO2_DIV>;
clock-names = "csi_mclk";
assigned-clocks = <&clk IMX8MQ_CLK_CLKO2_SRC>,
<&clk IMX8MQ_CLK_CLKO2_DIV>;
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>;
assigned-clock-rates = <0>, <25000000>;
csi_id = <1>;
AVDD-supply = <&reg_vref_2v5>;
DVDD-supply = <&reg_vref_3v3>;
DOVDD-supply = <&reg_vref_1v8>;
pwn-gpios = GP_CSI2_MIPI_PWDN;
rst-gpios = GP_CSI2_MIPI_RESET;
mclk = <25000000>;
mipi_csi;
port {
ov5640_mipi2_ep: endpoint {
remote-endpoint = <&mipi2_sensor_ep>;
};
};
};
#endif
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
touchscreen@5d {
compatible = "goodix,gt9271";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4_gt911>;
reg = <0x5d>;
esd-recovery-timeout-ms = <2000>;
interrupts-extended = GPIRQ_GT911;
irq-gpios = GP_GT911_IRQ;
reset-gpios = GP_GT911_RESET;
};
#if 0
mipi_to_lvds: mipi-to-lvds@2c {
clocks = <&mipi_dsi_phy 0>;
clock-names = "mipi_clk";
compatible = "ti,sn65dsi83";
display = <&lcdif>;
display-dsi = <&fb_mipi>;
enable-gpios = GP_I2C4_SN65DSI83_EN;
interrupts-extended = GPIRQ_I2C4_SN65DSI83;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4_sn65dsi83>;
reg = <0x2c>;
status = "disabled";
};
#endif
touchscreen@38 {
compatible = "ft5x06-ts";
interrupts-extended = GPIRQ_I2C4_FT5X06;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4_ft5x06>;
reg = <0x38>;
wakeup-gpios = GP_I2C4_FT5X06_WAKE;
reset-gpios = GP_I2C4_FT5X06_RESET;
};
touchscreen@55 {
compatible = "sitronix,st1633i";
reg = <0x55>;
interrupts-extended = GPIRQ_ST1633;
/* pins used by touchscreen */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4_st1633>;
reset-gpios = GP_ST1633_RESET;
wakeup-gpios = GP_ST1633_IRQ;
};
i2cmux@70 {
compatible = "pca9546";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4_pca9546>;
reg = <0x70>;
reset-gpios = GP_I2C4_PCA9546_RESET;
#address-cells = <1>;
#size-cells = <0>;
i2c4a: i2c4@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c4b: i2c4@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c4c: i2c4@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c4d: i2c4@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
&i2c4a {
/* pciei */
};
&i2c4b {
wm8960: codec@1a {
compatible = "wlf,wm8960";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4b_wm8960>;
reg = <0x1a>;
clocks = <&clk IMX8MQ_CLK_SAI1_ROOT>;
clock-names = "mclk";
wlf,shared-lrclk;
};
};
&i2c4c {
/* unused */
};
&i2c4d {
rtc@68 {
compatible = "microcrystal,rv4162";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4d_rv4162>;
reg = <0x68>;
interrupts-extended = GPIRQ_RV4162;
wakeup-source;
};
};
#if 0
&lcdif {
status = "disabled";
assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_SRC>,
<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
<&clk IMX8MQ_CLK_25M>;
max-res = <1920>, <1920>;
port@0 {
lcdif_mipi_dsi: mipi-dsi-endpoint {
remote-endpoint = <&mipi_dsi_in>;
};
};
};
&mipi_csi_1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port {
mipi1_sensor_ep: endpoint1 {
remote-endpoint = <&ov5640_mipi1_ep>;
data-lanes = <1 2>;
};
csi1_mipi_ep: endpoint2 {
remote-endpoint = <&csi1_ep>;
};
};
};
&mipi_csi_2 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
port {
mipi2_sensor_ep: endpoint1 {
remote-endpoint = <&ov5640_mipi2_ep>;
data-lanes = <1 2>;
};
csi2_mipi_ep: endpoint2 {
remote-endpoint = <&csi2_ep>;
};
};
};
&mipi_dsi_phy {
status = "disabled";
};
&mipi_dsi {
status = "disabled";
as_bridge;
assigned-clocks = <&clk IMX8MQ_CLK_DSI_CORE_SRC>,
<&clk IMX8MQ_CLK_DSI_PHY_REF_SRC>,
<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
<&clk IMX8MQ_VIDEO_PLL1_OUT>,
<&clk IMX8MQ_CLK_25M>;
assigned-clock-rates = <266000000>;
clocks = <&clk IMX8MQ_CLK_DSI_CORE_DIV>,
<&clk IMX8MQ_CLK_DSI_PHY_REF_DIV>,
<&clk IMX8MQ_VIDEO_PLL1>;
clock-names = "core", "phy_ref", "pixel_pll";
port@1 {
mipi_dsi_in: endpoint {
remote-endpoint = <&lcdif_mipi_dsi>;
};
};
};
&mipi_dsi_bridge {
status = "disabled";
fb_mipi: panel@0 {
bits-per-color = <8>;
bridge-de-active = <0>;
bridge-sync-active = <1>;
bus-format = "rgb888";
compatible = "panel,simple";
dsi-format = "rgb888";
dsi-lanes = <4>;
mode-skip-eot;
mode-video;
mode-video-burst;
panel-height-mm = <136>;
panel-width-mm = <217>;
power-supply = <&reg_vref_5v>;
reg = <0>;
spwg;
display-timings {
t_mipi: t-dsi-default {
/* m101nwwb by default */
clock-frequency = <70000000>;
hactive = <1280>;
vactive = <800>;
hback-porch = <5>;
hfront-porch = <123>;
vback-porch = <3>;
vfront-porch = <24>;
hsync-len = <1>;
vsync-len = <1>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
};
};
port {
panel1_in: endpoint {
remote-endpoint = <&mipi_dsi_bridge_out>;
};
};
};
port@1 {
mipi_dsi_bridge_out: endpoint {
remote-endpoint = <&panel1_in>;
};
};
};
&mu {
status = "okay";
};
&pcie0 {
#if 1
clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
<&clk IMX8MQ_CLK_PCIE1_AUX_CG>,
<&clk IMX8MQ_CLK_PCIE1_PHY_CG>,
<&clk IMX8MQ_CLK_CLK2_CG>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_ext_src";
ext_osc = <0>;
#else
ext_osc = <1>;
#endif
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
/* TODO check clock */
disable-gpio = GP_PCIE0_DISABLE;
reset-gpio = GP_PCIE0_RESET;
status = "okay";
};
&pcie1 {
/* TODO check clock */
ext_osc = <1>;
hard-wired = <1>;
status = "disabled";
};
#endif
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
#if 0
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&sai1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
assigned-clocks = <&clk IMX8MQ_CLK_SAI1_SRC>,
<&clk IMX8MQ_CLK_SAI1_DIV>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <0>, <12288000>;
status = "okay";
};
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
status = "disabled";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
status = "okay";
};
&sai4 {
assigned-clocks = <&clk IMX8MQ_CLK_SAI4_SRC>,
<&clk IMX8MQ_CLK_SAI4_DIV>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <0>, <24576000>;
clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_SAI4_ROOT>, <&clk IMX8MQ_CLK_DUMMY>,
<&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>,
<&clk IMX8MQ_AUDIO_PLL2_OUT>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
status = "okay";
};
#endif
#if 0
&uart1 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
assigned-clocks = <&clk IMX8MQ_CLK_UART2_SRC>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
uart-has-rtscts;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
assigned-clocks = <&clk IMX8MQ_CLK_UART4_SRC>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
status = "okay";
};
#endif
&usb3_phy0 {
status = "okay";
};
&usb3_0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb3_0>;
status = "okay";
};
&usb_dwc3_0 {
#if 0
status = "okay";
#endif
dr_mode = "otg";
vbus-supply = <&reg_usb_otg_vbus>;
};
&usb3_phy1 {
status = "okay";
};
&usb3_1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb3_1>;
reset-gpios = GP_USB3_1_HUB_RESET;
status = "okay";
};
&usb_dwc3_1 {
#if 0
status = "okay";
#endif
dr_mode = "host";
};
&usdhc1 {
cap-mmc-highspeed;
bus-width = <8>;
// mmc-ddr-1_8v;
// mmc-hs200-1_8v;
fsl,strobe-dll-delay-target = <5>;
fsl,tuning-start-tap = <63>;
fsl,tuning-step = <2>;
no-mmc-hs400;
non-removable;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
status = "okay";
vmmc-supply = <&reg_vref_1v8>;
vqmmc-1-8-v;
};
&usdhc2 {
bus-width = <4>;
fsl,tuning-start-tap = <70>;
fsl,tuning-step = <2>;
no-sd-uhs-sdr104;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
non-removable;
status = "okay";
tuning-delay = <32>;
tuning-mode = <1>;
vmmc-supply = <&reg_vref_3v3>;
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
arch/arm/dts/imx8mq-son.dts 0 → 100644
View file @ 8e809399
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2018 Boundary Devices
*/
/dts-v1/;
/* First 128KB is for PSCI ATF. */
/memreserve/ 0x40000000 0x00020000;
#include "fsl-imx8mq.dtsi"
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_backlight: backlightgrp {
fsl,pins = <
#define GP_BACKLIGHT_EN <&gpio3 24 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x03
>;
};
pinctrl_bt_rfkill: bt-rfkillgrp {
fsl,pins = <
#define GP_BT_RFKILL_RESET <&gpio3 13 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x19
>;
};
pinctrl_ecspi1: ecspi2grp {
fsl,pins = <
/* MCP2515 */
#define GP_ECSPI1_CS0 <&gpio5 9 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19
MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x19
MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x19
MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x19
>;
};
pinctrl_ecspi1_mcp2515: ecspi1-mcp2515grp {
fsl,pins = <
#define GP_MCP2515_RESET <&gpio1 4 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x06
#define GPIRQ_MCP2515 <&gpio1 8 IRQ_TYPE_EDGE_FALLING>
MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xc6
#define GP_MCP2515_ENABLE <&gpio1 3 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x06
#define GPIRQ_MCP2515_ERR <&gpio1 0 IRQ_TYPE_EDGE_FALLING>
MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0xc6
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x19 /* J23 Pin 6 */
MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x19 /* J23 Pin 8 */
#define GP_ECSPI2_CS0 <&gpio5 13 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 /* J23 Pin 9 */
MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x19 /* J23 Pin 10 */
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
#define GP_FEC1_RESET <&gpio1 9 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
#define GPIRQ_FEC1_PHY <&gpio1 11 IRQ_TYPE_LEVEL_LOW>
MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59
>;
};
pinctrl_gpio_keys: gpio-keysgrp {
fsl,pins = <
#define GP_AC_FAIL <&gpio3 10 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0xc6 /* J8 Pin 4*/
#define GP_FAN_FAIL <&gpio3 9 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0xc6 /* J8 Pin 5*/
#define GP_FASTBOOT_KEY <&gpio1 7 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
#define GP_GPI1 <&gpio3 7 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0xc6 /* J9 Pin 7*/
#define GP_GPI2 <&gpio3 6 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0xc6 /* J9 Pin 4*/
#define GP_ON <&gpio1 1 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1
#define GP_POWER <&gpio3 2 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19
#define GP_TEMP_ALARM <&gpio3 8 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0xc6 /* J8 Pin 7*/
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0xc6 /* WIFI EN */
/* J17 connector, odd */
MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24 0xc6 /* Pin 15 */
MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23 0xc6 /* Pin 23 */
MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0xc6 /* Pin 25 */
MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0xc6 /* Pin 29 */
MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0xc6 /* Pin 19 */
MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0xc6 /* Pin 21 */
MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0xc6 /* Pin 39 */
MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0xc6 /* Pin 41 */
MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0xc6 /* Pin 43 */
/* J17 connector, even */
MX8MQ_IOMUXC_SAI2_MCLK_GPIO4_IO27 0xc6 /* Pin 32 */
MX8MQ_IOMUXC_SAI2_TXD0_GPIO4_IO26 0xc6 /* Pin 34 */
MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0xc6 /* Pin 56 */
/* J18 connector, odd */
MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0xc6 /* Pin 43 */
MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0xc6 /* Pin 47 */
MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0xc6 /* Pin 49 */
MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0xc6 /* Pin 51 */
/* J18 connector, even */
MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0xc6 /* Pin 36 */
MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0xc6 /* Pin 38 */
MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0xc6 /* Pin 40 */
/* Clock for both CSI1 and CSI2 */
MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0xc6
MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0xc6
/* test points */
MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xc6 /* TP145 */
MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0xc6 /* TP146 */
MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0xc6 /* TP147 */
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
>;
};
pinctrl_i2c1_1: i2c1_1grp {
fsl,pins = <
#define GP_I2C1_SCL <&gpio5 14 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x4000007f
#define GP_I2C1_SDA <&gpio5 15 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x4000007f
>;
};
pinctrl_i2c1_pf8100: i2c1-pf8100grp {
fsl,pins = <
#define GP_I2C1_PF8100_EWARN <&gpio3 23 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0xc1
#define GP_I2C1_PF8100_FAULT <&gpio3 22 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0xc1
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
>;
};
pinctrl_i2c2_1: i2c2_1grp {
fsl,pins = <
#define GP_I2C2_SCL <&gpio5 16 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x4000007f
#define GP_I2C2_SDA <&gpio5 17 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x4000007f
>;
};
pinctrl_i2c2_pca9546: i2c2-pca9546grp {
fsl,pins = <
#define GP_I2C2_PCA9546_RESET <&gpio3 18 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x49
>;
};
pinctrl_i2c2a_sn65dsi83: i2c2a-sn65dsi83grp {
fsl,pins = <
#define GPIRQ_I2C2A_SN65DSI83 <&gpio3 19 IRQ_TYPE_LEVEL_HIGH>
MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x04
#define GP_I2C2A_SN65DSI83_EN <&gpio3 15 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x06
>;
};
pinctrl_i2c2d_rv4162: i2c2d-rv4162grp {
fsl,pins = <
#define GPIRQ_RV4162 <&gpio1 6 IRQ_TYPE_LEVEL_LOW>
MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x49
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
>;
};
pinctrl_i2c3_1: i2c3_1grp {
fsl,pins = <
#define GP_I2C3_SCL <&gpio5 18 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18 0x4000007f
#define GP_I2C3_SDA <&gpio5 19 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19 0x4000007f
>;
};
pinctrl_i2c3_sc16is7xx: i2c3-sc16is7xxgrp {
fsl,pins = <
#define GPIRQ_SC16IS7XX <&gpio4 30 IRQ_TYPE_LEVEL_LOW>
MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30 0xc1
#define GP_SC16IS7XX_RESET <&gpio4 29 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0xc1
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
>;
};
pinctrl_i2c4_1: i2c4_1grp {
fsl,pins = <
#define GP_I2C4_SCL <&gpio5 20 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20 0x4000007f
#define GP_I2C4_SDA <&gpio5 21 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21 0x4000007f
>;
};
/* i2c4 wm8960 - Amplifier Mute, TDA7491LP13TR */
pinctrl_i2c4_wm8960: i2c4-wm8960grp {
fsl,pins = <
#define GP_WM8960_AMP_STDBY <&gpio4 28 GPIO_ACTIVE_LOW> /* Low is standby */
MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x06
#define GP_WM8960_AMP_MUTE <&gpio4 31 GPIO_ACTIVE_LOW> /* Low is muted */
MX8MQ_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x06
#define GP_WM8960_AMP_G0 <&gpio5 0 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_SAI3_TXC_GPIO5_IO0 0x06
#define GP_WM8960_AMP_G1 <&gpio5 1 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x06
>;
};
pinctrl_leds: ledsgrp {
fsl,pins = <
#define GP_J9_PIN6 <&gpio3 11 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x06
#define GP_J13_PIN2 <&gpio4 19 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x06
#define GP_J13_PIN3 <&gpio4 18 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x06
#define GP_J15_PIN2 <&gpio4 5 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x06
#define GP_J15_PIN3 <&gpio4 4 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x06
#define GP_J25_PIN2 <&gpio4 17 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x06
#define GP_J25_PIN3 <&gpio4 16 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x06
#define GP_J26_PIN2 <&gpio4 3 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x06
#define GP_J26_PIN3 <&gpio4 6 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x06
#define GP_LED1 <&gpio4 7 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19
#define GP_LED2 <&gpio4 8 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19
#define GP_LED3 <&gpio4 25 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25 0xd6
#define GP_RELAY <&gpio3 12 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x06
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
#define GP_PCIE0_RESET <&gpio3 14 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x16
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x16 /* J17 pin 31 */
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x16
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x16
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x16
>;
};
pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp {
fsl,pins = <
#define GP_REG_USB_OTG_VBUS <&gpio1 12 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x16
>;
};
pinctrl_reg_usdhc2_vqmmc: reg-usdhc2-vqmmcgrp {
fsl,pins = <
#define GP_USDHC2_VSEL <&gpio3 20 GPIO_ACTIVE_HIGH>
MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x16
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
/* wm8960 */
MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6
MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6
MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6
MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6
MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45
MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45
MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x45
MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x45
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x45
MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x45
>;
};
pinctrl_usb3_0: usb3-0grp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x16
>;
};
pinctrl_usb3_1: usb3-1grp {
fsl,pins = <
#define GP_USB3_1_HUB_RESET <&gpio1 14 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
#define GP_EMMC_RESET <&gpio2 10 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
#define GP_USDHC2_CD <&gpio2 12 GPIO_ACTIVE_LOW>
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0xc3
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf
MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf
MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf
MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};
/ {
model = "Boundary Devices i.MX8MQ Son";
compatible = "boundary,imx8mq-son", "fsl,imx8mq";
chosen {
bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
#if 0
stdout-path = &uart1;
#endif
};
#if 0
backlight_mipi: backlight-mipi {
brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>;
compatible = "pwm-backlight";
default-brightness-level = <8>;
display = <&lcdif>;
enable-gpios = GP_BACKLIGHT_EN;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_backlight>;
pwms = <&pwm3 0 30000>; /* 33.3 Khz */
status = "disabled";
};
#endif
bt-rfkill {
compatible = "net,rfkill-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_bt_rfkill>;
name = "bt-rfkill";
type = <2>; /* Bluetooth */
reset-gpios = GP_BT_RFKILL_RESET;
status = "okay";
};
clocks {
clk16m: clk16m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <16000000>;
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
ac-fail {
label = "Fan failure";
gpios = GP_AC_FAIL;
linux,code = <KEY_A>;
gpio-key,wakeup;
};
fan-fail {
label = "Fan failure";
gpios = GP_FAN_FAIL;
linux,code = <KEY_F>;
gpio-key,wakeup;
};
fastboot {
label = "fastboot Button";
gpios = GP_FASTBOOT_KEY;
linux,code = <KEY_ESC>;
gpio-key,wakeup;
};
gpi1 {
label = "GPI1 Button";
gpios = GP_GPI1;
linux,code = <KEY_1>;
gpio-key,wakeup;
};
gpi2 {
label = "GPI2 Button";
gpios = GP_GPI2;
linux,code = <KEY_2>;
gpio-key,wakeup;
};
on {
label = "on Button";
gpios = GP_ON;
linux,code = <KEY_0>;
gpio-key,wakeup;
};
power {
label = "Power Button";
gpios = GP_POWER;
linux,code = <KEY_POWER>;
gpio-key,wakeup;
};
temp-alarm {
label = "Temperature Alarm";
gpios = GP_TEMP_ALARM;
linux,code = <KEY_T>;
gpio-key,wakeup;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_leds>;
j9-pin6 {
gpios = GP_J9_PIN6;
retain-state-suspended;
default-state = "off";
};
j13-pin2 {
gpios = GP_J13_PIN2;
retain-state-suspended;
default-state = "off";
};
j13-pin3 {
gpios = GP_J13_PIN3;
retain-state-suspended;
default-state = "off";
};
j15-pin2 {
gpios = GP_J15_PIN2;
retain-state-suspended;
default-state = "off";
};
j15-pin3 {
gpios = GP_J15_PIN3;
retain-state-suspended;
default-state = "off";
};
j25-pin2 {
gpios = GP_J25_PIN2;
retain-state-suspended;
default-state = "off";
};
j25-pin3 {
gpios = GP_J25_PIN3;
retain-state-suspended;
default-state = "off";
};
j26-pin2 {
gpios = GP_J26_PIN2;
retain-state-suspended;
default-state = "off";
};
j26-pin3 {
gpios = GP_J26_PIN3;
retain-state-suspended;
default-state = "off";
};
led1 {
gpios = GP_LED1;
retain-state-suspended;
default-state = "off";
};
led2 {
gpios = GP_LED2;
retain-state-suspended;
default-state = "off";
};
led3 {
gpios = GP_LED3;
retain-state-suspended;
default-state = "off";
};
relay {
gpios = GP_RELAY;
retain-state-suspended;
default-state = "off";
};
};
mipi_mclk: mipi-mclk {
compatible = "pwm-clock";
#clock-cells = <0>;
clock-frequency = <22000000>;
clock-output-names = "mipi_mclk";
#if 0
pwms = <&pwm1 0 45>; /* 1 / 45 ns = 22 MHz */
#endif
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usbotg_vbus>;
regulator-name = "usb_otg_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = GP_REG_USB_OTG_VBUS;
enable-active-high;
};
reg_vref_0v9: regulator-vref-0v9 {
compatible = "regulator-fixed";
regulator-name = "vref-0v9";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
};
reg_vref_1v8: regulator-vref-1v8 {
compatible = "regulator-fixed";
regulator-name = "vref-1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reg_vref_3v3: regulator-vref-3v3 {
compatible = "regulator-fixed";
regulator-name = "vref-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_vref_5v: regulator-vref-5v {
compatible = "regulator-fixed";
regulator-name = "vref-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
compatible = "regulator-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vqmmc>;
regulator-name = "reg_sd2_vsel";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-type = "voltage";
regulator-boot-on;
regulator-always-on;
gpios = GP_USDHC2_VSEL;
states = <1800000 0x1
3300000 0x0>;
};
#if 0
sound-wm8960 {
amp-mute-gpios = GP_WM8960_AMP_MUTE;
/* delay between mute and standby enter */
amp-standby-enter-wait-ms = <50>;
/* delay between standby exit and unmute */
amp-standby-exit-delay-ms = <100>;
amp-standby-gpios = GP_WM8960_AMP_STDBY;
amp-gain-gpios = GP_WM8960_AMP_G0, GP_WM8960_AMP_G1;
/* amp-gain-seq = /bits/ 8 <0 1 2 3>; */ /* default */
compatible = "fsl,imx-audio-wm8960";
model = "wm8960-audio";
cpu-dai = <&sai1>;
codec-master;
audio-codec = <&wm8960>;
audio-routing =
"Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"LINPUT1", "Main MIC",
"Main MIC", "MICB";
/* JD2: hp detect high for headphone*/
hp-det = <2 0>;
};
sound_hdmi: sound-hdmi {
compatible = "fsl,imx-audio-cdnhdmi";
model = "imx-audio-hdmi";
audio-cpu = <&sai4>;
constraint-rate = <32000 44100 48000 96000 192000>;
protocol = <1>;
status = "okay";
};
#endif
};
&A53_0 {
arm-supply = <&reg_sw4>;
};
&clk {
assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>;
assigned-clock-rates = <786432000>, <722534400>;
};
#if 0
&dcss {
status = "okay";
disp-dev = "hdmi_disp";
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
fsl,spi-num-chipselects = <1>;
cs-gpios = GP_ECSPI2_CS0;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
/* can bus */
mcp2515: mcp2515@0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_mcp2515>;
compatible = "microchip,mcp2515";
clocks = <&clk16m>;
interrupts-extended = GPIRQ_MCP2515;
reg = <0>;
reset-gpios = GP_MCP2515_RESET;
enable-gpios = GP_MCP2515_ENABLE;
err-gpios = GPIRQ_MCP2515_ERR;
spi-max-frequency = <10000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};
#endif
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
#if 0
phy-reset-gpios = GP_FEC1_RESET;
#endif
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
interrupts-extended = GPIRQ_FEC1_PHY;
};
};
};
#if 0
&gpu {
status = "okay";
};
&hdmi {
status = "okay";
};
#endif
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_1>;
scl-gpios = GP_I2C1_SCL;
sda-gpios = GP_I2C1_SDA;
status = "okay";
pf8100@08 {
compatible = "nxp,pf8x00";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_pf8100>;
reg = <0x08>;
regulators {
reg_ldo1: ldo1 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <1500000>;
};
reg_ldo2: ldo2 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <1500000>;
/* vselect low is 3.3V, high is 1.8V */
vselect-en;
};
reg_ldo3: ldo3 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <1500000>;
};
reg_ldo4: ldo4 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <1500000>;
};
reg_sw1: sw1 {
phase = <0>;
ilim-ma = <4500>;
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <400000>;
};
reg_sw2: sw2 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <400000>;
};
reg_sw3: sw3 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <400000>;
};
reg_sw4: sw4 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <400000>;
dual-phase;
};
reg_sw5: sw5 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <400000>;
};
reg_sw6: sw6 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1800000>;
regulator-min-microvolt = <400000>;
};
reg_sw7: sw7 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <4100000>;
regulator-min-microvolt = <1000000>;
};
reg_vsnvs: vsnvs {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1800000>;
};
};
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_1>;
scl-gpios = GP_I2C2_SCL;
sda-gpios = GP_I2C2_SDA;
status = "okay";
i2cmux@70 {
compatible = "pca9546";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_pca9546>;
reg = <0x70>;
reset-gpios = GP_I2C2_PCA9546_RESET;
#address-cells = <1>;
#size-cells = <0>;
i2c2a: i2c2@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c2b: i2c2@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c2c: i2c2@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
i2c2d: i2c2@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
&i2c2a {
#if 0
mipi_to_lvds: mipi-to-lvds@2c {
clocks = <&mipi_dsi_phy 0>;
clock-names = "mipi_clk";
compatible = "ti,sn65dsi83";
display = <&lcdif>;
display-dsi = <&fb_mipi>;
enable-gpios = GP_I2C2A_SN65DSI83_EN;
interrupts-extended = GPIRQ_I2C2A_SN65DSI83;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2a_sn65dsi83>;
reg = <0x2c>;
status = "disabled";
};
#endif
};
&i2c2b {
/* J27 */
};
&i2c2c {
/* J28 */
};
&i2c2d {
rtc@68 {
compatible = "microcrystal,rv4162";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2d_rv4162>;
reg = <0x68>;
interrupts-extended = GPIRQ_RV4162;
wakeup-source;
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_1>;
scl-gpios = GP_I2C3_SCL;
sda-gpios = GP_I2C3_SDA;
status = "okay";
sc16is7xx-uart@49 {
compatible = "nxp,sc16is7xx-uart";
interrupts-extended = GPIRQ_SC16IS7XX;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_sc16is7xx>;
reg = <0x49>;
reset-gpio = GP_SC16IS7XX_RESET;
};
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_1>;
scl-gpios = GP_I2C4_SCL;
sda-gpios = GP_I2C4_SDA;
status = "okay";
wm8960: codec@1a {
compatible = "wlf,wm8960";
clock-names = "mclk";
clocks = <&clk IMX8MQ_CLK_SAI1_ROOT>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4_wm8960>;
reg = <0x1a>;
wlf,shared-lrclk;
};
};
&lcdif {
#if 0
status = "disabled";
assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>,
<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>;
assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
<&clk IMX8MQ_CLK_25M>;
max-res = <1920>, <1920>;
port@0 {
lcdif_mipi_dsi: mipi-dsi-endpoint {
remote-endpoint = <&mipi_dsi_in>;
};
};
#endif
};
#if 0
&mipi_dsi_phy {
status = "disabled";
};
&mipi_dsi {
/delete-property/ no_clk_reset;
status = "disabled";
as_bridge;
assigned-clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
<&clk IMX8MQ_CLK_DSI_PHY_REF>,
<&clk IMX8MQ_VIDEO_PLL1_REF_SEL>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
<&clk IMX8MQ_VIDEO_PLL1_OUT>,
<&clk IMX8MQ_CLK_25M>;
assigned-clock-rates = <266000000>;
port@1 {
mipi_dsi_in: endpoint {
remote-endpoint = <&lcdif_mipi_dsi>;
};
};
};
&mipi_dsi_bridge {
/delete-property/ no_clk_reset;
status = "disabled";
fb_mipi: panel@0 {
bits-per-color = <8>;
bridge-de-active = <0>;
#if 0
bridge-sync-active = <1>;
#endif
bus-format = "rgb888";
compatible = "panel,simple";
delay-power-up = <2>;
dsi-format = "rgb888";
dsi-lanes = <4>;
mode-skip-eot;
mode-video;
mode-video-burst;
panel-height-mm = <136>;
panel-width-mm = <217>;
power-supply = <&reg_vref_5v>;
reg = <0>;
display-timings {
t_mipi: t-dsi-default {
/* m101nwwb by default */
clock-frequency = <70000000>;
hactive = <1280>;
vactive = <800>;
hback-porch = <5>;
hfront-porch = <123>;
vback-porch = <3>;
vfront-porch = <24>;
hsync-len = <1>;
vsync-len = <1>;
hsync-active = <1>;
vsync-active = <1>;
de-active = <1>;
};
};
port {
panel1_in: endpoint {
remote-endpoint = <&mipi_dsi_bridge_out>;
};
};
};
port@1 {
mipi_dsi_bridge_out: endpoint {
remote-endpoint = <&panel1_in>;
};
};
};
#endif
#if 0
&mu {
status = "okay";
};
&pcie0 {
#if 1
clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
<&clk IMX8MQ_CLK_PCIE1_AUX_CG>,
<&clk IMX8MQ_CLK_PCIE1_PHY_CG>,
<&clk IMX8MQ_CLK_CLK2_CG>;
clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_ext_src";
ext_osc = <0>;
#else
ext_osc = <1>;
#endif
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
/* TODO check clock */
reset-gpio = GP_PCIE0_RESET;
status = "okay";
};
#endif
#if 0
&pcie1 {
/* TODO check clock */
ext_osc = <1>;
hard-wired = <1>;
status = "disabled";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
#endif
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
#if 0
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
#endif
#if 0
&resmem {
limit3g@0x100000000 {
no-map;
reg = <1 0x00000000 0 0x40000000>;
};
};
&sai1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
assigned-clocks = <&clk IMX8MQ_CLK_SAI1>;
assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
assigned-clock-rates = <12288000>;
status = "okay";
};
#endif
#if 0
&uart1 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MQ_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
assigned-clocks = <&clk IMX8MQ_CLK_UART4>;
assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
status = "okay";
};
#endif
&usb3_phy0 {
status = "okay";
};
&usb3_0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb3_0>;
status = "okay";
};
&usb_dwc3_0 {
#if 0
status = "okay";
#endif
dr_mode = "otg";
vbus-supply = <&reg_usb_otg_vbus>;
};
&usb3_phy1 {
status = "okay";
};
&usb3_1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb3_1>;
reset-gpios = GP_USB3_1_HUB_RESET;
status = "okay";
};
&usb_dwc3_1 {
#if 0
status = "okay";
#endif
dr_mode = "host";
};
&usdhc1 {
cap-mmc-highspeed;
bus-width = <8>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
no-mmc-hs400;
non-removable;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
reset-gpios = GP_EMMC_RESET;
status = "okay";
vmmc-supply = <&reg_vref_3v3>;
vqmmc-1-8-v;
vqmmc-supply = <&reg_vref_1v8>;
};
&usdhc2 {
bus-width = <4>;
cap-sd-highspeed;
cd-gpios = GP_USDHC2_CD;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
sd-uhs-ddr50;
sd-uhs-sdr104;
sd-uhs-sdr12;
sd-uhs-sdr25;
status = "okay";
vmmc-supply = <&reg_vref_3v3>;
#if 1
vqmmc-supply = <&reg_usdhc2_vqmmc>;
#else
vqmmc-supply = <&reg_ldo2>;
#endif
};
#if 0
&vpu {
status = "okay";
regulator-supply = <&reg_vref_0v9>;
};
#endif
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
arch/arm/include/asm/arch-imx/cpu.h
View file @ 8e809399
......@@ -17,6 +17,7 @@
#define MXC_CPU_MX6Q 0x63
#define MXC_CPU_MX6UL 0x64
#define MXC_CPU_MX6ULL 0x65
#define MXC_CPU_MX6ULZ 0x6B
#define MXC_CPU_MX6SOLO 0x66 /* dummy */
#define MXC_CPU_MX6SLL 0x67
#define MXC_CPU_MX6D 0x6A
......@@ -24,13 +25,25 @@
#define MXC_CPU_MX6QP 0x69
#define MXC_CPU_MX7S 0x71 /* dummy ID */
#define MXC_CPU_MX7D 0x72
#define MXC_CPU_MX8MQ 0x82
#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
#define MXC_CPU_IMX8MQ 0x82
#define MXC_CPU_IMX8MM 0x85 /* dummy ID */
#define MXC_CPU_IMX8MML 0x86 /* dummy ID */
#define MXC_CPU_IMX8MMD 0x87 /* dummy ID */
#define MXC_CPU_IMX8MMDL 0x88 /* dummy ID */
#define MXC_CPU_IMX8MMS 0x89 /* dummy ID */
#define MXC_CPU_IMX8MMSL 0x8a /* dummy ID */
#define MXC_CPU_IMX8MN 0x8b /* dummy ID */
#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
#define MXC_CPU_IMX8QM 0x91 /* dummy ID */
#define MXC_CPU_IMX8QXP 0x92 /* dummy ID */
#define MXC_CPU_VF610 0xF6 /* dummy ID */
#define MXC_SOC_MX6 0x60
#define MXC_SOC_MX7 0x70
#define MXC_SOC_MX8M 0x80
#define MXC_SOC_IMX8M 0x80
#define MXC_SOC_IMX8 0x90 /* dummy */
#define MXC_SOC_MX7ULP 0xE0 /* dummy */
#define CHIP_REV_1_0 0x10
......@@ -38,6 +51,7 @@
#define CHIP_REV_1_2 0x12
#define CHIP_REV_1_5 0x15
#define CHIP_REV_2_0 0x20
#define CHIP_REV_2_1 0x21
#define CHIP_REV_2_5 0x25
#define CHIP_REV_3_0 0x30
......
arch/arm/include/asm/arch-imx8/imx-regs.h 0 → 100644
View file @ 8e809399
/*
* Copyright 2017 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*
*/
#ifndef __ASM_ARCH_IMX_REGS_H__
#define __ASM_ARCH_IMX_REGS_H__
#define MU_BASE_ADDR(id) ((0x5D1B0000UL + (id*0x10000)))
#define LPUART_BASE 0x5A060000
#define GPT1_BASE_ADDR 0x5D140000
#define SCU_LPUART_BASE 0x33220000
#define GPIO1_BASE_ADDR 0x5D080000
#define GPIO2_BASE_ADDR 0x5D090000
#define GPIO3_BASE_ADDR 0x5D0A0000
#define GPIO4_BASE_ADDR 0x5D0B0000
#define GPIO5_BASE_ADDR 0x5D0C0000
#define GPIO6_BASE_ADDR 0x5D0D0000
#define GPIO7_BASE_ADDR 0x5D0E0000
#define GPIO8_BASE_ADDR 0x5D0F0000
#define LPI2C1_BASE_ADDR 0x5A800000
#define LPI2C2_BASE_ADDR 0x5A810000
#define LPI2C3_BASE_ADDR 0x5A820000
#define LPI2C4_BASE_ADDR 0x5A830000
#define LPI2C5_BASE_ADDR 0x5A840000
#ifdef CONFIG_LPUART
#define LPUART_BASE SCU_LPUART_BASE
#endif
#define ROM_SW_INFO_ADDR 0x00000890
#define USB_BASE_ADDR 0x5b0d0000
#define USB_PHY0_BASE_ADDR 0x5b100000
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
/*
* If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB
* If boot from the other mode, USB0_PWD will keep reset value
*/
#define is_boot_from_usb(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20)))
#define disconnect_from_pc(void) writel(0x0, USB_BASE_ADDR + 0x140)
struct usbphy_regs {
u32 usbphy_pwd; /* 0x000 */
u32 usbphy_pwd_set; /* 0x004 */
u32 usbphy_pwd_clr; /* 0x008 */
u32 usbphy_pwd_tog; /* 0x00c */
u32 usbphy_tx; /* 0x010 */
u32 usbphy_tx_set; /* 0x014 */
u32 usbphy_tx_clr; /* 0x018 */
u32 usbphy_tx_tog; /* 0x01c */
u32 usbphy_rx; /* 0x020 */
u32 usbphy_rx_set; /* 0x024 */
u32 usbphy_rx_clr; /* 0x028 */
u32 usbphy_rx_tog; /* 0x02c */
u32 usbphy_ctrl; /* 0x030 */
u32 usbphy_ctrl_set; /* 0x034 */
u32 usbphy_ctrl_clr; /* 0x038 */
u32 usbphy_ctrl_tog; /* 0x03c */
u32 usbphy_status; /* 0x040 */
u32 reserved0[3];
u32 usbphy_debug0; /* 0x050 */
u32 usbphy_debug0_set; /* 0x054 */
u32 usbphy_debug0_clr; /* 0x058 */
u32 usbphy_debug0_tog; /* 0x05c */
u32 reserved1[4];
u32 usbphy_debug1; /* 0x070 */
u32 usbphy_debug1_set; /* 0x074 */
u32 usbphy_debug1_clr; /* 0x078 */
u32 usbphy_debug1_tog; /* 0x07c */
u32 usbphy_version; /* 0x080 */
u32 reserved2[7];
u32 usb1_pll_480_ctrl; /* 0x0a0 */
u32 usb1_pll_480_ctrl_set; /* 0x0a4 */
u32 usb1_pll_480_ctrl_clr; /* 0x0a8 */
u32 usb1_pll_480_ctrl_tog; /* 0x0ac */
u32 reserved3[4];
u32 usb1_vbus_detect; /* 0xc0 */
u32 usb1_vbus_detect_set; /* 0xc4 */
u32 usb1_vbus_detect_clr; /* 0xc8 */
u32 usb1_vbus_detect_tog; /* 0xcc */
u32 usb1_vbus_det_stat; /* 0xd0 */
u32 reserved4[3];
u32 usb1_chrg_detect; /* 0xe0 */
u32 usb1_chrg_detect_set; /* 0xe4 */
u32 usb1_chrg_detect_clr; /* 0xe8 */
u32 usb1_chrg_detect_tog; /* 0xec */
u32 usb1_chrg_det_stat; /* 0xf0 */
u32 reserved5[3];
u32 usbphy_anactrl; /* 0x100 */
u32 usbphy_anactrl_set; /* 0x104 */
u32 usbphy_anactrl_clr; /* 0x108 */
u32 usbphy_anactrl_tog; /* 0x10c */
u32 usb1_loopback; /* 0x110 */
u32 usb1_loopback_set; /* 0x114 */
u32 usb1_loopback_clr; /* 0x118 */
u32 usb1_loopback_tog; /* 0x11c */
u32 usb1_loopback_hsfscnt; /* 0x120 */
u32 usb1_loopback_hsfscnt_set; /* 0x124 */
u32 usb1_loopback_hsfscnt_clr; /* 0x128 */
u32 usb1_loopback_hsfscnt_tog; /* 0x12c */
u32 usphy_trim_override_en; /* 0x130 */
u32 usphy_trim_override_en_set; /* 0x134 */
u32 usphy_trim_override_en_clr; /* 0x138 */
u32 usphy_trim_override_en_tog; /* 0x13c */
u32 usb1_pfda_ctrl1; /* 0x140 */
u32 usb1_pfda_ctrl1_set; /* 0x144 */
u32 usb1_pfda_ctrl1_clr; /* 0x148 */
u32 usb1_pfda_ctrl1_tog; /* 0x14c */
};
#endif
#endif /* __ASM_ARCH_IMX_REGS_H__ */
arch/arm/include/asm/arch-imx8m/clock.h 0 → 100644
View file @ 8e809399
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2017-2018 NXP
*
* Peng Fan <peng.fan@nxp.com>
*/
#ifndef _ASM_ARCH_IMX8M_CLOCK_H
#define _ASM_ARCH_IMX8M_CLOCK_H
#define MHZ(X) ((X) * 1000000UL)
#ifdef CONFIG_IMX8MQ
#include <asm/arch/clock_imx8mq.h>
#elif defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN)
#include <asm/arch/clock_imx8mm.h>
#else
#error "Error no clock.h"
#endif
#endif
arch/arm/include/asm/arch-imx8m/clock_imx8mm.h 0 → 100644
View file @ 8e809399
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018 NXP
*
* Peng Fan <peng.fan@nxp.com>
*/
#ifndef _ASM_ARCH_IMX8MM_CLOCK_H
#define _ASM_ARCH_IMX8MM_CLOCK_H
#include <linux/bitops.h>
/* Mainly for compatible to imx common code. */
enum mxc_clock {
MXC_ARM_CLK = 0,
MXC_IPG_CLK,
MXC_CSPI_CLK,
MXC_ESDHC_CLK,
MXC_ESDHC2_CLK,
MXC_ESDHC3_CLK,
MXC_I2C_CLK,
MXC_UART_CLK,
MXC_QSPI_CLK,
};
enum pll_clocks {
ANATOP_ARM_PLL,
ANATOP_VPU_PLL,
ANATOP_GPU_PLL,
ANATOP_SYSTEM_PLL1,
ANATOP_SYSTEM_PLL2,
ANATOP_SYSTEM_PLL3,
ANATOP_AUDIO_PLL1,
ANATOP_AUDIO_PLL2,
ANATOP_VIDEO_PLL,
ANATOP_DRAM_PLL,
};
enum clk_slice_type {
CORE_CLOCK_SLICE,
BUS_CLOCK_SLICE,
IP_CLOCK_SLICE,
AHB_CLOCK_SLICE,
IPG_CLOCK_SLICE,
CORE_SEL_CLOCK_SLICE,
DRAM_SEL_CLOCK_SLICE,
};
#ifdef CONFIG_IMX8MN
enum clk_root_index {
ARM_A53_CLK_ROOT = 0,
ARM_M7_CLK_ROOT = 1,
GPU_CORE_CLK_ROOT = 3,
GPU_SHADER_CLK_ROOT = 4,
MAIN_AXI_CLK_ROOT = 16,
ENET_AXI_CLK_ROOT = 17,
NAND_USDHC_BUS_CLK_ROOT = 18,
DISPLAY_AXI_CLK_ROOT = 20,
DISPLAY_APB_CLK_ROOT = 21,
USB_BUS_CLK_ROOT = 23,
GPU_AXI_CLK_ROOT = 24,
GPU_AHB_CLK_ROOT = 25,
NOC_CLK_ROOT = 26,
AHB_CLK_ROOT = 32,
IPG_CLK_ROOT = 33,
AUDIO_AHB_CLK_ROOT = 34,
DRAM_SEL_CFG = 48,
CORE_SEL_CFG = 49,
DRAM_ALT_CLK_ROOT = 64,
DRAM_APB_CLK_ROOT = 65,
DISPLAY_PIXEL_CLK_ROOT = 74,
SAI2_CLK_ROOT = 76,
SAI3_CLK_ROOT = 77,
SAI5_CLK_ROOT = 79,
SAI6_CLK_ROOT = 80,
SPDIF1_CLK_ROOT = 81,
ENET_REF_CLK_ROOT = 83,
ENET_TIMER_CLK_ROOT = 84,
ENET_PHY_REF_CLK_ROOT = 85,
NAND_CLK_ROOT = 86,
QSPI_CLK_ROOT = 87,
USDHC1_CLK_ROOT = 88,
USDHC2_CLK_ROOT = 89,
I2C1_CLK_ROOT = 90,
I2C2_CLK_ROOT = 91,
I2C3_CLK_ROOT = 92,
I2C4_CLK_ROOT = 93,
UART1_CLK_ROOT = 94,
UART2_CLK_ROOT = 95,
UART3_CLK_ROOT = 96,
UART4_CLK_ROOT = 97,
USB_CORE_REF_CLK_ROOT = 98,
USB_PHY_REF_CLK_ROOT = 99,
GIC_CLK_ROOT = 100,
ECSPI1_CLK_ROOT = 101,
ECSPI2_CLK_ROOT = 102,
PWM1_CLK_ROOT = 103,
PWM2_CLK_ROOT = 104,
PWM3_CLK_ROOT = 105,
PWM4_CLK_ROOT = 106,
GPT1_CLK_ROOT = 107,
GPT2_CLK_ROOT = 108,
GPT3_CLK_ROOT = 109,
GPT4_CLK_ROOT = 110,
GPT5_CLK_ROOT = 111,
GPT6_CLK_ROOT = 112,
TRACE_CLK_ROOT = 113,
WDOG_CLK_ROOT = 114,
WRCLK_CLK_ROOT = 115,
IPP_DO_CLKO1 = 116,
IPP_DO_CLKO2 = 117,
MIPI_DSI_CORE_CLK_ROOT = 118,
DISPLAY_DSI_PHY_REF_CLK_ROOT = 119,
MIPI_DSI_DBI_CLK_ROOT = 120,
USDHC3_CLK_ROOT = 121,
DISPLAY_CAMERA_PIXEL_CLK_ROOT = 122,
MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
MIPI_CSI2_ESC_CLK_ROOT = 127,
ECSPI3_CLK_ROOT = 131,
PDM_CLK_ROOT = 132,
SAI7_CLK_ROOT = 134,
CLK_ROOT_MAX,
};
#else
enum clk_root_index {
ARM_A53_CLK_ROOT = 0,
ARM_M4_CLK_ROOT = 1,
VPU_A53_CLK_ROOT = 2,
GPU3D_CLK_ROOT = 3,
GPU2D_CLK_ROOT = 4,
MAIN_AXI_CLK_ROOT = 16,
ENET_AXI_CLK_ROOT = 17,
NAND_USDHC_BUS_CLK_ROOT = 18,
VPU_BUS_CLK_ROOT = 19,
DISPLAY_AXI_CLK_ROOT = 20,
DISPLAY_APB_CLK_ROOT = 21,
DISPLAY_RTRM_CLK_ROOT = 22,
USB_BUS_CLK_ROOT = 23,
GPU_AXI_CLK_ROOT = 24,
GPU_AHB_CLK_ROOT = 25,
NOC_CLK_ROOT = 26,
NOC_APB_CLK_ROOT = 27,
AHB_CLK_ROOT = 32,
/* TODO: IPG Not sure */
IPG_CLK_ROOT = 33,
AUDIO_AHB_CLK_ROOT = 34,
MIPI_DSI_ESC_RX_CLK_ROOT = 36,
DRAM_SEL_CFG = 48,
CORE_SEL_CFG = 49,
DRAM_ALT_CLK_ROOT = 64,
DRAM_APB_CLK_ROOT = 65,
VPU_G1_CLK_ROOT = 66,
VPU_G2_CLK_ROOT = 67,
DISPLAY_DTRC_CLK_ROOT = 68,
DISPLAY_DC8000_CLK_ROOT = 69,
PCIE_CTRL_CLK_ROOT = 70,
PCIE_PHY_CLK_ROOT = 71,
PCIE_AUX_CLK_ROOT = 72,
DC_PIXEL_CLK_ROOT = 73,
LCDIF_PIXEL_CLK_ROOT = 74,
SAI1_CLK_ROOT = 75,
SAI2_CLK_ROOT = 76,
SAI3_CLK_ROOT = 77,
SAI4_CLK_ROOT = 78,
SAI5_CLK_ROOT = 79,
SAI6_CLK_ROOT = 80,
SPDIF1_CLK_ROOT = 81,
SPDIF2_CLK_ROOT = 82,
ENET_REF_CLK_ROOT = 83,
ENET_TIMER_CLK_ROOT = 84,
ENET_PHY_REF_CLK_ROOT = 85,
NAND_CLK_ROOT = 86,
QSPI_CLK_ROOT = 87,
USDHC1_CLK_ROOT = 88,
USDHC2_CLK_ROOT = 89,
I2C1_CLK_ROOT = 90,
I2C2_CLK_ROOT = 91,
I2C3_CLK_ROOT = 92,
I2C4_CLK_ROOT = 93,
UART1_CLK_ROOT = 94,
UART2_CLK_ROOT = 95,
UART3_CLK_ROOT = 96,
UART4_CLK_ROOT = 97,
USB_CORE_REF_CLK_ROOT = 98,
USB_PHY_REF_CLK_ROOT = 99,
GIC_CLK_ROOT = 100,
ECSPI1_CLK_ROOT = 101,
ECSPI2_CLK_ROOT = 102,
PWM1_CLK_ROOT = 103,
PWM2_CLK_ROOT = 104,
PWM3_CLK_ROOT = 105,
PWM4_CLK_ROOT = 106,
GPT1_CLK_ROOT = 107,
GPT2_CLK_ROOT = 108,
GPT3_CLK_ROOT = 109,
GPT4_CLK_ROOT = 110,
GPT5_CLK_ROOT = 111,
GPT6_CLK_ROOT = 112,
TRACE_CLK_ROOT = 113,
WDOG_CLK_ROOT = 114,
WRCLK_CLK_ROOT = 115,
IPP_DO_CLKO1 = 116,
IPP_DO_CLKO2 = 117,
MIPI_DSI_CORE_CLK_ROOT = 118,
MIPI_DSI_PHY_REF_CLK_ROOT = 119,
MIPI_DSI_DBI_CLK_ROOT = 120,
USDHC3_CLK_ROOT = 121,
MIPI_CSI1_CORE_CLK_ROOT = 122,
MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
MIPI_CSI1_ESC_CLK_ROOT = 124,
MIPI_CSI2_CORE_CLK_ROOT = 125,
MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
MIPI_CSI2_ESC_CLK_ROOT = 127,
PCIE2_CTRL_CLK_ROOT = 128,
PCIE2_PHY_CLK_ROOT = 129,
PCIE2_AUX_CLK_ROOT = 130,
ECSPI3_CLK_ROOT = 131,
PDM_CLK_ROOT = 132,
VPU_H1_CLK_ROOT = 133,
CLK_ROOT_MAX,
};
#endif
enum clk_root_src {
OSC_24M_CLK,
ARM_PLL_CLK,
DRAM_PLL1_CLK,
VIDEO_PLL2_CLK,
VPU_PLL_CLK,
GPU_PLL_CLK,
SYSTEM_PLL1_800M_CLK,
SYSTEM_PLL1_400M_CLK,
SYSTEM_PLL1_266M_CLK,
SYSTEM_PLL1_200M_CLK,
SYSTEM_PLL1_160M_CLK,
SYSTEM_PLL1_133M_CLK,
SYSTEM_PLL1_100M_CLK,
SYSTEM_PLL1_80M_CLK,
SYSTEM_PLL1_40M_CLK,
SYSTEM_PLL2_1000M_CLK,
SYSTEM_PLL2_500M_CLK,
SYSTEM_PLL2_333M_CLK,
SYSTEM_PLL2_250M_CLK,
SYSTEM_PLL2_200M_CLK,
SYSTEM_PLL2_166M_CLK,
SYSTEM_PLL2_125M_CLK,
SYSTEM_PLL2_100M_CLK,
SYSTEM_PLL2_50M_CLK,
SYSTEM_PLL3_CLK,
AUDIO_PLL1_CLK,
AUDIO_PLL2_CLK,
VIDEO_PLL_CLK,
OSC_32K_CLK,
EXT_CLK_1,
EXT_CLK_2,
EXT_CLK_3,
EXT_CLK_4,
OSC_HDMI_CLK
};
enum clk_ccgr_index {
CCGR_DVFS = 0,
CCGR_ANAMIX = 1,
CCGR_CPU = 2,
CCGR_CSU = 3,
CCGR_DEBUG = 4,
CCGR_DDR1 = 5,
CCGR_ECSPI1 = 7,
CCGR_ECSPI2 = 8,
CCGR_ECSPI3 = 9,
CCGR_ENET1 = 10,
CCGR_GPIO1 = 11,
CCGR_GPIO2 = 12,
CCGR_GPIO3 = 13,
CCGR_GPIO4 = 14,
CCGR_GPIO5 = 15,
CCGR_GPT1 = 16,
CCGR_GPT2 = 17,
CCGR_GPT3 = 18,
CCGR_GPT4 = 19,
CCGR_GPT5 = 20,
CCGR_GPT6 = 21,
CCGR_HS = 22,
CCGR_I2C1 = 23,
CCGR_I2C2 = 24,
CCGR_I2C3 = 25,
CCGR_I2C4 = 26,
CCGR_IOMUX = 27,
CCGR_IOMUX1 = 28,
CCGR_IOMUX2 = 29,
CCGR_IOMUX3 = 30,
CCGR_IOMUX4 = 31,
CCGR_SNVSMIX_IPG_CLK = 32,
CCGR_MU = 33,
CCGR_OCOTP = 34,
CCGR_OCRAM = 35,
CCGR_OCRAM_S = 36,
CCGR_PCIE = 37,
CCGR_PERFMON1 = 38,
CCGR_PERFMON2 = 39,
CCGR_PWM1 = 40,
CCGR_PWM2 = 41,
CCGR_PWM3 = 42,
CCGR_PWM4 = 43,
CCGR_QOS = 44,
CCGR_QOS_DISPMIX = 45,
CCGR_QOS_ETHENET = 46,
CCGR_QSPI = 47,
CCGR_RAWNAND = 48,
CCGR_RDC = 49,
CCGR_ROM = 50,
CCGR_SAI1 = 51,
CCGR_SAI2 = 52,
CCGR_SAI3 = 53,
CCGR_SAI4 = 54,
CCGR_SAI5 = 55,
CCGR_SAI6 = 56,
CCGR_SCTR = 57,
CCGR_SDMA1 = 58,
CCGR_SDMA2 = 59,
CCGR_SEC_DEBUG = 60,
CCGR_SEMA1 = 61,
CCGR_SEMA2 = 62,
CCGR_SIM_DISPLAY = 63,
CCGR_SIM_ENET = 64,
CCGR_SIM_M = 65,
CCGR_SIM_MAIN = 66,
CCGR_SIM_S = 67,
CCGR_SIM_WAKEUP = 68,
CCGR_SIM_HSIO = 69,
CCGR_SIM_VPU = 70,
CCGR_SNVS = 71,
CCGR_TRACE = 72,
CCGR_UART1 = 73,
CCGR_UART2 = 74,
CCGR_UART3 = 75,
CCGR_UART4 = 76,
CCGR_USB_MSCALE_PL301 = 77,
CCGR_GPU3D = 79,
CCGR_USDHC1 = 81,
CCGR_USDHC2 = 82,
CCGR_WDOG1 = 83,
CCGR_WDOG2 = 84,
CCGR_WDOG3 = 85,
CCGR_VPUG1 = 86,
CCGR_GPU_BUS = 87,
CCGR_VPUH1 = 89,
CCGR_VPUG2 = 90,
CCGR_PDM = 91,
CCGR_GIC = 92,
CCGR_DISPMIX = 93,
CCGR_USDHC3 = 94,
CCGR_SDMA3 = 95,
CCGR_XTAL = 96,
CCGR_PLL = 97,
CCGR_TEMP_SENSOR = 98,
CCGR_VPUMIX_BUS = 99,
CCGR_GPU2D = 102,
CCGR_MAX
};
enum clk_src_index {
CLK_SRC_CKIL_SYNC_REQ = 0,
CLK_SRC_ARM_PLL_EN = 1,
CLK_SRC_GPU_PLL_EN = 2,
CLK_SRC_VPU_PLL_EN = 3,
CLK_SRC_DRAM_PLL_EN = 4,
CLK_SRC_SYSTEM_PLL1_EN = 5,
CLK_SRC_SYSTEM_PLL2_EN = 6,
CLK_SRC_SYSTEM_PLL3_EN = 7,
CLK_SRC_AUDIO_PLL1_EN = 8,
CLK_SRC_AUDIO_PLL2_EN = 9,
CLK_SRC_VIDEO_PLL1_EN = 10,
CLK_SRC_RESERVED = 11,
CLK_SRC_ARM_PLL = 12,
CLK_SRC_GPU_PLL = 13,
CLK_SRC_VPU_PLL = 14,
CLK_SRC_DRAM_PLL = 15,
CLK_SRC_SYSTEM_PLL1_800M = 16,
CLK_SRC_SYSTEM_PLL1_400M = 17,
CLK_SRC_SYSTEM_PLL1_266M = 18,
CLK_SRC_SYSTEM_PLL1_200M = 19,
CLK_SRC_SYSTEM_PLL1_160M = 20,
CLK_SRC_SYSTEM_PLL1_133M = 21,
CLK_SRC_SYSTEM_PLL1_100M = 22,
CLK_SRC_SYSTEM_PLL1_80M = 23,
CLK_SRC_SYSTEM_PLL1_40M = 24,
CLK_SRC_SYSTEM_PLL2_1000M = 25,
CLK_SRC_SYSTEM_PLL2_500M = 26,
CLK_SRC_SYSTEM_PLL2_333M = 27,
CLK_SRC_SYSTEM_PLL2_250M = 28,
CLK_SRC_SYSTEM_PLL2_200M = 29,
CLK_SRC_SYSTEM_PLL2_166M = 30,
CLK_SRC_SYSTEM_PLL2_125M = 31,
CLK_SRC_SYSTEM_PLL2_100M = 32,
CLK_SRC_SYSTEM_PLL2_50M = 33,
CLK_SRC_SYSTEM_PLL3 = 34,
CLK_SRC_AUDIO_PLL1 = 35,
CLK_SRC_AUDIO_PLL2 = 36,
CLK_SRC_VIDEO_PLL1 = 37,
};
enum root_pre_div {
CLK_ROOT_PRE_DIV1 = 0,
CLK_ROOT_PRE_DIV2,
CLK_ROOT_PRE_DIV3,
CLK_ROOT_PRE_DIV4,
CLK_ROOT_PRE_DIV5,
CLK_ROOT_PRE_DIV6,
CLK_ROOT_PRE_DIV7,
CLK_ROOT_PRE_DIV8,
};
enum root_post_div {
CLK_ROOT_POST_DIV1 = 0,
CLK_ROOT_POST_DIV2,
CLK_ROOT_POST_DIV3,
CLK_ROOT_POST_DIV4,
CLK_ROOT_POST_DIV5,
CLK_ROOT_POST_DIV6,
CLK_ROOT_POST_DIV7,
CLK_ROOT_POST_DIV8,
CLK_ROOT_POST_DIV9,
CLK_ROOT_POST_DIV10,
CLK_ROOT_POST_DIV11,
CLK_ROOT_POST_DIV12,
CLK_ROOT_POST_DIV13,
CLK_ROOT_POST_DIV14,
CLK_ROOT_POST_DIV15,
CLK_ROOT_POST_DIV16,
CLK_ROOT_POST_DIV17,
CLK_ROOT_POST_DIV18,
CLK_ROOT_POST_DIV19,
CLK_ROOT_POST_DIV20,
CLK_ROOT_POST_DIV21,
CLK_ROOT_POST_DIV22,
CLK_ROOT_POST_DIV23,
CLK_ROOT_POST_DIV24,
CLK_ROOT_POST_DIV25,
CLK_ROOT_POST_DIV26,
CLK_ROOT_POST_DIV27,
CLK_ROOT_POST_DIV28,
CLK_ROOT_POST_DIV29,
CLK_ROOT_POST_DIV30,
CLK_ROOT_POST_DIV31,
CLK_ROOT_POST_DIV32,
CLK_ROOT_POST_DIV33,
CLK_ROOT_POST_DIV34,
CLK_ROOT_POST_DIV35,
CLK_ROOT_POST_DIV36,
CLK_ROOT_POST_DIV37,
CLK_ROOT_POST_DIV38,
CLK_ROOT_POST_DIV39,
CLK_ROOT_POST_DIV40,
CLK_ROOT_POST_DIV41,
CLK_ROOT_POST_DIV42,
CLK_ROOT_POST_DIV43,
CLK_ROOT_POST_DIV44,
CLK_ROOT_POST_DIV45,
CLK_ROOT_POST_DIV46,
CLK_ROOT_POST_DIV47,
CLK_ROOT_POST_DIV48,
CLK_ROOT_POST_DIV49,
CLK_ROOT_POST_DIV50,
CLK_ROOT_POST_DIV51,
CLK_ROOT_POST_DIV52,
CLK_ROOT_POST_DIV53,
CLK_ROOT_POST_DIV54,
CLK_ROOT_POST_DIV55,
CLK_ROOT_POST_DIV56,
CLK_ROOT_POST_DIV57,
CLK_ROOT_POST_DIV58,
CLK_ROOT_POST_DIV59,
CLK_ROOT_POST_DIV60,
CLK_ROOT_POST_DIV61,
CLK_ROOT_POST_DIV62,
CLK_ROOT_POST_DIV63,
CLK_ROOT_POST_DIV64,
};
struct clk_root_map {
enum clk_root_index entry;
enum clk_slice_type slice_type;
uint32_t slice_index;
uint8_t src_mux[8];
};
#define INTPLL_LOCK_MASK BIT(31)
#define INTPLL_LOCK_SEL_MASK BIT(29)
#define INTPLL_EXT_BYPASS_MASK BIT(28)
#define INTPLL_DIV20_CLKE_MASK BIT(27)
#define INTPLL_DIV20_CLKE_OVERRIDE_MASK BIT(26)
#define INTPLL_DIV10_CLKE_MASK BIT(25)
#define INTPLL_DIV10_CLKE_OVERRIDE_MASK BIT(24)
#define INTPLL_DIV8_CLKE_MASK BIT(23)
#define INTPLL_DIV8_CLKE_OVERRIDE_MASK BIT(22)
#define INTPLL_DIV6_CLKE_MASK BIT(21)
#define INTPLL_DIV6_CLKE_OVERRIDE_MASK BIT(20)
#define INTPLL_DIV5_CLKE_MASK BIT(19)
#define INTPLL_DIV5_CLKE_OVERRIDE_MASK BIT(18)
#define INTPLL_DIV4_CLKE_MASK BIT(17)
#define INTPLL_DIV4_CLKE_OVERRIDE_MASK BIT(16)
#define INTPLL_DIV3_CLKE_MASK BIT(15)
#define INTPLL_DIV3_CLKE_OVERRIDE_MASK BIT(14)
#define INTPLL_DIV2_CLKE_MASK BIT(13)
#define INTPLL_DIV2_CLKE_OVERRIDE_MASK BIT(12)
#define INTPLL_CLKE_MASK BIT(11)
#define INTPLL_CLKE_OVERRIDE_MASK BIT(10)
#define INTPLL_RST_MASK BIT(9)
#define INTPLL_RST_OVERRIDE_MASK BIT(8)
#define INTPLL_BYPASS_MASK BIT(4)
#define INTPLL_PAD_CLK_SEL_MASK GENMASK(3, 2)
#define INTPLL_REF_CLK_SEL_MASK GENMASK(1, 0)
#define INTPLL_MAIN_DIV_MASK GENMASK(21, 12)
#define INTPLL_MAIN_DIV_VAL(n) ((n << 12) & GENMASK(21, 12))
#define INTPLL_MAIN_DIV_SHIFT 12
#define INTPLL_PRE_DIV_MASK GENMASK(9, 4)
#define INTPLL_PRE_DIV_VAL(n) ((n << 4) & GENMASK(9, 4))
#define INTPLL_PRE_DIV_SHIFT 4
#define INTPLL_POST_DIV_MASK GENMASK(2, 0)
#define INTPLL_POST_DIV_VAL(n) ((n << 0) & GENMASK(2, 0))
#define INTPLL_POST_DIV_SHIFT 0
#define INTPLL_LOCK_CON_DLY_MASK GENMASK(5, 4)
#define INTPLL_LOCK_CON_DLY_SHIFT 4
#define INTPLL_LOCK_CON_OUT_MASK GENMASK(3, 2)
#define INTPLL_LOCK_CON_OUT_SHIFT 2
#define INTPLL_LOCK_CON_IN_MASK GENMASK(1, 0)
#define INTPLL_LOCK_CON_IN_SHIFT 0
#define INTPLL_LRD_EN_MASK BIT(21)
#define INTPLL_FOUT_MASK BIT(20)
#define INTPLL_AFC_SEL_MASK BIT(19)
#define INTPLL_PBIAS_CTRL_MASK BIT(18)
#define INTPLL_PBIAS_CTRL_EN_MASK BIT(17)
#define INTPLL_AFCINIT_SEL_MASK BIT(16)
#define INTPLL_FSEL_MASK BIT(14)
#define INTPLL_FEED_EN_MASK BIT(13)
#define INTPLL_EXTAFC_MASK GENMASK(7, 3)
#define INTPLL_AFC_EN_MASK BIT(2)
#define INTPLL_ICP_MASK GENMASK(1, 0)
struct ccm_ccgr {
u32 ccgr;
u32 ccgr_set;
u32 ccgr_clr;
u32 ccgr_tog;
};
struct ccm_root {
u32 target_root;
u32 target_root_set;
u32 target_root_clr;
u32 target_root_tog;
u32 misc;
u32 misc_set;
u32 misc_clr;
u32 misc_tog;
u32 nm_post;
u32 nm_post_root_set;
u32 nm_post_root_clr;
u32 nm_post_root_tog;
u32 nm_pre;
u32 nm_pre_root_set;
u32 nm_pre_root_clr;
u32 nm_pre_root_tog;
u32 db_post;
u32 db_post_root_set;
u32 db_post_root_clr;
u32 db_post_root_tog;
u32 db_pre;
u32 db_pre_root_set;
u32 db_pre_root_clr;
u32 db_pre_root_tog;
u32 reserved[4];
u32 access_ctrl;
u32 access_ctrl_root_set;
u32 access_ctrl_root_clr;
u32 access_ctrl_root_tog;
};
struct ccm_reg {
u32 reserved_0[4096];
struct ccm_ccgr ccgr_array[192];
u32 reserved_1[3328];
struct ccm_root core_root[5];
u32 reserved_2[352];
struct ccm_root bus_root[12];
u32 reserved_3[128];
struct ccm_root ahb_ipg_root[4];
u32 reserved_4[384];
struct ccm_root dram_sel;
struct ccm_root core_sel;
u32 reserved_5[448];
struct ccm_root ip_root[78];
};
#define CCGR_CLK_ON_MASK 0x03
#define CLK_SRC_ON_MASK 0x03
#define CLK_ROOT_ON BIT(28)
#define CLK_ROOT_OFF (0 << 28)
#define CLK_ROOT_ENABLE_MASK BIT(28)
#define CLK_ROOT_ENABLE_SHIFT 28
#define CLK_ROOT_SOURCE_SEL(n) (((n) & 0x7) << 24)
/* For SEL, only use 1 bit */
#define CLK_ROOT_SRC_MUX_MASK 0x07000000
#define CLK_ROOT_SRC_MUX_SHIFT 24
#define CLK_ROOT_SRC_0 0x00000000
#define CLK_ROOT_SRC_1 0x01000000
#define CLK_ROOT_SRC_2 0x02000000
#define CLK_ROOT_SRC_3 0x03000000
#define CLK_ROOT_SRC_4 0x04000000
#define CLK_ROOT_SRC_5 0x05000000
#define CLK_ROOT_SRC_6 0x06000000
#define CLK_ROOT_SRC_7 0x07000000
#define CLK_ROOT_PRE_DIV_MASK (0x00070000)
#define CLK_ROOT_PRE_DIV_SHIFT 16
#define CLK_ROOT_PRE_DIV(n) (((n) << 16) & 0x00070000)
#define CLK_ROOT_AUDO_SLOW_EN 0x1000
#define CLK_ROOT_AUDO_DIV_MASK 0x700
#define CLK_ROOT_AUDO_DIV_SHIFT 0x8
#define CLK_ROOT_AUDO_DIV(n) (((n) << 8) & 0x700)
/* For CORE: mask is 0x7; For IPG: mask is 0x3 */
#define CLK_ROOT_POST_DIV_MASK 0x3f
#define CLK_ROOT_CORE_POST_DIV_MASK 0x7
#define CLK_ROOT_IPG_POST_DIV_MASK 0x3
#define CLK_ROOT_POST_DIV_SHIFT 0
#define CLK_ROOT_POST_DIV(n) ((n) & 0x3f)
/* TODO check more */
#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000
#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000
#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x07000000
#define ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M 0x01000000
#define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000
enum enet_freq {
ENET_25MHZ = 0,
ENET_50MHZ,
ENET_125MHZ,
};
void dram_pll_init(ulong pll_val);
void dram_enable_bypass(ulong clk_val);
void dram_disable_bypass(void);
u32 imx_get_fecclk(void);
u32 imx_get_uartclk(void);
int clock_init(void);
void init_clk_usdhc(u32 index);
void init_uart_clk(u32 index);
void init_wdog_clk(void);
u32 mxc_get_clock(enum mxc_clock clk);
int clock_enable(enum clk_ccgr_index index, bool enable);
int clock_root_enabled(enum clk_root_index clock_id);
int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
enum root_post_div post_div, enum clk_root_src clock_src);
int clock_set_target_val(enum clk_root_index clock_id, u32 val);
int clock_get_target_val(enum clk_root_index clock_id, u32 *val);
int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div);
int clock_get_postdiv(enum clk_root_index clock_id,
enum root_post_div *post_div);
int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src);
void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq);
int set_clk_qspi(void);
void enable_ocotp_clk(unsigned char enable);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
#ifdef CONFIG_FEC_MXC
int set_clk_enet(enum enet_freq type);
#endif
void hab_caam_clock_enable(unsigned char enable);
void enable_usboh3_clk(unsigned char enable);
#endif
arch/arm/include/asm/arch-mx8m/clock.h → arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
View file @ 8e809399
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2017 NXP
* Copyright 2017-2018 NXP
*
* Peng Fan <peng.fan@nxp.com>
*/
#ifndef _ASM_ARCH_IMX8M_CLOCK_H
#define _ASM_ARCH_IMX8M_CLOCK_H
#ifndef _ASM_ARCH_IMX8M_CLOCK_IMX8MQ_H
#define _ASM_ARCH_IMX8M_CLOCK_IMX8MQ_H
#include <linux/bitops.h>
......@@ -405,8 +405,8 @@ enum root_post_div {
struct clk_root_map {
enum clk_root_index entry;
enum clk_slice_type slice_type;
u32 slice_index;
u8 src_mux[8];
uint32_t slice_index;
uint8_t src_mux[8];
};
struct ccm_ccgr {
......@@ -502,11 +502,44 @@ struct ccm_reg {
#define CLK_ROOT_POST_DIV_SHIFT 0
#define CLK_ROOT_POST_DIV(n) ((n) & 0x3f)
#define AUDIO_PLL1_CFG0_ADDR (0x30360000)
#define AUDIO_PLL1_CFG1_ADDR (0x30360004)
#define AUDIO_PLL2_CFG0_ADDR (0x30360008)
#define AUDIO_PLL2_CFG1_ADDR (0x3036000c)
#define VIDEO_PLL_CFG0 (0x30360010)
#define VIDEO_PLL_CFG1 (0x30360014)
#define GPU_PLL_CFG0 (0x30360018)
#define GPU_PLL_CFG1 (0x3036001c)
#define VPU_PLL_CFG0 (0x30360020)
#define VPU_PLL_CFG1 (0x30360024)
#define ARM_PLL_CFG0 (0x30360028)
#define ARM_PLL_CFG1 (0x3036002c)
#define SYS_PLL1_CFG0 (0x30360030)
#define SYS_PLL1_CFG1 (0x30360034)
#define SYS_PLL1_CFG2 (0x30360038)
#define SYS_PLL2_CFG0 (0x3036003c)
#define SYS_PLL2_CFG1 (0x30360040)
#define SYS_PLL2_CFG2 (0x30360044)
#define SYS_PLL3_CFG0 (0x30360048)
#define SYS_PLL3_CFG1 (0x3036004c)
#define SYS_PLL3_CFG2 (0x30360050)
#define VIDEO_PLL2_CFG0 (0x30360054)
#define VIDEO_PLL2_CFG1 (0x30360058)
#define VIDEO_PLL2_CFG2 (0x3036005c)
#define DRAM_PLL_CFG0 (0x30360060)
#define DRAM_PLL_CFG1 (0x30360064)
#define DRAM_PLL_CFG2 (0x30360068)
#define DIGPROG (0x3036006c)
#define OSC_MISC_CFG (0x30360070)
#define PLLOUT_MONITOR_CFG (0x30360074)
#define FRAC_PLLOUT_DIV_CFG (0x30360078)
#define SSCG_PLLOUT_DIV_CFG (0x3036007c)
/* AUDIO PLL1/2 VIDEO PLL1 GPU PLL VPU PLL ARM PLL*/
#define FRAC_PLL_LOCK_MASK BIT(31)
#define FRAC_PLL_CLKE_MASK BIT(21)
#define FRAC_PLL_PD_MASK BIT(19)
#define FRAC_PLL_REFCLK_SEL_MASK BIT(16)
#define FRAC_PLL_REFCLK_SEL_MASK (3 << 16)
#define FRAC_PLL_LOCK_SEL_MASK BIT(15)
#define FRAC_PLL_BYPASS_MASK BIT(14)
#define FRAC_PLL_COUNTCLK_SEL_MASK BIT(13)
......@@ -631,13 +664,9 @@ enum frac_pll_out_val {
FRAC_PLL_OUT_1600M,
};
enum sscg_pll_out_val {
SSCG_PLL_OUT_400M,
SSCG_PLL_OUT_600M,
SSCG_PLL_OUT_800M,
};
void dram_pll_init(enum sscg_pll_out_val pll_val);
void dram_pll_init(ulong pll_val);
void dram_enable_bypass(ulong clk_val);
void dram_disable_bypass(void);
u32 imx_get_fecclk(void);
u32 imx_get_uartclk(void);
int clock_init(void);
......@@ -655,9 +684,12 @@ int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div);
int clock_get_postdiv(enum clk_root_index clock_id,
enum root_post_div *post_div);
int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src);
void mxs_set_lcdclk(u32 base_addr, u32 freq);
void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq);
int set_clk_qspi(void);
void enable_ocotp_clk(unsigned char enable);
int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
#ifdef CONFIG_FEC_MXC
int set_clk_enet(enum enet_freq type);
#endif
void hab_caam_clock_enable(unsigned char enable);
#endif
arch/arm/include/asm/arch-mx8m/crm_regs.h → arch/arm/include/asm/arch-imx8m/crm_regs.h
View file @ 8e809399
......@@ -3,7 +3,7 @@
* Copyright 2017 NXP
*/
#ifndef _ASM_ARCH_MX8M_CRM_REGS_H
#define _ASM_ARCH_MX8M_CRM_REGS_H
#ifndef _ASM_ARCH_IMX8M_CRM_REGS_H
#define _ASM_ARCH_IMX8M_CRM_REGS_H
/* Dummy header, some imx-common code needs this file */
#endif
arch/arm/include/asm/arch-imx8m/ddr.h 0 → 100644
View file @ 8e809399
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2017 NXP
*/
#ifndef __ASM_ARCH_IMX8M_DDR_H
#define __ASM_ARCH_IMX8M_DDR_H
#include <asm/io.h>
#include <asm/types.h>
#include <asm/arch/ddr.h>
#define DDRC_DDR_SS_GPR0 0x3d000000
#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000))
#define DDRPHY_MEM(X) (0x3c000000 + (X * 0x2000000) + 0x50000)
struct ddrc_freq {
u32 res0[8];
u32 derateen;
u32 derateint;
u32 res1[10];
u32 rfshctl0;
u32 res2[4];
u32 rfshtmg;
u32 rfshtmg1;
u32 res3[28];
u32 init3;
u32 init4;
u32 res;
u32 init6;
u32 init7;
u32 res4[4];
u32 dramtmg0;
u32 dramtmg1;
u32 dramtmg2;
u32 dramtmg3;
u32 dramtmg4;
u32 dramtmg5;
u32 dramtmg6;
u32 dramtmg7;
u32 dramtmg8;
u32 dramtmg9;
u32 dramtmg10;
u32 dramtmg11;
u32 dramtmg12;
u32 dramtmg13;
u32 dramtmg14;
u32 dramtmg15;
u32 dramtmg16;
u32 dramtmg17;
u32 res5[10];
u32 mramtmg0;
u32 mramtmg1;
u32 mramtmg4;
u32 mramtmg9;
u32 zqctl0;
u32 res6[3];
u32 dfitmg0;
u32 dfitmg1;
u32 res7[7];
u32 dfitmg2;
u32 dfitmg3;
u32 res8[33];
u32 odtcfg;
};
struct imx8m_ddrc_regs {
u32 mstr;
u32 stat;
u32 mstr1;
u32 res1;
u32 mrctrl0;
u32 mrctrl1;
u32 mrstat;
u32 mrctrl2;
u32 derateen;
u32 derateint;
u32 mstr2;
u32 res2;
u32 pwrctl;
u32 pwrtmg;
u32 hwlpctl;
u32 hwffcctl;
u32 hwffcstat;
u32 res3[3];
u32 rfshctl0;
u32 rfshctl1;
u32 rfshctl2;
u32 rfshctl4;
u32 rfshctl3;
u32 rfshtmg;
u32 rfshtmg1;
u32 res4;
u32 ecccfg0;
u32 ecccfg1;
u32 eccstat;
u32 eccclr;
u32 eccerrcnt;
u32 ecccaddr0;
u32 ecccaddr1;
u32 ecccsyn0;
u32 ecccsyn1;
u32 ecccsyn2;
u32 eccbitmask0;
u32 eccbitmask1;
u32 eccbitmask2;
u32 eccuaddr0;
u32 eccuaddr1;
u32 eccusyn0;
u32 eccusyn1;
u32 eccusyn2;
u32 eccpoisonaddr0;
u32 eccpoisonaddr1;
u32 crcparctl0;
u32 crcparctl1;
u32 crcparctl2;
u32 crcparstat;
u32 init0;
u32 init1;
u32 init2;
u32 init3;
u32 init4;
u32 init5;
u32 init6;
u32 init7;
u32 dimmctl;
u32 rankctl;
u32 res5;
u32 chctl;
u32 dramtmg0;
u32 dramtmg1;
u32 dramtmg2;
u32 dramtmg3;
u32 dramtmg4;
u32 dramtmg5;
u32 dramtmg6;
u32 dramtmg7;
u32 dramtmg8;
u32 dramtmg9;
u32 dramtmg10;
u32 dramtmg11;
u32 dramtmg12;
u32 dramtmg13;
u32 dramtmg14;
u32 dramtmg15;
u32 dramtmg16;
u32 dramtmg17;
u32 res6[10];
u32 mramtmg0;
u32 mramtmg1;
u32 mramtmg4;
u32 mramtmg9;
u32 zqctl0;
u32 zqctl1;
u32 zqctl2;
u32 zqstat;
u32 dfitmg0;
u32 dfitmg1;
u32 dfilpcfg0;
u32 dfilpcfg1;
u32 dfiupd0;
u32 dfiupd1;
u32 dfiupd2;
u32 res7;
u32 dfimisc;
u32 dfitmg2;
u32 dfitmg3;
u32 dfistat;
u32 dbictl;
u32 dfiphymstr;
u32 res8[14];
u32 addrmap0;
u32 addrmap1;
u32 addrmap2;
u32 addrmap3;
u32 addrmap4;
u32 addrmap5;
u32 addrmap6;
u32 addrmap7;
u32 addrmap8;
u32 addrmap9;
u32 addrmap10;
u32 addrmap11;
u32 res9[4];
u32 odtcfg;
u32 odtmap;
u32 res10[2];
u32 sched;
u32 sched1;
u32 sched2;
u32 perfhpr1;
u32 res11;
u32 perflpr1;
u32 res12;
u32 perfwr1;
u32 res13[4];
u32 dqmap0;
u32 dqmap1;
u32 dqmap2;
u32 dqmap3;
u32 dqmap4;
u32 dqmap5;
u32 res14[26];
u32 dbg0;
u32 dbg1;
u32 dbgcam;
u32 dbgcmd;
u32 dbgstat;
u32 res15[3];
u32 swctl;
u32 swstat;
u32 res16[2];
u32 ocparcfg0;
u32 ocparcfg1;
u32 ocparcfg2;
u32 ocparcfg3;
u32 ocparstat0;
u32 ocparstat1;
u32 ocparwlog0;
u32 ocparwlog1;
u32 ocparwlog2;
u32 ocparawlog0;
u32 ocparawlog1;
u32 ocparrlog0;
u32 ocparrlog1;
u32 ocpararlog0;
u32 ocpararlog1;
u32 poisoncfg;
u32 poisonstat;
u32 adveccindex;
union {
u32 adveccstat;
u32 eccapstat;
};
u32 eccpoisonpat0;
u32 eccpoisonpat1;
u32 eccpoisonpat2;
u32 res17[6];
u32 caparpoisonctl;
u32 caparpoisonstat;
u32 res18[2];
u32 dynbsmstat;
u32 res19[18];
u32 pstat;
u32 pccfg;
struct {
u32 pcfgr;
u32 pcfgw;
u32 pcfgc;
struct {
u32 pcfgidmaskch0;
u32 pcfidvaluech0;
} pcfgid[16];
u32 pctrl;
u32 pcfgqos0;
u32 pcfgqos1;
u32 pcfgwqos0;
u32 pcfgwqos1;
u32 res[4];
} pcfg[16];
struct {
u32 sarbase;
u32 sarsize;
} sar[4];
u32 sbrctl;
u32 sbrstat;
u32 sbrwdata0;
u32 sbrwdata1;
u32 pdch;
u32 res20[755];
/* umctl2_regs_dch1 */
u32 ch1_stat;
u32 res21[2];
u32 ch1_mrctrl0;
u32 ch1_mrctrl1;
u32 ch1_mrstat;
u32 ch1_mrctrl2;
u32 res22[4];
u32 ch1_pwrctl;
u32 ch1_pwrtmg;
u32 ch1_hwlpctl;
u32 res23[15];
u32 ch1_eccstat;
u32 ch1_eccclr;
u32 ch1_eccerrcnt;
u32 ch1_ecccaddr0;
u32 ch1_ecccaddr1;
u32 ch1_ecccsyn0;
u32 ch1_ecccsyn1;
u32 ch1_ecccsyn2;
u32 ch1_eccbitmask0;
u32 ch1_eccbitmask1;
u32 ch1_eccbitmask2;
u32 ch1_eccuaddr0;
u32 ch1_eccuaddr1;
u32 ch1_eccusyn0;
u32 ch1_eccusyn1;
u32 ch1_eccusyn2;
u32 res24[2];
u32 ch1_crcparctl0;
u32 res25[2];
u32 ch1_crcparstat;
u32 res26[46];
u32 ch1_zqctl2;
u32 ch1_zqstat;
u32 res27[11];
u32 ch1_dfistat;
u32 res28[33];
u32 ch1_odtmap;
u32 res29[47];
u32 ch1_dbg1;
u32 ch1_dbgcam;
u32 ch1_dbgcmd;
u32 ch1_dbgstat;
u32 res30[123];
/* umctl2_regs_freq1 */
struct ddrc_freq freq1;
u32 res31[109];
/* umctl2_regs_addrmap_alt */
u32 addrmap0_alt;
u32 addrmap1_alt;
u32 addrmap2_alt;
u32 addrmap3_alt;
u32 addrmap4_alt;
u32 addrmap5_alt;
u32 addrmap6_alt;
u32 addrmap7_alt;
u32 addrmap8_alt;
u32 addrmap9_alt;
u32 addrmap10_alt;
u32 addrmap11_alt;
u32 res32[758];
/* umctl2_regs_freq2 */
struct ddrc_freq freq2;
u32 res33[879];
/* umctl2_regs_freq3 */
struct ddrc_freq freq3;
};
struct imx8m_ddrphy_regs {
u32 reg[0xf0000];
};
/* PHY State */
enum pstate {
PS0,
PS1,
PS2,
PS3,
};
enum msg_response {
TRAIN_SUCCESS = 0x7,
TRAIN_STREAM_START = 0x8,
TRAIN_FAIL = 0xff,
};
#define DDRC_MSTR_0 0x3d400000
#define DDRC_STAT_0 0x3d400004
#define DDRC_MSTR1_0 0x3d400008
#define DDRC_MRCTRL0_0 0x3d400010
#define DDRC_MRCTRL1_0 0x3d400014
#define DDRC_MRSTAT_0 0x3d400018
#define DDRC_MRCTRL2_0 0x3d40001c
#define DDRC_DERATEEN_0 0x3d400020
#define DDRC_DERATEINT_0 0x3d400024
#define DDRC_MSTR2_0 0x3d400028
#define DDRC_PWRCTL_0 0x3d400030
#define DDRC_PWRTMG_0 0x3d400034
#define DDRC_HWLPCTL_0 0x3d400038
#define DDRC_HWFFCCTL_0 0x3d40003c
#define DDRC_HWFFCSTAT_0 0x3d400040
#define DDRC_RFSHCTL0_0 0x3d400050
#define DDRC_RFSHCTL1_0 0x3d400054
#define DDRC_RFSHCTL2_0 0x3d400058
#define DDRC_RFSHCTL3_0 0x3d400060
#define DDRC_RFSHTMG_0 0x3d400064
#define DDRC_ECCCFG0_0 0x3d400070
#define DDRC_ECCCFG1_0 0x3d400074
#define DDRC_ECCSTAT_0 0x3d400078
#define DDRC_ECCCLR_0 0x3d40007c
#define DDRC_ECCERRCNT_0 0x3d400080
#define DDRC_ECCCADDR0_0 0x3d400084
#define DDRC_ECCCADDR1_0 0x3d400088
#define DDRC_ECCCSYN0_0 0x3d40008c
#define DDRC_ECCCSYN1_0 0x3d400090
#define DDRC_ECCCSYN2_0 0x3d400094
#define DDRC_ECCBITMASK0_0 0x3d400098
#define DDRC_ECCBITMASK1_0 0x3d40009c
#define DDRC_ECCBITMASK2_0 0x3d4000a0
#define DDRC_ECCUADDR0_0 0x3d4000a4
#define DDRC_ECCUADDR1_0 0x3d4000a8
#define DDRC_ECCUSYN0_0 0x3d4000ac
#define DDRC_ECCUSYN1_0 0x3d4000b0
#define DDRC_ECCUSYN2_0 0x3d4000b4
#define DDRC_ECCPOISONADDR0_0 0x3d4000b8
#define DDRC_ECCPOISONADDR1_0 0x3d4000bc
#define DDRC_CRCPARCTL0_0 0x3d4000c0
#define DDRC_CRCPARCTL1_0 0x3d4000c4
#define DDRC_CRCPARCTL2_0 0x3d4000c8
#define DDRC_CRCPARSTAT_0 0x3d4000cc
#define DDRC_INIT0_0 0x3d4000d0
#define DDRC_INIT1_0 0x3d4000d4
#define DDRC_INIT2_0 0x3d4000d8
#define DDRC_INIT3_0 0x3d4000dc
#define DDRC_INIT4_0 0x3d4000e0
#define DDRC_INIT5_0 0x3d4000e4
#define DDRC_INIT6_0 0x3d4000e8
#define DDRC_INIT7_0 0x3d4000ec
#define DDRC_DIMMCTL_0 0x3d4000f0
#define DDRC_RANKCTL_0 0x3d4000f4
#define DDRC_DRAMTMG0_0 0x3d400100
#define DDRC_DRAMTMG1_0 0x3d400104
#define DDRC_DRAMTMG2_0 0x3d400108
#define DDRC_DRAMTMG3_0 0x3d40010c
#define DDRC_DRAMTMG4_0 0x3d400110
#define DDRC_DRAMTMG5_0 0x3d400114
#define DDRC_DRAMTMG6_0 0x3d400118
#define DDRC_DRAMTMG7_0 0x3d40011c
#define DDRC_DRAMTMG8_0 0x3d400120
#define DDRC_DRAMTMG9_0 0x3d400124
#define DDRC_DRAMTMG10_0 0x3d400128
#define DDRC_DRAMTMG11_0 0x3d40012c
#define DDRC_DRAMTMG12_0 0x3d400130
#define DDRC_DRAMTMG13_0 0x3d400134
#define DDRC_DRAMTMG14_0 0x3d400138
#define DDRC_DRAMTMG15_0 0x3d40013C
#define DDRC_DRAMTMG16_0 0x3d400140
#define DDRC_DRAMTMG17_0 0x3d400144
#define DDRC_ZQCTL0_0 0x3d400180
#define DDRC_ZQCTL1_0 0x3d400184
#define DDRC_ZQCTL2_0 0x3d400188
#define DDRC_ZQSTAT_0 0x3d40018c
#define DDRC_DFITMG0_0 0x3d400190
#define DDRC_DFITMG1_0 0x3d400194
#define DDRC_DFILPCFG0_0 0x3d400198
#define DDRC_DFILPCFG1_0 0x3d40019c
#define DDRC_DFIUPD0_0 0x3d4001a0
#define DDRC_DFIUPD1_0 0x3d4001a4
#define DDRC_DFIUPD2_0 0x3d4001a8
#define DDRC_DFIMISC_0 0x3d4001b0
#define DDRC_DFITMG2_0 0x3d4001b4
#define DDRC_DFITMG3_0 0x3d4001b8
#define DDRC_DFISTAT_0 0x3d4001bc
#define DDRC_DBICTL_0 0x3d4001c0
#define DDRC_DFIPHYMSTR_0 0x3d4001c4
#define DDRC_TRAINCTL0_0 0x3d4001d0
#define DDRC_TRAINCTL1_0 0x3d4001d4
#define DDRC_TRAINCTL2_0 0x3d4001d8
#define DDRC_TRAINSTAT_0 0x3d4001dc
#define DDRC_ADDRMAP0_0 0x3d400200
#define DDRC_ADDRMAP1_0 0x3d400204
#define DDRC_ADDRMAP2_0 0x3d400208
#define DDRC_ADDRMAP3_0 0x3d40020c
#define DDRC_ADDRMAP4_0 0x3d400210
#define DDRC_ADDRMAP5_0 0x3d400214
#define DDRC_ADDRMAP6_0 0x3d400218
#define DDRC_ADDRMAP7_0 0x3d40021c
#define DDRC_ADDRMAP8_0 0x3d400220
#define DDRC_ADDRMAP9_0 0x3d400224
#define DDRC_ADDRMAP10_0 0x3d400228
#define DDRC_ADDRMAP11_0 0x3d40022c
#define DDRC_ODTCFG_0 0x3d400240
#define DDRC_ODTMAP_0 0x3d400244
#define DDRC_SCHED_0 0x3d400250
#define DDRC_SCHED1_0 0x3d400254
#define DDRC_PERFHPR1_0 0x3d40025c
#define DDRC_PERFLPR1_0 0x3d400264
#define DDRC_PERFWR1_0 0x3d40026c
#define DDRC_PERFVPR1_0 0x3d400274
#define DDRC_PERFVPW1_0 0x3d400278
#define DDRC_DQMAP0_0 0x3d400280
#define DDRC_DQMAP1_0 0x3d400284
#define DDRC_DQMAP2_0 0x3d400288
#define DDRC_DQMAP3_0 0x3d40028c
#define DDRC_DQMAP4_0 0x3d400290
#define DDRC_DQMAP5_0 0x3d400294
#define DDRC_DBG0_0 0x3d400300
#define DDRC_DBG1_0 0x3d400304
#define DDRC_DBGCAM_0 0x3d400308
#define DDRC_DBGCMD_0 0x3d40030c
#define DDRC_DBGSTAT_0 0x3d400310
#define DDRC_SWCTL_0 0x3d400320
#define DDRC_SWSTAT_0 0x3d400324
#define DDRC_OCPARCFG0_0 0x3d400330
#define DDRC_OCPARCFG1_0 0x3d400334
#define DDRC_OCPARCFG2_0 0x3d400338
#define DDRC_OCPARCFG3_0 0x3d40033c
#define DDRC_OCPARSTAT0_0 0x3d400340
#define DDRC_OCPARSTAT1_0 0x3d400344
#define DDRC_OCPARWLOG0_0 0x3d400348
#define DDRC_OCPARWLOG1_0 0x3d40034c
#define DDRC_OCPARWLOG2_0 0x3d400350
#define DDRC_OCPARAWLOG0_0 0x3d400354
#define DDRC_OCPARAWLOG1_0 0x3d400358
#define DDRC_OCPARRLOG0_0 0x3d40035c
#define DDRC_OCPARRLOG1_0 0x3d400360
#define DDRC_OCPARARLOG0_0 0x3d400364
#define DDRC_OCPARARLOG1_0 0x3d400368
#define DDRC_POISONCFG_0 0x3d40036C
#define DDRC_POISONSTAT_0 0x3d400370
#define DDRC_ADVECCINDEX_0 0x3d400003
#define DDRC_ADVECCSTAT_0 0x3d400003
#define DDRC_ECCPOISONPAT0_0 0x3d400003
#define DDRC_ECCPOISONPAT1_0 0x3d400003
#define DDRC_ECCPOISONPAT2_0 0x3d400003
#define DDRC_HIFCTL_0 0x3d400003
#define DDRC_PSTAT_0 0x3d4003fc
#define DDRC_PCCFG_0 0x3d400400
#define DDRC_PCFGR_0_0 0x3d400404
#define DDRC_PCFGR_1_0 0x3d4004b4
#define DDRC_PCFGR_2_0 0x3d400564
#define DDRC_PCFGR_3_0 0x3d400614
#define DDRC_PCFGW_0_0 0x3d400408
#define DDRC_PCFGW_1_0 0x3d400408
#define DDRC_PCFGW_2_0 0x3d400568
#define DDRC_PCFGW_3_0 0x3d400618
#define DDRC_PCFGC_0_0 0x3d40040c
#define DDRC_PCFGIDMASKCH_0 0x3d400410
#define DDRC_PCFGIDVALUECH_0 0x3d400414
#define DDRC_PCTRL_0_0 0x3d400490
#define DDRC_PCTRL_1_0 0x3d400540
#define DDRC_PCTRL_2_0 0x3d4005f0
#define DDRC_PCTRL_3_0 0x3d4006a0
#define DDRC_PCFGQOS0_0_0 0x3d400494
#define DDRC_PCFGQOS1_0_0 0x3d400498
#define DDRC_PCFGWQOS0_0_0 0x3d40049c
#define DDRC_PCFGWQOS1_0_0 0x3d4004a0
#define DDRC_SARBASE0_0 0x3d400f04
#define DDRC_SARSIZE0_0 0x3d400f08
#define DDRC_SBRCTL_0 0x3d400f24
#define DDRC_SBRSTAT_0 0x3d400f28
#define DDRC_SBRWDATA0_0 0x3d400f2c
#define DDRC_SBRWDATA1_0 0x3d400f30
#define DDRC_PDCH_0 0x3d400f34
/**********************/
#define DDRC_MSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x00)
#define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04)
#define DDRC_MSTR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x08)
#define DDRC_MRCTRL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x10)
#define DDRC_MRCTRL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x14)
#define DDRC_MRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18)
#define DDRC_MRCTRL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c)
#define DDRC_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x20)
#define DDRC_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x24)
#define DDRC_MSTR2(X) (DDRC_IPS_BASE_ADDR(X) + 0x28)
#define DDRC_PWRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x30)
#define DDRC_PWRTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x34)
#define DDRC_HWLPCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x38)
#define DDRC_HWFFCCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x3c)
#define DDRC_HWFFCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x40)
#define DDRC_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x50)
#define DDRC_RFSHCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x54)
#define DDRC_RFSHCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x58)
#define DDRC_RFSHCTL3(X) (DDRC_IPS_BASE_ADDR(X) + 0x60)
#define DDRC_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x64)
#define DDRC_ECCCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x70)
#define DDRC_ECCCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x74)
#define DDRC_ECCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x78)
#define DDRC_ECCCLR(X) (DDRC_IPS_BASE_ADDR(X) + 0x7c)
#define DDRC_ECCERRCNT(X) (DDRC_IPS_BASE_ADDR(X) + 0x80)
#define DDRC_ECCCADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0x84)
#define DDRC_ECCCADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x88)
#define DDRC_ECCCSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0x8c)
#define DDRC_ECCCSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0x90)
#define DDRC_ECCCSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0x94)
#define DDRC_ECCBITMASK0(X) (DDRC_IPS_BASE_ADDR(X) + 0x98)
#define DDRC_ECCBITMASK1(X) (DDRC_IPS_BASE_ADDR(X) + 0x9c)
#define DDRC_ECCBITMASK2(X) (DDRC_IPS_BASE_ADDR(X) + 0xa0)
#define DDRC_ECCUADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xa4)
#define DDRC_ECCUADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xa8)
#define DDRC_ECCUSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0xac)
#define DDRC_ECCUSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0xb0)
#define DDRC_ECCUSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0xb4)
#define DDRC_ECCPOISONADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xb8)
#define DDRC_ECCPOISONADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xbc)
#define DDRC_CRCPARCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0xc0)
#define DDRC_CRCPARCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0xc4)
#define DDRC_CRCPARCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0xc8)
#define DDRC_CRCPARSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xcc)
#define DDRC_INIT0(X) (DDRC_IPS_BASE_ADDR(X) + 0xd0)
#define DDRC_INIT1(X) (DDRC_IPS_BASE_ADDR(X) + 0xd4)
#define DDRC_INIT2(X) (DDRC_IPS_BASE_ADDR(X) + 0xd8)
#define DDRC_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0xdc)
#define DDRC_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0xe0)
#define DDRC_INIT5(X) (DDRC_IPS_BASE_ADDR(X) + 0xe4)
#define DDRC_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0xe8)
#define DDRC_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0xec)
#define DDRC_DIMMCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf0)
#define DDRC_RANKCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf4)
#define DDRC_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x100)
#define DDRC_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x104)
#define DDRC_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x108)
#define DDRC_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x10c)
#define DDRC_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x110)
#define DDRC_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x114)
#define DDRC_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x118)
#define DDRC_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x11c)
#define DDRC_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x120)
#define DDRC_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x124)
#define DDRC_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x128)
#define DDRC_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x12c)
#define DDRC_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x130)
#define DDRC_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x134)
#define DDRC_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x138)
#define DDRC_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x13C)
#define DDRC_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x140)
#define DDRC_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x144)
#define DDRC_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x180)
#define DDRC_ZQCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x184)
#define DDRC_ZQCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x188)
#define DDRC_ZQSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18c)
#define DDRC_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x190)
#define DDRC_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x194)
#define DDRC_DFILPCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x198)
#define DDRC_DFILPCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x19c)
#define DDRC_DFIUPD0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a0)
#define DDRC_DFIUPD1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a4)
#define DDRC_DFIUPD2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a8)
#define DDRC_DFIMISC(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b0)
#define DDRC_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b4)
#define DDRC_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b8)
#define DDRC_DFISTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1bc)
#define DDRC_DBICTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c0)
#define DDRC_DFIPHYMSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c4)
#define DDRC_TRAINCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d0)
#define DDRC_TRAINCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d4)
#define DDRC_TRAINCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d8)
#define DDRC_TRAINSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1dc)
#define DDRC_ADDRMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x200)
#define DDRC_ADDRMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x204)
#define DDRC_ADDRMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x208)
#define DDRC_ADDRMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20c)
#define DDRC_ADDRMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x210)
#define DDRC_ADDRMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x214)
#define DDRC_ADDRMAP6(X) (DDRC_IPS_BASE_ADDR(X) + 0x218)
#define DDRC_ADDRMAP7(X) (DDRC_IPS_BASE_ADDR(X) + 0x21c)
#define DDRC_ADDRMAP8(X) (DDRC_IPS_BASE_ADDR(X) + 0x220)
#define DDRC_ADDRMAP9(X) (DDRC_IPS_BASE_ADDR(X) + 0x224)
#define DDRC_ADDRMAP10(X) (DDRC_IPS_BASE_ADDR(X) + 0x228)
#define DDRC_ADDRMAP11(X) (DDRC_IPS_BASE_ADDR(X) + 0x22c)
#define DDRC_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x240)
#define DDRC_ODTMAP(X) (DDRC_IPS_BASE_ADDR(X) + 0x244)
#define DDRC_SCHED(X) (DDRC_IPS_BASE_ADDR(X) + 0x250)
#define DDRC_SCHED1(X) (DDRC_IPS_BASE_ADDR(X) + 0x254)
#define DDRC_PERFHPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x25c)
#define DDRC_PERFLPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x264)
#define DDRC_PERFWR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x26c)
#define DDRC_PERFVPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x274)
#define DDRC_PERFVPW1(X) (DDRC_IPS_BASE_ADDR(X) + 0x278)
#define DDRC_DQMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x280)
#define DDRC_DQMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x284)
#define DDRC_DQMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x288)
#define DDRC_DQMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x28c)
#define DDRC_DQMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x290)
#define DDRC_DQMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x294)
#define DDRC_DBG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x300)
#define DDRC_DBG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x304)
#define DDRC_DBGCAM(X) (DDRC_IPS_BASE_ADDR(X) + 0x308)
#define DDRC_DBGCMD(X) (DDRC_IPS_BASE_ADDR(X) + 0x30c)
#define DDRC_DBGSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x310)
#define DDRC_SWCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x320)
#define DDRC_SWSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x324)
#define DDRC_OCPARCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x330)
#define DDRC_OCPARCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x334)
#define DDRC_OCPARCFG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x338)
#define DDRC_OCPARCFG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x33c)
#define DDRC_OCPARSTAT0(X) (DDRC_IPS_BASE_ADDR(X) + 0x340)
#define DDRC_OCPARSTAT1(X) (DDRC_IPS_BASE_ADDR(X) + 0x344)
#define DDRC_OCPARWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x348)
#define DDRC_OCPARWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x34c)
#define DDRC_OCPARWLOG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x350)
#define DDRC_OCPARAWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x354)
#define DDRC_OCPARAWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x358)
#define DDRC_OCPARRLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x35c)
#define DDRC_OCPARRLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x360)
#define DDRC_OCPARARLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x364)
#define DDRC_OCPARARLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x368)
#define DDRC_POISONCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x36C)
#define DDRC_POISONSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x370)
#define DDRC_PSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3fc)
#define DDRC_PCCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x400)
#define DDRC_PCFGR_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x404)
#define DDRC_PCFGR_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x404)
#define DDRC_PCFGR_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x404)
#define DDRC_PCFGR_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x404)
#define DDRC_PCFGW_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x408)
#define DDRC_PCFGW_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x408)
#define DDRC_PCFGW_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x408)
#define DDRC_PCFGW_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x408)
#define DDRC_PCFGC_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x40c)
#define DDRC_PCFGIDMASKCH(X) (DDRC_IPS_BASE_ADDR(X) + 0x410)
#define DDRC_PCFGIDVALUECH(X) (DDRC_IPS_BASE_ADDR(X) + 0x414)
#define DDRC_PCTRL_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x490)
#define DDRC_PCTRL_1(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 1 * 0xb0)
#define DDRC_PCTRL_2(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 2 * 0xb0)
#define DDRC_PCTRL_3(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 3 * 0xb0)
#define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494)
#define DDRC_PCFGQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x498)
#define DDRC_PCFGWQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x49c)
#define DDRC_PCFGWQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4a0)
#define DDRC_SARBASE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf04)
#define DDRC_SARSIZE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf08)
#define DDRC_SBRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf24)
#define DDRC_SBRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xf28)
#define DDRC_SBRWDATA0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf2c)
#define DDRC_SBRWDATA1(X) (DDRC_IPS_BASE_ADDR(X) + 0xf30)
#define DDRC_PDCH(X) (DDRC_IPS_BASE_ADDR(X) + 0xf34)
#define DDRC_FREQ1_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x2020)
#define DDRC_FREQ1_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x2024)
#define DDRC_FREQ1_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2050)
#define DDRC_FREQ1_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2064)
#define DDRC_FREQ1_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20dc)
#define DDRC_FREQ1_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e0)
#define DDRC_FREQ1_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e8)
#define DDRC_FREQ1_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x20ec)
#define DDRC_FREQ1_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2100)
#define DDRC_FREQ1_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2104)
#define DDRC_FREQ1_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x2108)
#define DDRC_FREQ1_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x210c)
#define DDRC_FREQ1_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x2110)
#define DDRC_FREQ1_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x2114)
#define DDRC_FREQ1_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x2118)
#define DDRC_FREQ1_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x211c)
#define DDRC_FREQ1_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x2120)
#define DDRC_FREQ1_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x2124)
#define DDRC_FREQ1_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x2128)
#define DDRC_FREQ1_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x212c)
#define DDRC_FREQ1_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x2130)
#define DDRC_FREQ1_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x2134)
#define DDRC_FREQ1_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x2138)
#define DDRC_FREQ1_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x213C)
#define DDRC_FREQ1_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x2140)
#define DDRC_FREQ1_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x2144)
#define DDRC_FREQ1_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2180)
#define DDRC_FREQ1_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190)
#define DDRC_FREQ1_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194)
#define DDRC_FREQ1_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4)
#define DDRC_FREQ1_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8)
#define DDRC_FREQ1_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240)
#define DDRC_FREQ2_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x3020)
#define DDRC_FREQ2_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3024)
#define DDRC_FREQ2_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3050)
#define DDRC_FREQ2_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3064)
#define DDRC_FREQ2_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x30dc)
#define DDRC_FREQ2_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e0)
#define DDRC_FREQ2_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e8)
#define DDRC_FREQ2_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x30ec)
#define DDRC_FREQ2_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3100)
#define DDRC_FREQ2_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3104)
#define DDRC_FREQ2_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x3108)
#define DDRC_FREQ2_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x310c)
#define DDRC_FREQ2_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x3110)
#define DDRC_FREQ2_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x3114)
#define DDRC_FREQ2_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x3118)
#define DDRC_FREQ2_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x311c)
#define DDRC_FREQ2_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x3120)
#define DDRC_FREQ2_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x3124)
#define DDRC_FREQ2_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x3128)
#define DDRC_FREQ2_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x312c)
#define DDRC_FREQ2_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x3130)
#define DDRC_FREQ2_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x3134)
#define DDRC_FREQ2_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x3138)
#define DDRC_FREQ2_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x313C)
#define DDRC_FREQ2_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x3140)
#define DDRC_FREQ2_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x3144)
#define DDRC_FREQ2_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3180)
#define DDRC_FREQ2_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3190)
#define DDRC_FREQ2_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3194)
#define DDRC_FREQ2_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b4)
#define DDRC_FREQ2_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b8)
#define DDRC_FREQ2_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3240)
#define DDRC_FREQ3_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x4020)
#define DDRC_FREQ3_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x4024)
#define DDRC_FREQ3_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4050)
#define DDRC_FREQ3_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4064)
#define DDRC_FREQ3_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x40dc)
#define DDRC_FREQ3_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e0)
#define DDRC_FREQ3_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e8)
#define DDRC_FREQ3_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x40ec)
#define DDRC_FREQ3_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4100)
#define DDRC_FREQ3_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4104)
#define DDRC_FREQ3_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x4108)
#define DDRC_FREQ3_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x410c)
#define DDRC_FREQ3_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x4110)
#define DDRC_FREQ3_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x4114)
#define DDRC_FREQ3_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x4118)
#define DDRC_FREQ3_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x411c)
#define DDRC_FREQ3_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x4120)
#define DDRC_FREQ3_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x4124)
#define DDRC_FREQ3_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x4128)
#define DDRC_FREQ3_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x412c)
#define DDRC_FREQ3_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x4130)
#define DDRC_FREQ3_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x4134)
#define DDRC_FREQ3_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x4138)
#define DDRC_FREQ3_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x413C)
#define DDRC_FREQ3_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x4140)
#define DDRC_FREQ3_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4180)
#define DDRC_FREQ3_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4190)
#define DDRC_FREQ3_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4194)
#define DDRC_FREQ3_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b4)
#define DDRC_FREQ3_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b8)
#define DDRC_FREQ3_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4240)
#define DDRC_DFITMG0_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190)
#define DDRC_DFITMG1_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194)
#define DDRC_DFITMG2_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4)
#define DDRC_DFITMG3_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8)
#define DDRC_ODTCFG_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240)
#define DDRPHY_CalBusy(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4 * 0x020097)
#define DRC_PERF_MON_BASE_ADDR(X) (0x3d800000 + ((X) * 0x2000000))
#define DRC_PERF_MON_CNT0_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x0)
#define DRC_PERF_MON_CNT1_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4)
#define DRC_PERF_MON_CNT2_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x8)
#define DRC_PERF_MON_CNT3_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0xC)
#define DRC_PERF_MON_CNT0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x20)
#define DRC_PERF_MON_CNT1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x24)
#define DRC_PERF_MON_CNT2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x28)
#define DRC_PERF_MON_CNT3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x2C)
#define DRC_PERF_MON_MRR0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x40)
#define DRC_PERF_MON_MRR1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x44)
#define DRC_PERF_MON_MRR2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x48)
#define DRC_PERF_MON_MRR3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4C)
#define DRC_PERF_MON_MRR4_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x50)
#define DRC_PERF_MON_MRR5_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x54)
#define DRC_PERF_MON_MRR6_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x58)
#define DRC_PERF_MON_MRR7_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x5C)
#define DRC_PERF_MON_MRR8_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x60)
#define DRC_PERF_MON_MRR9_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x64)
#define DRC_PERF_MON_MRR10_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x68)
#define DRC_PERF_MON_MRR11_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x6C)
#define DRC_PERF_MON_MRR12_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x70)
#define DRC_PERF_MON_MRR13_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x74)
#define DRC_PERF_MON_MRR14_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x78)
#define DRC_PERF_MON_MRR15_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x7C)
/* user data type */
enum fw_type {
FW_1D_IMAGE,
FW_2D_IMAGE,
};
struct dram_cfg_param {
unsigned int reg;
unsigned int val;
};
struct dram_fsp_msg {
unsigned int drate;
enum fw_type fw_type;
struct dram_cfg_param *fsp_cfg;
unsigned int fsp_cfg_num;
};
struct dram_timing_info {
/* umctl2 config */
struct dram_cfg_param *ddrc_cfg;
unsigned int ddrc_cfg_num;
/* ddrphy config */
struct dram_cfg_param *ddrphy_cfg;
unsigned int ddrphy_cfg_num;
/* ddr fsp train info */
struct dram_fsp_msg *fsp_msg;
unsigned int fsp_msg_num;
/* ddr phy trained CSR */
struct dram_cfg_param *ddrphy_trained_csr;
unsigned int ddrphy_trained_csr_num;
/* ddr phy PIE */
struct dram_cfg_param *ddrphy_pie;
unsigned int ddrphy_pie_num;
/* initialized drate table */
unsigned int fsp_table[4];
};
extern struct dram_timing_info dram_timing;
void ddr_load_train_firmware(enum fw_type type);
void ddr_init(struct dram_timing_info *timing_info);
void ddr_cfg_phy(struct dram_timing_info *timing_info);
void load_lpddr4_phy_pie(void);
void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num);
void dram_config_save(struct dram_timing_info *info, unsigned long base);
/* utils function for ddr phy training */
void wait_ddrphy_training_complete(void);
void ddrphy_init_set_dfi_clk(unsigned int drate);
void ddrphy_init_read_msg_block(enum fw_type type);
static inline void reg32_write(unsigned long addr, u32 val)
{
writel(val, addr);
}
static inline u32 reg32_read(unsigned long addr)
{
return readl(addr);
}
static inline void reg32setbit(unsigned long addr, u32 bit)
{
setbits_le32(addr, (1 << bit));
}
#define dwc_ddrphy_apb_wr(addr, data) \
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), data)
#define dwc_ddrphy_apb_rd(addr) \
reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr))
extern struct dram_cfg_param ddrphy_trained_csr[];
extern uint32_t ddrphy_trained_csr_num;
#endif
arch/arm/include/asm/arch-imx8m/ddr_memory_map.h 0 → 100644
View file @ 8e809399
#define DDRC_DDR_SS_GPR0 0x3d000000
#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
#define DDRC_MSTR_0 0x3d400000
#define DDRC_STAT_0 0x3d400004
#define DDRC_MSTR1_0 0x3d400008
#define DDRC_MRCTRL0_0 0x3d400010
#define DDRC_MRCTRL1_0 0x3d400014
#define DDRC_MRSTAT_0 0x3d400018
#define DDRC_MRCTRL2_0 0x3d40001c
#define DDRC_DERATEEN_0 0x3d400020
#define DDRC_DERATEINT_0 0x3d400024
#define DDRC_MSTR2_0 0x3d400028
#define DDRC_PWRCTL_0 0x3d400030
#define DDRC_PWRTMG_0 0x3d400034
#define DDRC_HWLPCTL_0 0x3d400038
#define DDRC_HWFFCCTL_0 0x3d40003c
#define DDRC_HWFFCSTAT_0 0x3d400040
#define DDRC_RFSHCTL0_0 0x3d400050
#define DDRC_RFSHCTL1_0 0x3d400054
#define DDRC_RFSHCTL2_0 0x3d400058
#define DDRC_RFSHCTL3_0 0x3d400060
#define DDRC_RFSHTMG_0 0x3d400064
#define DDRC_ECCCFG0_0 0x3d400070
#define DDRC_ECCCFG1_0 0x3d400074
#define DDRC_ECCSTAT_0 0x3d400078
#define DDRC_ECCCLR_0 0x3d40007c
#define DDRC_ECCERRCNT_0 0x3d400080
#define DDRC_ECCCADDR0_0 0x3d400084
#define DDRC_ECCCADDR1_0 0x3d400088
#define DDRC_ECCCSYN0_0 0x3d40008c
#define DDRC_ECCCSYN1_0 0x3d400090
#define DDRC_ECCCSYN2_0 0x3d400094
#define DDRC_ECCBITMASK0_0 0x3d400098
#define DDRC_ECCBITMASK1_0 0x3d40009c
#define DDRC_ECCBITMASK2_0 0x3d4000a0
#define DDRC_ECCUADDR0_0 0x3d4000a4
#define DDRC_ECCUADDR1_0 0x3d4000a8
#define DDRC_ECCUSYN0_0 0x3d4000ac
#define DDRC_ECCUSYN1_0 0x3d4000b0
#define DDRC_ECCUSYN2_0 0x3d4000b4
#define DDRC_ECCPOISONADDR0_0 0x3d4000b8
#define DDRC_ECCPOISONADDR1_0 0x3d4000bc
#define DDRC_CRCPARCTL0_0 0x3d4000c0
#define DDRC_CRCPARCTL1_0 0x3d4000c4
#define DDRC_CRCPARCTL2_0 0x3d4000c8
#define DDRC_CRCPARSTAT_0 0x3d4000cc
#define DDRC_INIT0_0 0x3d4000d0
#define DDRC_INIT1_0 0x3d4000d4
#define DDRC_INIT2_0 0x3d4000d8
#define DDRC_INIT3_0 0x3d4000dc
#define DDRC_INIT4_0 0x3d4000e0
#define DDRC_INIT5_0 0x3d4000e4
#define DDRC_INIT6_0 0x3d4000e8
#define DDRC_INIT7_0 0x3d4000ec
#define DDRC_DIMMCTL_0 0x3d4000f0
#define DDRC_RANKCTL_0 0x3d4000f4
#define DDRC_DRAMTMG0_0 0x3d400100
#define DDRC_DRAMTMG1_0 0x3d400104
#define DDRC_DRAMTMG2_0 0x3d400108
#define DDRC_DRAMTMG3_0 0x3d40010c
#define DDRC_DRAMTMG4_0 0x3d400110
#define DDRC_DRAMTMG5_0 0x3d400114
#define DDRC_DRAMTMG6_0 0x3d400118
#define DDRC_DRAMTMG7_0 0x3d40011c
#define DDRC_DRAMTMG8_0 0x3d400120
#define DDRC_DRAMTMG9_0 0x3d400124
#define DDRC_DRAMTMG10_0 0x3d400128
#define DDRC_DRAMTMG11_0 0x3d40012c
#define DDRC_DRAMTMG12_0 0x3d400130
#define DDRC_DRAMTMG13_0 0x3d400134
#define DDRC_DRAMTMG14_0 0x3d400138
#define DDRC_DRAMTMG15_0 0x3d40013C
#define DDRC_DRAMTMG16_0 0x3d400140
#define DDRC_DRAMTMG17_0 0x3d400144
//
#define DDRC_ZQCTL0_0 0x3d400180
#define DDRC_ZQCTL1_0 0x3d400184
#define DDRC_ZQCTL2_0 0x3d400188
#define DDRC_ZQSTAT_0 0x3d40018c
#define DDRC_DFITMG0_0 0x3d400190
#define DDRC_DFITMG1_0 0x3d400194
#define DDRC_DFILPCFG0_0 0x3d400198
#define DDRC_DFILPCFG1_0 0x3d40019c
#define DDRC_DFIUPD0_0 0x3d4001a0
#define DDRC_DFIUPD1_0 0x3d4001a4
#define DDRC_DFIUPD2_0 0x3d4001a8
//#define DDRC_DFIUPD3(X) ( DDRC_IPS_BASE_ADDR(X) + 0x1ac) // iMX8 hasn't it
#define DDRC_DFIMISC_0 0x3d4001b0
#define DDRC_DFITMG2_0 0x3d4001b4
#define DDRC_DFITMG3_0 0x3d4001b8
#define DDRC_DFISTAT_0 0x3d4001bc
//
#define DDRC_DBICTL_0 0x3d4001c0
#define DDRC_DFIPHYMSTR_0 0x3d4001c4
#define DDRC_TRAINCTL0_0 0x3d4001d0
#define DDRC_TRAINCTL1_0 0x3d4001d4
#define DDRC_TRAINCTL2_0 0x3d4001d8
#define DDRC_TRAINSTAT_0 0x3d4001dc
#define DDRC_ADDRMAP0_0 0x3d400200
#define DDRC_ADDRMAP1_0 0x3d400204
#define DDRC_ADDRMAP2_0 0x3d400208
#define DDRC_ADDRMAP3_0 0x3d40020c
#define DDRC_ADDRMAP4_0 0x3d400210
#define DDRC_ADDRMAP5_0 0x3d400214
#define DDRC_ADDRMAP6_0 0x3d400218
#define DDRC_ADDRMAP7_0 0x3d40021c
#define DDRC_ADDRMAP8_0 0x3d400220
#define DDRC_ADDRMAP9_0 0x3d400224
#define DDRC_ADDRMAP10_0 0x3d400228
#define DDRC_ADDRMAP11_0 0x3d40022c
//
#define DDRC_ODTCFG_0 0x3d400240
#define DDRC_ODTMAP_0 0x3d400244
#define DDRC_SCHED_0 0x3d400250
#define DDRC_SCHED1_0 0x3d400254
#define DDRC_PERFHPR1_0 0x3d40025c
#define DDRC_PERFLPR1_0 0x3d400264
#define DDRC_PERFWR1_0 0x3d40026c
#define DDRC_PERFVPR1_0 0x3d400274
//
#define DDRC_PERFVPW1_0 0x3d400278
//
#define DDRC_DQMAP0_0 0x3d400280
#define DDRC_DQMAP1_0 0x3d400284
#define DDRC_DQMAP2_0 0x3d400288
#define DDRC_DQMAP3_0 0x3d40028c
#define DDRC_DQMAP4_0 0x3d400290
#define DDRC_DQMAP5_0 0x3d400294
#define DDRC_DBG0_0 0x3d400300
#define DDRC_DBG1_0 0x3d400304
#define DDRC_DBGCAM_0 0x3d400308
#define DDRC_DBGCMD_0 0x3d40030c
#define DDRC_DBGSTAT_0 0x3d400310
//
#define DDRC_SWCTL_0 0x3d400320
#define DDRC_SWSTAT_0 0x3d400324
#define DDRC_OCPARCFG0_0 0x3d400330
#define DDRC_OCPARCFG1_0 0x3d400334
#define DDRC_OCPARCFG2_0 0x3d400338
#define DDRC_OCPARCFG3_0 0x3d40033c
#define DDRC_OCPARSTAT0_0 0x3d400340
#define DDRC_OCPARSTAT1_0 0x3d400344
#define DDRC_OCPARWLOG0_0 0x3d400348
#define DDRC_OCPARWLOG1_0 0x3d40034c
#define DDRC_OCPARWLOG2_0 0x3d400350
#define DDRC_OCPARAWLOG0_0 0x3d400354
#define DDRC_OCPARAWLOG1_0 0x3d400358
#define DDRC_OCPARRLOG0_0 0x3d40035c
#define DDRC_OCPARRLOG1_0 0x3d400360
#define DDRC_OCPARARLOG0_0 0x3d400364
#define DDRC_OCPARARLOG1_0 0x3d400368
#define DDRC_POISONCFG_0 0x3d40036C
#define DDRC_POISONSTAT_0 0x3d400370
#define DDRC_ADVECCINDEX_0 0x3d400003
#define DDRC_ADVECCSTAT_0 0x3d400003
#define DDRC_ECCPOISONPAT0_0 0x3d400003
#define DDRC_ECCPOISONPAT1_0 0x3d400003
#define DDRC_ECCPOISONPAT2_0 0x3d400003
#define DDRC_HIFCTL_0 0x3d400003
#define DDRC_PSTAT_0 0x3d4003fc
#define DDRC_PCCFG_0 0x3d400400
#define DDRC_PCFGR_0_0 0x3d400404
#define DDRC_PCFGR_1_0 0x3d4004b4
#define DDRC_PCFGR_2_0 0x3d400564
#define DDRC_PCFGR_3_0 0x3d400614
#define DDRC_PCFGW_0_0 0x3d400408
#define DDRC_PCFGW_1_0 0x3d400408
#define DDRC_PCFGW_2_0 0x3d400568
#define DDRC_PCFGW_3_0 0x3d400618
#define DDRC_PCFGC_0_0 0x3d40040c
#define DDRC_PCFGIDMASKCH_0 0x3d400410
#define DDRC_PCFGIDVALUECH_0 0x3d400414
#define DDRC_PCTRL_0_0 0x3d400490
#define DDRC_PCTRL_1_0 0x3d400540
#define DDRC_PCTRL_2_0 0x3d4005f0
#define DDRC_PCTRL_3_0 0x3d4006a0
#define DDRC_PCFGQOS0_0_0 0x3d400494
#define DDRC_PCFGQOS1_0_0 0x3d400498
#define DDRC_PCFGWQOS0_0_0 0x3d40049c
#define DDRC_PCFGWQOS1_0_0 0x3d4004a0
#define DDRC_SARBASE0_0 0x3d400f04
#define DDRC_SARSIZE0_0 0x3d400f08
#define DDRC_SBRCTL_0 0x3d400f24
#define DDRC_SBRSTAT_0 0x3d400f28
#define DDRC_SBRWDATA0_0 0x3d400f2c
#define DDRC_SBRWDATA1_0 0x3d400f30
#define DDRC_PDCH_0 0x3d400f34
/**********************/
#define DDRC_MSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x00)
#define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04)
#define DDRC_MSTR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x08)
#define DDRC_MRCTRL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x10)
#define DDRC_MRCTRL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x14)
#define DDRC_MRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18)
#define DDRC_MRCTRL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c)
#define DDRC_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x20)
#define DDRC_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x24)
#define DDRC_MSTR2(X) (DDRC_IPS_BASE_ADDR(X) + 0x28)
#define DDRC_PWRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x30)
#define DDRC_PWRTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x34)
#define DDRC_HWLPCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x38)
#define DDRC_HWFFCCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x3c)
#define DDRC_HWFFCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x40)
#define DDRC_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x50)
#define DDRC_RFSHCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x54)
#define DDRC_RFSHCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x58)
#define DDRC_RFSHCTL3(X) (DDRC_IPS_BASE_ADDR(X) + 0x60)
#define DDRC_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x64)
#define DDRC_ECCCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x70)
#define DDRC_ECCCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x74)
#define DDRC_ECCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x78)
#define DDRC_ECCCLR(X) (DDRC_IPS_BASE_ADDR(X) + 0x7c)
#define DDRC_ECCERRCNT(X) (DDRC_IPS_BASE_ADDR(X) + 0x80)
#define DDRC_ECCCADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0x84)
#define DDRC_ECCCADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x88)
#define DDRC_ECCCSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0x8c)
#define DDRC_ECCCSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0x90)
#define DDRC_ECCCSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0x94)
#define DDRC_ECCBITMASK0(X) (DDRC_IPS_BASE_ADDR(X) + 0x98)
#define DDRC_ECCBITMASK1(X) (DDRC_IPS_BASE_ADDR(X) + 0x9c)
#define DDRC_ECCBITMASK2(X) (DDRC_IPS_BASE_ADDR(X) + 0xa0)
#define DDRC_ECCUADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xa4)
#define DDRC_ECCUADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xa8)
#define DDRC_ECCUSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0xac)
#define DDRC_ECCUSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0xb0)
#define DDRC_ECCUSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0xb4)
#define DDRC_ECCPOISONADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xb8)
#define DDRC_ECCPOISONADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xbc)
#define DDRC_CRCPARCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0xc0)
#define DDRC_CRCPARCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0xc4)
#define DDRC_CRCPARCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0xc8)
#define DDRC_CRCPARSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xcc)
#define DDRC_INIT0(X) (DDRC_IPS_BASE_ADDR(X) + 0xd0)
#define DDRC_INIT1(X) (DDRC_IPS_BASE_ADDR(X) + 0xd4)
#define DDRC_INIT2(X) (DDRC_IPS_BASE_ADDR(X) + 0xd8)
#define DDRC_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0xdc)
#define DDRC_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0xe0)
#define DDRC_INIT5(X) (DDRC_IPS_BASE_ADDR(X) + 0xe4)
#define DDRC_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0xe8)
#define DDRC_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0xec)
#define DDRC_DIMMCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf0)
#define DDRC_RANKCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf4)
#define DDRC_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x100)
#define DDRC_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x104)
#define DDRC_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x108)
#define DDRC_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x10c)
#define DDRC_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x110)
#define DDRC_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x114)
#define DDRC_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x118)
#define DDRC_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x11c)
#define DDRC_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x120)
#define DDRC_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x124)
#define DDRC_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x128)
#define DDRC_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x12c)
#define DDRC_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x130)
#define DDRC_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x134)
#define DDRC_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x138)
#define DDRC_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x13C)
#define DDRC_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x140)
#define DDRC_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x144)
//
#define DDRC_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x180)
#define DDRC_ZQCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x184)
#define DDRC_ZQCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x188)
#define DDRC_ZQSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18c)
#define DDRC_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x190)
#define DDRC_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x194)
#define DDRC_DFILPCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x198)
#define DDRC_DFILPCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x19c)
#define DDRC_DFIUPD0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a0)
#define DDRC_DFIUPD1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a4)
#define DDRC_DFIUPD2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a8)
//#define DDRC_DFIUPD3(X) ( DDRC_IPS_BASE_ADDR(X) + 0x1ac) // iMX8 hasn't it
#define DDRC_DFIMISC(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b0)
#define DDRC_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b4)
#define DDRC_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b8)
#define DDRC_DFISTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1bc)
//
#define DDRC_DBICTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c0)
#define DDRC_DFIPHYMSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c4)
#define DDRC_TRAINCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d0)
#define DDRC_TRAINCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d4)
#define DDRC_TRAINCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d8)
#define DDRC_TRAINSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1dc)
#define DDRC_ADDRMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x200)
#define DDRC_ADDRMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x204)
#define DDRC_ADDRMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x208)
#define DDRC_ADDRMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20c)
#define DDRC_ADDRMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x210)
#define DDRC_ADDRMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x214)
#define DDRC_ADDRMAP6(X) (DDRC_IPS_BASE_ADDR(X) + 0x218)
#define DDRC_ADDRMAP7(X) (DDRC_IPS_BASE_ADDR(X) + 0x21c)
#define DDRC_ADDRMAP8(X) (DDRC_IPS_BASE_ADDR(X) + 0x220)
#define DDRC_ADDRMAP9(X) (DDRC_IPS_BASE_ADDR(X) + 0x224)
#define DDRC_ADDRMAP10(X) (DDRC_IPS_BASE_ADDR(X) + 0x228)
#define DDRC_ADDRMAP11(X) (DDRC_IPS_BASE_ADDR(X) + 0x22c)
//
#define DDRC_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x240)
#define DDRC_ODTMAP(X) (DDRC_IPS_BASE_ADDR(X) + 0x244)
#define DDRC_SCHED(X) (DDRC_IPS_BASE_ADDR(X) + 0x250)
#define DDRC_SCHED1(X) (DDRC_IPS_BASE_ADDR(X) + 0x254)
#define DDRC_PERFHPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x25c)
#define DDRC_PERFLPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x264)
#define DDRC_PERFWR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x26c)
#define DDRC_PERFVPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x274)
//
#define DDRC_PERFVPW1(X) (DDRC_IPS_BASE_ADDR(X) + 0x278)
//
#define DDRC_DQMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x280)
#define DDRC_DQMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x284)
#define DDRC_DQMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x288)
#define DDRC_DQMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x28c)
#define DDRC_DQMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x290)
#define DDRC_DQMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x294)
#define DDRC_DBG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x300)
#define DDRC_DBG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x304)
#define DDRC_DBGCAM(X) (DDRC_IPS_BASE_ADDR(X) + 0x308)
#define DDRC_DBGCMD(X) (DDRC_IPS_BASE_ADDR(X) + 0x30c)
#define DDRC_DBGSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x310)
//
#define DDRC_SWCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x320)
#define DDRC_SWSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x324)
#define DDRC_OCPARCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x330)
#define DDRC_OCPARCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x334)
#define DDRC_OCPARCFG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x338)
#define DDRC_OCPARCFG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x33c)
#define DDRC_OCPARSTAT0(X) (DDRC_IPS_BASE_ADDR(X) + 0x340)
#define DDRC_OCPARSTAT1(X) (DDRC_IPS_BASE_ADDR(X) + 0x344)
#define DDRC_OCPARWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x348)
#define DDRC_OCPARWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x34c)
#define DDRC_OCPARWLOG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x350)
#define DDRC_OCPARAWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x354)
#define DDRC_OCPARAWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x358)
#define DDRC_OCPARRLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x35c)
#define DDRC_OCPARRLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x360)
#define DDRC_OCPARARLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x364)
#define DDRC_OCPARARLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x368)
#define DDRC_POISONCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x36C)
#define DDRC_POISONSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x370)
#define DDRC_ADVECCINDEX(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
#define DDRC_ADVECCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
#define DDRC_ECCPOISONPAT0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
#define DDRC_ECCPOISONPAT1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
#define DDRC_ECCPOISONPAT2(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
#define DDRC_HIFCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
#define DDRC_PSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3fc)
#define DDRC_PCCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x400)
#define DDRC_PCFGR_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x404)
#define DDRC_PCFGR_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x404)
#define DDRC_PCFGR_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x404)
#define DDRC_PCFGR_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x404)
#define DDRC_PCFGW_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x408)
#define DDRC_PCFGW_1(X) (DDRC_IPS_BASE_ADDR(X) + 1 * 0xb0 + 0x408)
#define DDRC_PCFGW_2(X) (DDRC_IPS_BASE_ADDR(X) + 2 * 0xb0 + 0x408)
#define DDRC_PCFGW_3(X) (DDRC_IPS_BASE_ADDR(X) + 3 * 0xb0 + 0x408)
#define DDRC_PCFGC_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x40c)
#define DDRC_PCFGIDMASKCH(X) (DDRC_IPS_BASE_ADDR(X) + 0x410)
#define DDRC_PCFGIDVALUECH(X) (DDRC_IPS_BASE_ADDR(X) + 0x414)
#define DDRC_PCTRL_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x490)
#define DDRC_PCTRL_1(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 1 * 0xb0)
#define DDRC_PCTRL_2(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 2 * 0xb0)
#define DDRC_PCTRL_3(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 3 * 0xb0)
#define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494)
#define DDRC_PCFGQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x498)
#define DDRC_PCFGWQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x49c)
#define DDRC_PCFGWQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4a0)
#define DDRC_SARBASE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf04)
#define DDRC_SARSIZE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf08)
#define DDRC_SBRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf24)
#define DDRC_SBRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xf28)
#define DDRC_SBRWDATA0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf2c)
#define DDRC_SBRWDATA1(X) (DDRC_IPS_BASE_ADDR(X) + 0xf30)
#define DDRC_PDCH(X) (DDRC_IPS_BASE_ADDR(X) + 0xf34)
/*
#define DDRC_PCFGW_0_0_ADDR ((vuint8_t*)&(DDRC_PCFGW_0(0)))
#define DDRC_PCFGW_0_1_ADDR ((vuint8_t*)&(DDRC_PCFGW_0(1)))
#define DDRC_PCFGW_0_2_ADDR ((vuint8_t*)&(DDRC_PCFGW_0(2)))
#define DDRC_PCFGW_0_3_ADDR ((vuint8_t*)&(DDRC_PCFGW_0(3)))
#define DDRC_MRCTRL1_0_ADDR ((vuint8_t*)&(DDRC_MRCTRL1(0)))
#define DDRC_MRCTRL1_1_ADDR ((vuint8_t*)&(DDRC_MRCTRL1(1)))
#define DDRC_MRCTRL1_2_ADDR ((vuint8_t*)&(DDRC_MRCTRL1(2)))
#define DDRC_FREQ1_MRCTRL1_3_ADDR ((vuint8_t*)&(DDRC_MRCTRL1(3)))
*/
// SHADOW registers
#define DDRC_FREQ1_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x2020)
#define DDRC_FREQ1_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x2024)
#define DDRC_FREQ1_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2050)
#define DDRC_FREQ1_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2064)
#define DDRC_FREQ1_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20dc)
#define DDRC_FREQ1_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e0)
#define DDRC_FREQ1_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e8)
#define DDRC_FREQ1_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x20ec)
#define DDRC_FREQ1_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2100)
#define DDRC_FREQ1_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2104)
#define DDRC_FREQ1_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x2108)
#define DDRC_FREQ1_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x210c)
#define DDRC_FREQ1_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x2110)
#define DDRC_FREQ1_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x2114)
#define DDRC_FREQ1_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x2118)
#define DDRC_FREQ1_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x211c)
#define DDRC_FREQ1_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x2120)
#define DDRC_FREQ1_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x2124)
#define DDRC_FREQ1_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x2128)
#define DDRC_FREQ1_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x212c)
#define DDRC_FREQ1_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x2130)
#define DDRC_FREQ1_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x2134)
#define DDRC_FREQ1_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x2138)
#define DDRC_FREQ1_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x213C)
#define DDRC_FREQ1_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x2140)
#define DDRC_FREQ1_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x2144)
#define DDRC_FREQ1_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2180)
#define DDRC_FREQ1_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190)
#define DDRC_FREQ1_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194)
#define DDRC_FREQ1_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4)
#define DDRC_FREQ1_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8)
#define DDRC_FREQ1_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240)
#define DDRC_FREQ2_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x3020)
#define DDRC_FREQ2_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3024)
#define DDRC_FREQ2_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3050)
#define DDRC_FREQ2_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3064)
#define DDRC_FREQ2_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x30dc)
#define DDRC_FREQ2_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e0)
#define DDRC_FREQ2_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e8)
#define DDRC_FREQ2_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x30ec)
#define DDRC_FREQ2_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3100)
#define DDRC_FREQ2_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3104)
#define DDRC_FREQ2_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x3108)
#define DDRC_FREQ2_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x310c)
#define DDRC_FREQ2_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x3110)
#define DDRC_FREQ2_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x3114)
#define DDRC_FREQ2_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x3118)
#define DDRC_FREQ2_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x311c)
#define DDRC_FREQ2_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x3120)
#define DDRC_FREQ2_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x3124)
#define DDRC_FREQ2_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x3128)
#define DDRC_FREQ2_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x312c)
#define DDRC_FREQ2_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x3130)
#define DDRC_FREQ2_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x3134)
#define DDRC_FREQ2_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x3138)
#define DDRC_FREQ2_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x313C)
#define DDRC_FREQ2_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x3140)
#define DDRC_FREQ2_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x3144)
#define DDRC_FREQ2_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3180)
#define DDRC_FREQ2_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3190)
#define DDRC_FREQ2_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3194)
#define DDRC_FREQ2_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b4)
#define DDRC_FREQ2_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b8)
#define DDRC_FREQ2_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3240)
#define DDRC_FREQ3_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x4020)
#define DDRC_FREQ3_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x4024)
#define DDRC_FREQ3_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4050)
#define DDRC_FREQ3_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4064)
#define DDRC_FREQ3_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x40dc)
#define DDRC_FREQ3_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e0)
#define DDRC_FREQ3_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e8)
#define DDRC_FREQ3_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x40ec)
#define DDRC_FREQ3_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4100)
#define DDRC_FREQ3_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4104)
#define DDRC_FREQ3_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x4108)
#define DDRC_FREQ3_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x410c)
#define DDRC_FREQ3_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x4110)
#define DDRC_FREQ3_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x4114)
#define DDRC_FREQ3_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x4118)
#define DDRC_FREQ3_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x411c)
#define DDRC_FREQ3_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x4120)
#define DDRC_FREQ3_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x4124)
#define DDRC_FREQ3_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x4128)
#define DDRC_FREQ3_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x412c)
#define DDRC_FREQ3_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x4130)
#define DDRC_FREQ3_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x4134)
#define DDRC_FREQ3_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x4138)
#define DDRC_FREQ3_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x413C)
#define DDRC_FREQ3_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x4140)
#if 0
/*todo fix*/
#define DDRC_FREQ3_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x4144)
#define DDRC_FREQ3_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x4140)
#endif
#define DDRC_FREQ3_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4180)
#define DDRC_FREQ3_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4190)
#define DDRC_FREQ3_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4194)
#define DDRC_FREQ3_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b4)
#define DDRC_FREQ3_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b8)
#define DDRC_FREQ3_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4240)
#define DDRC_DFITMG0_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190)
#define DDRC_DFITMG1_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194)
#define DDRC_DFITMG2_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4)
#define DDRC_DFITMG3_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8)
#define DDRC_ODTCFG_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240)
#define DDRPHY_MEM(X) (0x3c000000 + (X * 0x2000000) + 0x50000)
#define DDRPHY_CalBusy(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4 * 0x020097)
#define DRC_PERF_MON_BASE_ADDR(X) (0x3d800000 + ((X) * 0x2000000))
#define DRC_PERF_MON_CNT0_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x0)
#define DRC_PERF_MON_CNT1_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4)
#define DRC_PERF_MON_CNT2_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x8)
#define DRC_PERF_MON_CNT3_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0xC)
#define DRC_PERF_MON_CNT0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x20)
#define DRC_PERF_MON_CNT1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x24)
#define DRC_PERF_MON_CNT2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x28)
#define DRC_PERF_MON_CNT3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x2C)
#define DRC_PERF_MON_MRR0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x40)
#define DRC_PERF_MON_MRR1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x44)
#define DRC_PERF_MON_MRR2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x48)
#define DRC_PERF_MON_MRR3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4C)
#define DRC_PERF_MON_MRR4_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x50)
#define DRC_PERF_MON_MRR5_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x54)
#define DRC_PERF_MON_MRR6_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x58)
#define DRC_PERF_MON_MRR7_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x5C)
#define DRC_PERF_MON_MRR8_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x60)
#define DRC_PERF_MON_MRR9_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x64)
#define DRC_PERF_MON_MRR10_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x68)
#define DRC_PERF_MON_MRR11_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x6C)
#define DRC_PERF_MON_MRR12_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x70)
#define DRC_PERF_MON_MRR13_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x74)
#define DRC_PERF_MON_MRR14_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x78)
#define DRC_PERF_MON_MRR15_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x7C)
arch/arm/include/asm/arch-mx8m/gpio.h → arch/arm/include/asm/arch-imx8m/gpio.h
View file @ 8e809399
......@@ -3,8 +3,8 @@
* Copyright 2017 NXP
*/
#ifndef __ASM_ARCH_MX8M_GPIO_H
#define __ASM_ARCH_MX8M_GPIO_H
#ifndef __ASM_ARCH_IMX8M_GPIO_H
#define __ASM_ARCH_IMX8M_GPIO_H
#include <asm/mach-imx/gpio.h>
......
arch/arm/include/asm/arch-imx8m/imx-regs-imx8mm.h 0 → 100644
View file @ 8e809399
/*
* Copyright 2018 NXP
*/
/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef __ARCH_IMX8MM_REGS_H
#define __ARCH_IMX8MM_REGS_H
#include <asm/mach-imx/regs-lcdif.h>
/* Based on version 0.2.2 */
#define M4_BOOTROM_BASE_ADDR 0x007E0000
#define SAI1_BASE_ADDR 0x30010000
#define SAI2_BASE_ADDR 0x30020000
#define SAI3_BASE_ADDR 0x30030000
#define SAI5_BASE_ADDR 0x30050000
#define SAI6_BASE_ADDR 0x30060000
#define MICFIL_BASE_ADDR 0x30080000
#define SPDIF1_BASE_ADDR 0x30090000
#define SPDIF2_BASE_ADDR 0x300A0000
#define SPBA2_BASE_ADDR 0x300F0000
#define AIPS1_BASE_ADDR 0x301F0000
#define GPIO1_BASE_ADDR 0x30200000
#define GPIO2_BASE_ADDR 0x30210000
#define GPIO3_BASE_ADDR 0x30220000
#define GPIO4_BASE_ADDR 0x30230000
#define GPIO5_BASE_ADDR 0x30240000
#define ANA_TSENSOR_ADDR 0x30260000
#define ANA_OSC_BASE_ADDR 0x30270000
#define WDOG1_BASE_ADDR 0x30280000
#define WDOG2_BASE_ADDR 0x30290000
#define WDOG3_BASE_ADDR 0x302A0000
#define SDMA3_BASE_ADDR 0x302B0000
#define SDMA2_BASE_ADDR 0x302C0000
#define GPT1_BASE_ADDR 0x302D0000
#define GPT2_BASE_ADDR 0x302E0000
#define GPT3_BASE_ADDR 0x302F0000
#define ROMCP_BASE_ADDR 0x30310000
#define IOMUXC_BASE_ADDR 0x30330000
#define IOMUXC_GPR_BASE_ADDR 0x30340000
#define OCOTP_BASE_ADDR 0x30350000
#define ANATOP_BASE_ADDR 0x30360000
#define SNVS_HP_BASE_ADDR 0x30370000
#define CCM_BASE_ADDR 0x30380000
#define SRC_BASE_ADDR 0x30390000
#define GPC_BASE_ADDR 0x303A0000
#define SEMA1_BASE_ADDR 0x303B0000
#define SEMA2_BASE_ADDR 0x303C0000
#define RDC_BASE_ADDR 0x303D0000
#define CSU_BASE_ADDR 0x303E0000
#define AIPS2_BASE_ADDR 0x305E0000
#define PWM1_BASE_ADDR 0x30650000
#define PWM2_BASE_ADDR 0x30660000
#define PWM3_BASE_ADDR 0x30670000
#define PWM4_BASE_ADDR 0x30680000
#define SCTR_BASE_ADDR 0x306C0000
#define GPT6_BASE_ADDR 0x306D0000
#define GPT5_BASE_ADDR 0x306E0000
#define GPT4_BASE_ADDR 0x306F0000
#define PERFMON1_ADDR 0x307B0000
#define PERFMON2_ADDR 0x307C0000
#define QOSC_BASE_ADDR 0x307E0000
#define ECSPI1_BASE_ADDR 0x30820000
#define ECSPI2_BASE_ADDR 0x30830000
#define ECSPI3_BASE_ADDR 0x30840000
#define UART1_BASE_ADDR 0x30860000
#define UART3_BASE_ADDR 0x30880000
#define UART2_BASE_ADDR 0x30890000
#define SPBA_BASE_ADDR 0x308F0000
#define CAAM_BASE_ADDR 0x30900000
#define AIPS3_BASE_ADDR 0x309F0000
#define I2C1_BASE_ADDR 0x30A20000
#define I2C2_BASE_ADDR 0x30A30000
#define I2C3_BASE_ADDR 0x30A40000
#define I2C4_BASE_ADDR 0x30A50000
#define UART4_BASE_ADDR 0x30A60000
#define MUA_BASE_ADDR 0x30AA0000
#define MUB_BASE_ADDR 0x30AB0000
#define SEMAHS_BASE_ADDR 0x30AC0000
#define USDHC1_BASE_ADDR 0x30B40000
#define USDHC2_BASE_ADDR 0x30B50000
#define USDHC3_BASE_ADDR 0x30B60000
#define QSPI_BASE_ADDR 0x30BB0000
#define QSPI0_BASE_ADDR 0x30BB0000
#define QSPI0_AMBA_BASE 0x08000000
#define SDMA1_BASE_ADDR 0x30BD0000
#define ENET1_BASE_ADDR 0x30BE0000
#define AIPS4_BASE_ADDR 0x32DF0000
#define LCDIF_BASE_ADDR 0x32E00000
#define MIPI_DSI_BASE_ADDR 0x32E10000
#define CSI_BASE_ADDR 0x32E20000
#define MIPI_CSI_BASE_ADDR 0x32E30000
#define USB1_BASE_ADDR 0x32E40000
#define USB2_BASE_ADDR 0x32E50000
#define PCIE_PHY1_BASE_ADDR 0x32F00000
#define TZASC_BASE_ADDR 0x32F80000
#define PLAT_CTRL_BASE_ADDR 0x32FE0000
#define MXS_APBH_BASE 0x33000000
#define MXS_GPMI_BASE 0x33002000
#define MXS_BCH_BASE 0x33004000
#define USB_BASE_ADDR USB1_BASE_ADDR
#define MXS_LCDIF_BASE LCDIF_BASE_ADDR
#define IOMUXC_GPR0 (IOMUXC_GPR_BASE_ADDR + 0x00)
#define IOMUXC_GPR1 (IOMUXC_GPR_BASE_ADDR + 0x04)
#define IOMUXC_GPR2 (IOMUXC_GPR_BASE_ADDR + 0x08)
#define IOMUXC_GPR3 (IOMUXC_GPR_BASE_ADDR + 0x0c)
#define IOMUXC_GPR4 (IOMUXC_GPR_BASE_ADDR + 0x10)
#define IOMUXC_GPR5 (IOMUXC_GPR_BASE_ADDR + 0x14)
#define IOMUXC_GPR6 (IOMUXC_GPR_BASE_ADDR + 0x18)
#define IOMUXC_GPR7 (IOMUXC_GPR_BASE_ADDR + 0x1c)
#define IOMUXC_GPR8 (IOMUXC_GPR_BASE_ADDR + 0x20)
#define IOMUXC_GPR9 (IOMUXC_GPR_BASE_ADDR + 0x24)
#define IOMUXC_GPR10 (IOMUXC_GPR_BASE_ADDR + 0x28)
#define IOMUXC_GPR11 (IOMUXC_GPR_BASE_ADDR + 0x2C)
#define IOMUXC_GPR22 (IOMUXC_GPR_BASE_ADDR + 0x58)
#define CNTCR_OFF 0x00
#define CNTFID0_OFF 0x20
#define CNTFID1_OFF 0x24
#define SC_CNTCR_ENABLE (1 << 0)
#define SC_CNTCR_HDBG (1 << 1)
#define SC_CNTCR_FREQ0 (1 << 8)
#define SC_CNTCR_FREQ1 (1 << 9)
#define IMX_CSPI1_BASE 0x30820000
#define IMX_CSPI2_BASE 0x30830000
#define IMX_CSPI3_BASE 0x30840000
#define MXC_SPI_BASE_ADDRESSES \
IMX_CSPI1_BASE, \
IMX_CSPI2_BASE, \
IMX_CSPI3_BASE
#define SRC_IPS_BASE_ADDR 0x30390000
#define SRC_DDRC_RCR_ADDR 0x30391000
#define SRC_DDRC2_RCR_ADDR 0x30391004
#define DDR_CSD1_BASE_ADDR 0x40000000
#define CAAM_ARB_BASE_ADDR (0x00100000)
#define CAAM_ARB_END_ADDR (0x00107FFF)
#define CAAM_IPS_BASE_ADDR (0x30900000)
#define CONFIG_SYS_FSL_SEC_OFFSET (0)
#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
CONFIG_SYS_FSL_SEC_OFFSET)
#define CONFIG_SYS_FSL_JR0_OFFSET (0x1000)
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
CONFIG_SYS_FSL_JR0_OFFSET)
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
#include <linux/bitops.h>
#include <stdbool.h>
#define GPR_TZASC_EN BIT(0)
#define GPR_TZASC_EN_LOCK BIT(16)
#define GPR_TZASC_SWAP_ID BIT(1)
#define SRC_SCR_M4_ENABLE_OFFSET 3
#define SRC_SCR_M4_ENABLE_MASK BIT(3)
#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 0
#define SRC_SCR_M4C_NON_SCLR_RST_MASK BIT(0)
#define SRC_DDR1_ENABLE_MASK 0x8F000000UL
#define SRC_DDR2_ENABLE_MASK 0x8F000000UL
#define SRC_DDR1_RCR_PHY_PWROKIN_N_MASK BIT(3)
#define SRC_DDR1_RCR_PHY_RESET_MASK BIT(2)
#define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1)
#define SRC_DDR1_RCR_PRESET_N_MASK BIT(0)
extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
struct iomuxc_gpr_base_regs {
u32 gpr[47];
};
struct ocotp_regs {
u32 ctrl;
u32 ctrl_set;
u32 ctrl_clr;
u32 ctrl_tog;
u32 timing;
u32 rsvd0[3];
u32 data;
u32 rsvd1[3];
u32 read_ctrl;
u32 rsvd2[3];
u32 read_fuse_data;
u32 rsvd3[3];
u32 sw_sticky;
u32 rsvd4[3];
u32 scs;
u32 scs_set;
u32 scs_clr;
u32 scs_tog;
u32 crc_addr;
u32 rsvd5[3];
u32 crc_value;
u32 rsvd6[3];
u32 version;
u32 rsvd7[0xdb];
/* fuse banks */
struct fuse_bank {
u32 fuse_regs[0x10];
} bank[0];
};
struct fuse_bank0_regs {
u32 lock;
u32 rsvd0[3];
u32 uid_low;
u32 rsvd1[3];
u32 uid_high;
u32 rsvd2[7];
};
struct fuse_bank1_regs {
u32 tester3;
u32 rsvd0[3];
u32 tester4;
u32 rsvd1[3];
u32 tester5;
u32 rsvd2[3];
u32 cfg0;
u32 rsvd3[3];
};
struct ana_grp {
u32 gnrl_ctl;
u32 fdiv_ctl0;
u32 fdiv_ctl1;
u32 sscg_ctl;
u32 mnit_ctl;
};
struct ana_grp2 {
u32 gnrl_ctl;
u32 div_ctl;
u32 locked_ctl;
u32 mnit_ctl;
};
struct anamix_pll {
struct ana_grp audio_pll1;
struct ana_grp audio_pll2;
struct ana_grp video_pll1;
u32 reserved1[5];
struct ana_grp dram_pll;
struct ana_grp2 gpu_pll;
struct ana_grp2 vpu_pll;
struct ana_grp2 arm_pll;
struct ana_grp2 sys_pll1;
u32 reserved2[6*4];
struct ana_grp2 sys_pll2;
struct ana_grp2 sys_pll3;
u32 anamix_misc_ctl; /* 0x124 */
u32 reserved3[438]; /* 0x128 */
u32 digprog; /* 0x800 */
};
struct fuse_bank9_regs {
u32 mac_addr0;
u32 rsvd0[3];
u32 mac_addr1;
u32 rsvd1[11];
};
/* System Reset Controller (SRC) */
struct src {
u32 scr;
u32 a53rcr;
u32 a53rcr1;
u32 m4rcr;
u32 reserved1[4];
u32 usbophy1_rcr;
u32 usbophy2_rcr;
u32 mipiphy_rcr;
u32 pciephy_rcr;
u32 reserved2;
u32 disp_rcr;
u32 reserved3[2];
u32 gpu_rcr;
u32 vpu_rcr;
u32 reserved4[4];
u32 sbmr1;
u32 srsr;
u32 reserved5[2];
u32 sisr;
u32 simr;
u32 sbmr2;
u32 gpr1;
u32 gpr2;
u32 gpr3;
u32 gpr4;
u32 gpr5;
u32 gpr6;
u32 gpr7;
u32 gpr8;
u32 gpr9;
u32 gpr10;
u32 reserved6[985];
u32 ddr1_rcr;
};
struct gpc_reg {
u32 lpcr_bsc;
u32 lpcr_ad;
u32 lpcr_cpu1;
u32 lpcr_cpu2;
u32 lpcr_cpu3;
u32 slpcr;
u32 mst_cpu_mapping;
u32 mmdc_cpu_mapping;
u32 mlpcr;
u32 pgc_ack_sel;
u32 pgc_ack_sel_m4;
u32 gpc_misc;
u32 imr1_core0;
u32 imr2_core0;
u32 imr3_core0;
u32 imr4_core0;
u32 imr1_core1;
u32 imr2_core1;
u32 imr3_core1;
u32 imr4_core1;
u32 imr1_cpu1;
u32 imr2_cpu1;
u32 imr3_cpu1;
u32 imr4_cpu1;
u32 imr1_cpu3;
u32 imr2_cpu3;
u32 imr3_cpu3;
u32 imr4_cpu3;
u32 isr1_cpu0;
u32 isr2_cpu0;
u32 isr3_cpu0;
u32 isr4_cpu0;
u32 isr1_cpu1;
u32 isr2_cpu1;
u32 isr3_cpu1;
u32 isr4_cpu1;
u32 isr1_cpu2;
u32 isr2_cpu2;
u32 isr3_cpu2;
u32 isr4_cpu2;
u32 isr1_cpu3;
u32 isr2_cpu3;
u32 isr3_cpu3;
u32 isr4_cpu3;
u32 slt0_cfg;
u32 slt1_cfg;
u32 slt2_cfg;
u32 slt3_cfg;
u32 slt4_cfg;
u32 slt5_cfg;
u32 slt6_cfg;
u32 slt7_cfg;
u32 slt8_cfg;
u32 slt9_cfg;
u32 slt10_cfg;
u32 slt11_cfg;
u32 slt12_cfg;
u32 slt13_cfg;
u32 slt14_cfg;
u32 pgc_cpu_0_1_mapping;
u32 cpu_pgc_up_trg;
u32 mix_pgc_up_trg;
u32 pu_pgc_up_trg;
u32 cpu_pgc_dn_trg;
u32 mix_pgc_dn_trg;
u32 pu_pgc_dn_trg;
u32 lpcr_bsc2;
u32 pgc_cpu_2_3_mapping;
u32 lps_cpu0;
u32 lps_cpu1;
u32 lps_cpu2;
u32 lps_cpu3;
u32 gpc_gpr;
u32 gtor;
u32 debug_addr1;
u32 debug_addr2;
u32 cpu_pgc_up_status1;
u32 mix_pgc_up_status0;
u32 mix_pgc_up_status1;
u32 mix_pgc_up_status2;
u32 m4_mix_pgc_up_status0;
u32 m4_mix_pgc_up_status1;
u32 m4_mix_pgc_up_status2;
u32 pu_pgc_up_status0;
u32 pu_pgc_up_status1;
u32 pu_pgc_up_status2;
u32 m4_pu_pgc_up_status0;
u32 m4_pu_pgc_up_status1;
u32 m4_pu_pgc_up_status2;
u32 a53_lp_io_0;
u32 a53_lp_io_1;
u32 a53_lp_io_2;
u32 cpu_pgc_dn_status1;
u32 mix_pgc_dn_status0;
u32 mix_pgc_dn_status1;
u32 mix_pgc_dn_status2;
u32 m4_mix_pgc_dn_status0;
u32 m4_mix_pgc_dn_status1;
u32 m4_mix_pgc_dn_status2;
u32 pu_pgc_dn_status0;
u32 pu_pgc_dn_status1;
u32 pu_pgc_dn_status2;
u32 m4_pu_pgc_dn_status0;
u32 m4_pu_pgc_dn_status1;
u32 m4_pu_pgc_dn_status2;
u32 res[3];
u32 mix_pdn_flg;
u32 pu_pdn_flg;
u32 m4_mix_pdn_flg;
u32 m4_pu_pdn_flg;
u32 imr1_core2;
u32 imr2_core2;
u32 imr3_core2;
u32 imr4_core2;
u32 imr1_core3;
u32 imr2_core3;
u32 imr3_core3;
u32 imr4_core3;
u32 pgc_ack_sel_pu;
u32 pgc_ack_sel_m4_pu;
u32 slt15_cfg;
u32 slt16_cfg;
u32 slt17_cfg;
u32 slt18_cfg;
u32 slt19_cfg;
u32 gpc_pu_pwrhsk;
u32 slt0_cfg_pu;
u32 slt1_cfg_pu;
u32 slt2_cfg_pu;
u32 slt3_cfg_pu;
u32 slt4_cfg_pu;
u32 slt5_cfg_pu;
u32 slt6_cfg_pu;
u32 slt7_cfg_pu;
u32 slt8_cfg_pu;
u32 slt9_cfg_pu;
u32 slt10_cfg_pu;
u32 slt11_cfg_pu;
u32 slt12_cfg_pu;
u32 slt13_cfg_pu;
u32 slt14_cfg_pu;
u32 slt15_cfg_pu;
u32 slt16_cfg_pu;
u32 slt17_cfg_pu;
u32 slt18_cfg_pu;
u32 slt19_cfg_pu;
};
#define WDOG_WDT_MASK BIT(3)
#define WDOG_WDZST_MASK BIT(0)
struct wdog_regs {
u16 wcr; /* Control */
u16 wsr; /* Service */
u16 wrsr; /* Reset Status */
u16 wicr; /* Interrupt Control */
u16 wmcr; /* Miscellaneous Control */
};
/* Boot device type */
#define BOOT_TYPE_SD 0x1
#define BOOT_TYPE_MMC 0x2
#define BOOT_TYPE_NAND 0x3
#define BOOT_TYPE_QSPI 0x4
#define BOOT_TYPE_WEIM 0x5
#define BOOT_TYPE_SPINOR 0x6
#define BOOT_TYPE_USB 0xF
#define ROM_SW_INFO_ADDR_A0 0x000009e8
#define ROM_SW_INFO_ADDR 0x000009e8
struct bootrom_sw_info {
u8 reserved_1;
u8 boot_dev_instance;
u8 boot_dev_type;
u8 reserved_2;
u32 core_freq;
u32 axi_freq;
u32 ddr_freq;
u32 tick_freq;
u32 reserved_3[3];
};
/* ECSPI registers */
struct cspi_regs {
u32 rxdata;
u32 txdata;
u32 ctrl;
u32 cfg;
u32 intr;
u32 dma;
u32 stat;
u32 period;
};
/*
* CSPI register definitions
*/
#define MXC_ECSPI
#define MXC_CSPICTRL_EN (1 << 0)
#define MXC_CSPICTRL_MODE (1 << 1)
#define MXC_CSPICTRL_XCH (1 << 2)
#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
#define MXC_CSPICTRL_MAXBITS 0xfff
#define MXC_CSPICTRL_TC (1 << 7)
#define MXC_CSPICTRL_RXOVF (1 << 6)
#define MXC_CSPIPERIOD_32KHZ (1 << 15)
#define MAX_SPI_BYTES 32
/* Bit position inside CTRL register to be associated with SS */
#define MXC_CSPICTRL_CHAN 18
/* Bit position inside CON register to be associated with SS */
#define MXC_CSPICON_PHA 0 /* SCLK phase control */
#define MXC_CSPICON_POL 4 /* SCLK polarity */
#define MXC_CSPICON_SSPOL 12 /* SS polarity */
#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
#include <stdbool.h>
bool is_usb_boot(void);
#define is_boot_from_usb is_usb_boot
#define disconnect_from_pc(void) clrbits_le32(USB1_BASE_ADDR + 0xc704, (1 << 31));
#endif
#endif