diff --git a/board/Marvell/db64360/db64360.c b/board/Marvell/db64360/db64360.c
index a2ab2d7818573449eba8d2f4f54f8481f7a2a8e9..2a810a618b09026ad372a9c3675916c6f6359dea 100644
--- a/board/Marvell/db64360/db64360.c
+++ b/board/Marvell/db64360/db64360.c
@@ -51,9 +51,6 @@
 #define DP(x)
 #endif
 
-extern void flush_data_cache (void);
-extern void invalidate_l1_instruction_cache (void);
-
 /* ------------------------------------------------------------------------- */
 
 /* this is the current GT register space location */
@@ -930,7 +927,5 @@ void board_prebootm_init ()
 	my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM);
 
 	icache_disable ();
-	invalidate_l1_instruction_cache ();
-	flush_data_cache ();
 	dcache_disable ();
 }
diff --git a/board/Marvell/db64460/db64460.c b/board/Marvell/db64460/db64460.c
index a4abf8d1fa9839eaaa6bf56de43a87ec7608a320..1ae898d1ee9c2e826563ca1fc909cc4d1c91b57f 100644
--- a/board/Marvell/db64460/db64460.c
+++ b/board/Marvell/db64460/db64460.c
@@ -51,9 +51,6 @@
 #define DP(x)
 #endif
 
-extern void flush_data_cache (void);
-extern void invalidate_l1_instruction_cache (void);
-
 /* ------------------------------------------------------------------------- */
 
 /* this is the current GT register space location */
@@ -930,7 +927,5 @@ void board_prebootm_init ()
 	my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM);
 
 	icache_disable ();
-	invalidate_l1_instruction_cache ();
-	flush_data_cache ();
 	dcache_disable ();
 }
diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c
index 298aa6a195f6bca3fb6e216cb4296e1580354836..5ab76c6b8720d413420c5b7fd0313c7b9a5b62a7 100644
--- a/board/esd/cpci750/cpci750.c
+++ b/board/esd/cpci750/cpci750.c
@@ -120,8 +120,6 @@ static char show_config_tab[][15] = {{"PCI0DLL_2     "},  /* 31 */
 				     {"DRAMPLL_NDiv_1"},  /* 01 */
 				     {"DRAMPLL_NDiv_0"}}; /* 00 */
 
-extern void flush_data_cache (void);
-extern void invalidate_l1_instruction_cache (void);
 extern flash_info_t flash_info[];
 
 /* ------------------------------------------------------------------------- */
@@ -961,8 +959,6 @@ void board_prebootm_init ()
 	my_remap_gt_regs_bootm (CFG_GT_REGS, CFG_DFL_GT_REGS);
 
 	icache_disable ();
-	invalidate_l1_instruction_cache ();
-	flush_data_cache ();
 	dcache_disable ();
 }
 
diff --git a/board/freescale/mpc7448hpc2/mpc7448hpc2.c b/board/freescale/mpc7448hpc2/mpc7448hpc2.c
index b3d83cc19f7793bded7bd1c160f370d4c1873dc7..6f74c314ebf129e5191c8ac80a016b57ab2fc151 100644
--- a/board/freescale/mpc7448hpc2/mpc7448hpc2.c
+++ b/board/freescale/mpc7448hpc2/mpc7448hpc2.c
@@ -37,8 +37,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern void flush_data_cache (void);
-extern void invalidate_l1_instruction_cache (void);
 extern void tsi108_init_f (void);
 
 int display_mem_map (void);
diff --git a/board/prodrive/p3mx/p3mx.c b/board/prodrive/p3mx/p3mx.c
index d54ddaffc1ecbc4dbe51fc382430773d79f1d9d6..69d7c9b28e6cc5e5fc70f9b1ff8241f018942d0a 100644
--- a/board/prodrive/p3mx/p3mx.c
+++ b/board/prodrive/p3mx/p3mx.c
@@ -62,8 +62,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define DP(x)
 #endif
 
-extern void flush_data_cache (void);
-extern void invalidate_l1_instruction_cache (void);
 extern flash_info_t flash_info[];
 
 /* ------------------------------------------------------------------------- */
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 529596926001730d491e23eb35a8593e6d9d1e30..0b14b066f5d603e271764c713d429629d4e84592 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -236,8 +236,6 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 	 * bios emulation, so turn them off again
 	 */
 	icache_disable();
-	invalidate_l1_instruction_cache();
-	flush_data_cache();
 	dcache_disable();
 #endif
 
diff --git a/cpu/74xx_7xx/cache.S b/cpu/74xx_7xx/cache.S
index 3a745cbe0312fbd385d27411b2a67c9f197df5b6..eac4544ef2ed5bbeb73e48f377881b5109f4d133 100644
--- a/cpu/74xx_7xx/cache.S
+++ b/cpu/74xx_7xx/cache.S
@@ -245,6 +245,10 @@ _GLOBAL(icache_enable)
  * Disable L1 Instruction cache
  */
 _GLOBAL(icache_disable)
+	mflr	r4
+	bl	invalidate_l1_instruction_cache		/* uses r3 */
+	sync
+	mtlr	r4
 	mfspr	r3, HID0
 	li	r5, 0
 	ori	r5, r5, HID0_ICE
diff --git a/cpu/mpc86xx/cache.S b/cpu/mpc86xx/cache.S
index 2e4ea0239f1aa08e8d50a81d09cbe185a7b09b89..80ff68889b8a51d2cd5fb38371450fc069901401 100644
--- a/cpu/mpc86xx/cache.S
+++ b/cpu/mpc86xx/cache.S
@@ -232,6 +232,10 @@ _GLOBAL(icache_enable)
  * Disable L1 Instruction cache
  */
 _GLOBAL(icache_disable)
+	mflr	r4
+	bl	invalidate_l1_instruction_cache		/* uses r3 */
+	sync
+	mtlr	r4
 	mfspr	r3, HID0
 	li	r5, 0
 	ori	r5, r5, HID0_ICE