diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index bf8ff598acd7f43ea250be3b6ff5d13b6cf922a4..7482005b6796304f108317284d6427024c7c9613 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -95,6 +95,10 @@ void flush_dcache_range(ulong start_addr, ulong stop)
 	const void *addr = (const void *)(start_addr & ~(lsize - 1));
 	const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
 
+	/* aend will be miscalculated when size is zero, so we return here */
+	if (start_addr == stop)
+		return;
+
 	while (1) {
 		mips_cache(HIT_WRITEBACK_INV_D, addr);
 		if (addr == aend)
@@ -109,6 +113,10 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
 	const void *addr = (const void *)(start_addr & ~(lsize - 1));
 	const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
 
+	/* aend will be miscalculated when size is zero, so we return here */
+	if (start_addr == stop)
+		return;
+
 	while (1) {
 		mips_cache(HIT_INVALIDATE_D, addr);
 		if (addr == aend)