diff --git a/board/boundary/common/Makefile b/board/boundary/common/Makefile
index 75c2d747e5ac1dd9a4a5d968877f7c7edc0da8e3..2dcc13db451aae25f2021c6e47ff60e5ec062867 100644
--- a/board/boundary/common/Makefile
+++ b/board/boundary/common/Makefile
@@ -1,7 +1,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
+obj-y  := eth.o
 ifneq ($(CONFIG_ARCH_MX8M),y)
-obj-y  := eth.o bd_common.o
+obj-y  += bd_common.o
 obj-$(CONFIG_CMD_KBD)  += cmd_kbd.o
 endif
 obj-$(CONFIG_MAX77823)  += max77823.o
diff --git a/board/boundary/common/bd_common.h b/board/boundary/common/bd_common.h
index 212d83083ba690985b18869012bae1868c2fe952..99e087455f03a0023c6f9671024b9e9575d5b4f2 100644
--- a/board/boundary/common/bd_common.h
+++ b/board/boundary/common/bd_common.h
@@ -25,6 +25,7 @@ extern struct fsl_esdhc_cfg board_usdhc_cfg[];
 extern const char *board_type;
 void board_preboot_keys(void);
 void board_late_specific_init(void);
+void board_eth_addresses(void);
 const char *board_get_board_type(void);
 void set_gpios_in(const unsigned short *p, int cnt);
 void set_gpios(const unsigned short *p, int cnt, int val);
diff --git a/board/boundary/common/eth-mx8m.c b/board/boundary/common/eth-mx8m.c
new file mode 100644
index 0000000000000000000000000000000000000000..686808a05db9b36a0d5da7fa428b440dcb640f4c
--- /dev/null
+++ b/board/boundary/common/eth-mx8m.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2018, Boundary Devices <info@boundarydevices.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#define GP_PHY_RX_CTL	IMX_GPIO_NR(1, 24)
+#define GP_PHY_RXC	IMX_GPIO_NR(1, 25)
+#define GP_PHY_RD0	IMX_GPIO_NR(1, 26)
+#define GP_PHY_RD1	IMX_GPIO_NR(1, 27)
+#define GP_PHY_RD2	IMX_GPIO_NR(1, 28)
+#define GP_PHY_RD3	IMX_GPIO_NR(1, 29)
+
+#ifndef STRAP_AR8035
+#define STRAP_AR8035	(0x28 | (CONFIG_FEC_MXC_PHYADDR & 3))
+#endif
+
+#ifdef CONFIG_PHY_ATHEROS
+static const iomux_v3_cfg_t enet_ar8035_gpio_pads[] = {
+#define GP_RGMII_PHY_RESET	IMX_GPIO_NR(1, 9)
+	IOMUX_PAD_CTRL(GPIO1_IO09__GPIO1_IO9, PAD_CTL_DSE6),
+	IOMUX_PAD_CTRL(ENET_RD0__GPIO1_IO26, PULL_GP(STRAP_AR8035, 0)),
+	IOMUX_PAD_CTRL(ENET_RD1__GPIO1_IO27, PULL_GP(STRAP_AR8035, 1)),
+	IOMUX_PAD_CTRL(ENET_RD2__GPIO1_IO28, PULL_GP(STRAP_AR8035, 2)),
+	IOMUX_PAD_CTRL(ENET_RD3__GPIO1_IO29, PULL_GP(STRAP_AR8035, 3)),
+	IOMUX_PAD_CTRL(ENET_RX_CTL__GPIO1_IO24, PULL_GP(STRAP_AR8035, 4)),
+	/* 1.8V(1)/1.5V select(0) */
+	IOMUX_PAD_CTRL(ENET_RXC__GPIO1_IO25, PULL_GP(STRAP_AR8035, 5)),
+};
+
+static const iomux_v3_cfg_t enet_ar8035_pads[] = {
+	IOMUX_PAD_CTRL(ENET_RD0__ENET_RGMII_RD0, PULL_ENET(STRAP_AR8035, 0)),
+	IOMUX_PAD_CTRL(ENET_RD1__ENET_RGMII_RD1, PULL_ENET(STRAP_AR8035, 1)),
+	IOMUX_PAD_CTRL(ENET_RD2__ENET_RGMII_RD2, PULL_ENET(STRAP_AR8035, 2)),
+	IOMUX_PAD_CTRL(ENET_RD3__ENET_RGMII_RD3, PULL_ENET(STRAP_AR8035, 3)),
+	IOMUX_PAD_CTRL(ENET_RX_CTL__ENET_RGMII_RX_CTL, PULL_ENET(STRAP_AR8035, 4)),
+	IOMUX_PAD_CTRL(ENET_RXC__ENET_RGMII_RXC, PULL_ENET(STRAP_AR8035, 5)),
+};
+#endif
diff --git a/board/boundary/common/eth.c b/board/boundary/common/eth.c
index 80a91d0191cf97fc84dd3cc8af22b987344f11eb..bcfe778ddf5a303a490de3382cceb9a54422f409 100644
--- a/board/boundary/common/eth.c
+++ b/board/boundary/common/eth.c
@@ -9,13 +9,15 @@
 #include <asm/arch/imx-regs.h>
 #if defined(CONFIG_MX51)
 #include <asm/arch/iomux-mx51.h>
-#elif defined(CONFIG_MX7D)
+#elif defined(CONFIG_MX7D) || defined(CONFIG_MX8M)
 #else
 #include <asm/arch/iomux.h>
 #endif
 #include <asm/arch/sys_proto.h>
 #if defined(CONFIG_MX7D)
 #include <asm/arch/mx7-pins.h>
+#elif defined(CONFIG_MX8M)
+#include <asm/arch/mx8mq_pins.h>
 #elif !defined(CONFIG_MX51)
 #include <asm/arch/mx6-pins.h>
 #endif
@@ -78,6 +80,8 @@
 #include "eth-mx7d.c"
 #elif defined(CONFIG_MX51)
 #include "eth-mx51.c"
+#elif defined(CONFIG_MX8M)
+#include "eth-mx8m.c"
 #else
 #include "eth-mx6.c"
 #endif
@@ -145,6 +149,15 @@ static void init_fec_clocks(void)
 		 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
 
 	set_clk_enet(ENET_125MHZ);
+#endif
+#ifdef CONFIG_MX8M
+	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
+		= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
+
+	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
+	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
+			BIT(13) | BIT(17), 0);
+	set_clk_enet(ENET_125MHZ);
 #endif
 	udelay(100);	/* Wait 100 us before using mii interface */
 }
@@ -155,6 +168,7 @@ static void init_fec_clocks(void)
 #define FEC_INDEX	-1	/* just plain FEC */
 #endif
 
+#ifndef CONFIG_DM_ETH
 static void init_fec(bd_t *bis, unsigned phy_mask)
 {
 #ifdef CONFIG_MX6SX
@@ -209,6 +223,7 @@ error:
 #endif
 }
 #endif
+#endif
 
 #ifdef CONFIG_PHY_ATHEROS
 static void setup_gpio_ar8035(void)
@@ -275,7 +290,7 @@ static void setup_iomux_enet(int kz)
 	udelay(40);
 #else
 	/* strap hold time for AR8035, 5 fails, 6 works, so 12 should be safe */
-	udelay(12);
+	udelay(24);
 #endif
 #ifdef GP_KS8995_RESET
 	gpio_direction_output(GP_KS8995_RESET, 1);
@@ -447,20 +462,9 @@ free_slave:
 }
 #endif
 
-int board_eth_init(bd_t *bis)
+void board_eth_addresses(void)
 {
-#if defined(CONFIG_PHY_ATHEROS) || defined(CONFIG_PHY_MICREL)
-	setup_iomux_enet(0);
-#endif
-#ifdef GP_KS8995_RESET
-	ks8995_reset();
-#endif
-#ifdef CONFIG_FEC_MXC
-	init_fec_clocks();
-	init_fec(bis, ETH_PHY_MASK);
-#endif
-
-#ifdef CONFIG_CI_UDC
+#if defined(CONFIG_USB_ETHER)
 #if defined(CONFIG_FEC_MXC) && defined(CONFIG_RGMII1) && defined(CONFIG_RGMII2)
 #define USB_ETH "eth2addr"
 #elif defined(CONFIG_FEC_MXC)
@@ -484,7 +488,44 @@ int board_eth_init(bd_t *bis)
 	if (!env_get(USB_ETH))
 		env_set(USB_ETH, env_get("usbnet_devaddr"));
 #endif
+#endif
+}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_PHY_ATHEROS) || defined(CONFIG_PHY_MICREL)
+	gpio_request(GP_RGMII_PHY_RESET, "fec_rst");
+	gpio_request(GP_PHY_RD0, "fec_rd0");
+	gpio_request(GP_PHY_RD1, "fec_rd1");
+	gpio_request(GP_PHY_RD2, "fec_rd2");
+	gpio_request(GP_PHY_RD3, "fec_rd3");
+	gpio_request(GP_PHY_RX_CTL, "fec_rx_ctl");
+	gpio_request(GP_PHY_RXC, "fec_rxc");
+	setup_iomux_enet(0);
+#endif
+#ifdef GP_KS8995_RESET
+	ks8995_reset();
+#endif
+#ifdef CONFIG_FEC_MXC
+	init_fec_clocks();
+#ifndef CONFIG_DM_ETH
+	init_fec(bis, ETH_PHY_MASK);
+#endif
+#endif
+
+	board_eth_addresses();
+#if defined(CONFIG_USB_ETHER)
+#if defined(CONFIG_DM_ETH)
+	{
+		int ret = usb_ether_init();
+
+		if (ret) {
+			printf("usb_ether_init failed(%d)\n", ret);
+		}
+	}
+#else
 	usb_eth_initialize(bis);
+#endif
 #endif
 	return 0;
 }
diff --git a/board/boundary/common/padctrl-mx8m.h b/board/boundary/common/padctrl-mx8m.h
new file mode 100644
index 0000000000000000000000000000000000000000..c77e91c724c69b5a446feb0ebe75d6e6a277bf3b
--- /dev/null
+++ b/board/boundary/common/padctrl-mx8m.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2018, Boundary Devices <info@boundarydevices.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#define PAD_CTRL_ENET_MDC	(PAD_CTL_DSE3)
+#define PAD_CTRL_ENET_MDIO	(PAD_CTL_DSE3 | PAD_CTL_ODE)
+
+#define PAD_CTRL_ENET_RX	0x91
+#define PAD_CTRL_ENET_RX_DN	(PAD_CTRL_ENET_RX)
+#define PAD_CTRL_ENET_RX_UP	(PAD_CTL_PUE | PAD_CTRL_ENET_RX)
+
+#define PAD_CTRL_ENET_TX	0x1f
+
+#define WEAK_PULLUP		(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define WEAK_PULLUP_OUTPUT	0xd1
+#define WEAK_PULLDN_OUTPUT	0x91	/* Cannot pull down */
+
+#define QSPI_PAD_CTRL	(PAD_CTL_DSE2 | PAD_CTL_HYS)
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
diff --git a/board/boundary/common/padctrl.h b/board/boundary/common/padctrl.h
index 32b0a8ff0b77398a86b04df8927a2bc0970e69dd..06bf3055303ea042a2089b55d0ff66733ad19d0d 100644
--- a/board/boundary/common/padctrl.h
+++ b/board/boundary/common/padctrl.h
@@ -9,6 +9,8 @@
 #include "padctrl-mx7d.h"
 #elif defined(CONFIG_MX51)
 #include "padctrl-mx51.h"
+#elif defined(CONFIG_MX8M)
+#include "padctrl-mx8m.h"
 #else
 #include "padctrl-mx6.h"
 #endif