diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index da57b385c92296c460250c688c78b1141acb4fb2..ef2ac982171fc41fe43e552e649234fde09664d7 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -596,10 +596,34 @@ void scale_vcores(struct vcores_data const *vcores)
debug("gpu: %d\n", vcores->gpu.value);
do_scale_vcore(vcores->gpu.addr, vcores->gpu.value, vcores->gpu.pmic);
+ /* Configure GPU ABB LDO after scale */
+ abb_setup(vcores->gpu.efuse.reg,
+ (*ctrl)->control_wkup_ldovbb_gpu_voltage_ctrl,
+ (*prcm)->prm_abbldo_gpu_setup,
+ (*prcm)->prm_abbldo_gpu_ctrl,
+ (*prcm)->prm_irqstatus_mpu,
+ vcores->gpu.abb_tx_done_mask,
+ OMAP_ABB_FAST_OPP);
debug("eve: %d\n", vcores->eve.value);
do_scale_vcore(vcores->eve.addr, vcores->eve.value, vcores->eve.pmic);
+ /* Configure EVE ABB LDO after scale */
+ abb_setup(vcores->eve.efuse.reg,
+ (*ctrl)->control_wkup_ldovbb_eve_voltage_ctrl,
+ (*prcm)->prm_abbldo_eve_setup,
+ (*prcm)->prm_abbldo_eve_ctrl,
+ (*prcm)->prm_irqstatus_mpu,
+ vcores->eve.abb_tx_done_mask,
+ OMAP_ABB_FAST_OPP);
debug("iva: %d\n", vcores->iva.value);
do_scale_vcore(vcores->iva.addr, vcores->iva.value, vcores->iva.pmic);
+ /* Configure IVA ABB LDO after scale */
+ abb_setup(vcores->iva.efuse.reg,
+ (*ctrl)->control_wkup_ldovbb_iva_voltage_ctrl,
+ (*prcm)->prm_abbldo_iva_setup,
+ (*prcm)->prm_abbldo_iva_ctrl,
+ (*prcm)->prm_irqstatus_mpu,
+ vcores->iva.abb_tx_done_mask,
+ OMAP_ABB_FAST_OPP);
/* Might need udelay(1000) here if debug is enabled to see all prints */
#else
u32 val;
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index dfb1df6bce30786fbc7089bfaca8323d24402c89..88e8920bad31294f5b564b9c275a5e3d26c08a2f 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -377,12 +377,14 @@ struct vcores_data dra752_volts = {
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS659038_REG_ADDR_SMPS45,
.eve.pmic = &tps659038,
+ .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
.gpu.value = VDD_GPU_DRA752,
.gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS6,
.gpu.pmic = &tps659038,
+ .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
.core.value = VDD_CORE_DRA752,
.core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
@@ -395,6 +397,7 @@ struct vcores_data dra752_volts = {
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS659038_REG_ADDR_SMPS8,
.iva.pmic = &tps659038,
+ .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
};
struct vcores_data dra722_volts = {
@@ -420,18 +423,21 @@ struct vcores_data dra722_volts = {
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS65917_REG_ADDR_SMPS3,
.gpu.pmic = &tps659038,
+ .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
.eve.value = VDD_EVE_DRA72x,
.eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS65917_REG_ADDR_SMPS3,
.eve.pmic = &tps659038,
+ .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
.iva.value = VDD_IVA_DRA72x,
.iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS65917_REG_ADDR_SMPS3,
.iva.pmic = &tps659038,
+ .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
};
/*
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index d126a3223192922d63e9ffc0beeea8c75fe9bf05..655e92ba276575e2c8dbc85f3a3ca7f10c35b467 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -446,6 +446,9 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
.control_emif1_sdram_config_ext = 0x4AE0C144,
.control_emif2_sdram_config_ext = 0x4AE0C148,
.control_wkup_ldovbb_mpu_voltage_ctrl = 0x4AE0C158,
+ .control_wkup_ldovbb_iva_voltage_ctrl = 0x4A002470,
+ .control_wkup_ldovbb_eve_voltage_ctrl = 0x4A00246C,
+ .control_wkup_ldovbb_gpu_voltage_ctrl = 0x4AE0C154,
.control_std_fuse_die_id_0 = 0x4AE0C200,
.control_std_fuse_die_id_1 = 0x4AE0C208,
.control_std_fuse_die_id_2 = 0x4AE0C20C,
@@ -831,6 +834,7 @@ struct prcm_regs const dra7xx_prcm = {
.cm_ipu_i2c5_clkctrl = 0x4a005578,
/* prm irqstatus regs */
+ .prm_irqstatus_mpu = 0x4ae06010,
.prm_irqstatus_mpu_2 = 0x4ae06014,
/* cm2.ckgen */
@@ -999,6 +1003,12 @@ struct prcm_regs const dra7xx_prcm = {
.prm_abbldo_mpu_setup = 0x4AE07DDC,
.prm_abbldo_mpu_ctrl = 0x4AE07DE0,
+ .prm_abbldo_iva_setup = 0x4AE07E34,
+ .prm_abbldo_iva_ctrl = 0x4AE07E24,
+ .prm_abbldo_eve_setup = 0x4AE07E30,
+ .prm_abbldo_eve_ctrl = 0x4AE07E20,
+ .prm_abbldo_gpu_setup = 0x4AE07DE4,
+ .prm_abbldo_gpu_ctrl = 0x4AE07DE8,
/*l3main1 edma*/
.cm_l3main1_tptc1_clkctrl = 0x4a008778,
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index cfec5b063c213b162663f57ccf6d041d134db1f5..2fd5cda6238f431e207372c0857d1b89f679b7c7 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -216,6 +216,9 @@ struct s32ktimer {
/* ABB tranxdone mask */
#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7)
#define OMAP_ABB_MM_TXDONE_MASK (0x1 << 31)
+#define OMAP_ABB_IVA_TXDONE_MASK (0x1 << 30)
+#define OMAP_ABB_EVE_TXDONE_MASK (0x1 << 29)
+#define OMAP_ABB_GPU_TXDONE_MASK (0x1 << 28)
/* ABB efuse masks */
#define OMAP5_ABB_FUSE_VSET_MASK (0x1F << 24)
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 14c07fab34abf6ccbf2323351c1d41d32be3a602..8fb05e18b93fce6db629ca4a93f496ce828d4c3c 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -324,6 +324,12 @@ struct prcm_regs {
u32 prm_abbldo_mpu_ctrl;
u32 prm_abbldo_mm_setup;
u32 prm_abbldo_mm_ctrl;
+ u32 prm_abbldo_iva_setup;
+ u32 prm_abbldo_iva_ctrl;
+ u32 prm_abbldo_eve_setup;
+ u32 prm_abbldo_eve_ctrl;
+ u32 prm_abbldo_gpu_setup;
+ u32 prm_abbldo_gpu_ctrl;
u32 cm_div_m4_dpll_core;
u32 cm_div_m5_dpll_core;
@@ -445,6 +451,9 @@ struct omap_sys_ctrl_regs {
u32 control_emif2_sdram_config_ext;
u32 control_wkup_ldovbb_mpu_voltage_ctrl;
u32 control_wkup_ldovbb_mm_voltage_ctrl;
+ u32 control_wkup_ldovbb_iva_voltage_ctrl;
+ u32 control_wkup_ldovbb_eve_voltage_ctrl;
+ u32 control_wkup_ldovbb_gpu_voltage_ctrl;
u32 control_smart1nopmio_padconf_0;
u32 control_smart1nopmio_padconf_1;
u32 control_padconf_mode;
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 2404eb586757f9c225246cae37ee7e4a9d7e498c..86b8f6e8951ab49c2ca312c101e61b0b8ad6b02f 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -228,12 +228,14 @@ struct vcores_data beagle_x15_volts = {
.eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.eve.addr = TPS659038_REG_ADDR_SMPS45,
.eve.pmic = &tps659038,
+ .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
.gpu.value = VDD_GPU_DRA752,
.gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
.gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.gpu.addr = TPS659038_REG_ADDR_SMPS45,
.gpu.pmic = &tps659038,
+ .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
.core.value = VDD_CORE_DRA752,
.core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
@@ -246,6 +248,7 @@ struct vcores_data beagle_x15_volts = {
.iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
.iva.addr = TPS659038_REG_ADDR_SMPS45,
.iva.pmic = &tps659038,
+ .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
};
#ifdef CONFIG_SPL_BUILD