From bfb66bb71dba5b1fedb15ca043ed3207abd110fd Mon Sep 17 00:00:00 2001
From: Troy Kisky <troy.kisky@boundarydevices.com>
Date: Thu, 24 Jan 2019 16:53:12 -0800
Subject: [PATCH] nitrogen8m_som: initial addition
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
arch/arm/dts/imx8mq-nitrogen8m_som.dts | 1377 +++++++++++++++++
arch/arm/mach-imx/imx8m/Kconfig | 6 +
board/boundary/nitrogen8m_som/Kconfig | 14 +
board/boundary/nitrogen8m_som/Makefile | 12 +
board/boundary/nitrogen8m_som/lpddr4_timing.c | 1262 +++++++++++++++
board/boundary/nitrogen8m_som/mmc.c | 25 +
.../boundary/nitrogen8m_som/nitrogen8m_som.c | 403 +++++
board/boundary/nitrogen8m_som/spl.c | 226 +++
configs/nitrogen8m_som_2g_defconfig | 94 ++
include/configs/nitrogen8m_som.h | 259 ++++
10 files changed, 3678 insertions(+)
create mode 100644 arch/arm/dts/imx8mq-nitrogen8m_som.dts
create mode 100644 board/boundary/nitrogen8m_som/Kconfig
create mode 100644 board/boundary/nitrogen8m_som/Makefile
create mode 100644 board/boundary/nitrogen8m_som/lpddr4_timing.c
create mode 100644 board/boundary/nitrogen8m_som/mmc.c
create mode 100644 board/boundary/nitrogen8m_som/nitrogen8m_som.c
create mode 100644 board/boundary/nitrogen8m_som/spl.c
create mode 100644 configs/nitrogen8m_som_2g_defconfig
create mode 100644 include/configs/nitrogen8m_som.h
diff --git a/arch/arm/dts/imx8mq-nitrogen8m_som.dts b/arch/arm/dts/imx8mq-nitrogen8m_som.dts
new file mode 100644
index 00000000000..8f25b2c670a
--- /dev/null
+++ b/arch/arm/dts/imx8mq-nitrogen8m_som.dts
@@ -0,0 +1,1377 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2018 Boundary Devices
+ */
+
+/dts-v1/;
+
+#include "fsl-imx8mq.dtsi"
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ iomuxc_pinctrl: iomuxc-pinctrlgrp {
+ };
+};
+
+&iomuxc_pinctrl {
+ pinctrl_bt_rfkill: bt-rfkillgrp {
+ fsl,pins = <
+#define GP_BT_RFKILL_RESET <&gpio3 19 GPIO_ACTIVE_LOW>
+ MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ /* unused on our carrier */
+#define GP_ECSPI2_CS0 <&gpio5 13 GPIO_ACTIVE_LOW>
+ MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 /* Pin 89 */
+ MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x19 /* Pin 91 */
+ MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x19 /* Pin 93 */
+ MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x19 /* Pin 97 */
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
+ MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+#define GP_FEC1_RESET <&gpio1 9 GPIO_ACTIVE_LOW>
+ MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
+#define GPIRQ_FEC1_PHY <&gpio1 11 IRQ_TYPE_LEVEL_LOW>
+ MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59
+ >;
+ };
+
+ pinctrl_gpio_keys: gpio-keysgrp {
+ fsl,pins = <
+#define GP_GPIOKEY_POWER <&gpio1 7 GPIO_ACTIVE_LOW>
+ MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 /* Pin 139 */
+ >;
+ };
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ /* J1 connector, odd */
+ MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* Pin 105 */
+ MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* Pin 143 */
+ MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* Pin 145 */
+ MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* Pin 149 */
+ MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* Pin 153 */
+ MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* Pin 155 */
+ MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* Pin 157 */
+
+ /* J1 connector, even */
+ MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* Pin 82 */
+ MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* Pin 84 */
+ MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 /* Pin 86 */
+ MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 /* Pin 88 */
+ MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19 /* Pin 90 */
+ MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x19 /* Pin 92 */
+ MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 /* Pin 96 */
+ MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x19 /* Pin 132 */
+ MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 /* Pin 134 */
+ MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* Pin 136 */
+ MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 /* Pin 138 */
+ MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 /* Pin 140 */
+ MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* Pin 142 */
+ MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* Pin 144 */
+ MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x19 /* Pin 146 */
+ MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* Pin 148 */
+ MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* Pin 150 */
+ MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* Pin 152 */
+ MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19 /* Pin 154 */
+ MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19 /* Pin 156 */
+ MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19 /* Pin 158 */
+ MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 /* Pin 160 */
+ MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* Pin 162 */
+ MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 /* Pin 198 */
+ MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 /* Pin 200 */
+
+ /* J13 Pin 2, BT_FUNC5 (TiWI only) */
+ MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0xd6
+ /* J13 Pin 4, WL_IRQ, not needed for Silex */
+ MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0xd6
+ /* J13 pin 9, unused */
+ MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
+ /* J13 Pin 41, BT_CLK_REQ */
+ MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0xd6
+ /* J13 Pin 42, BT_HOST_WAKE */
+ MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0xd6
+ MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 /* TP79 */
+ MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49 /* TP80 */
+
+ /* Clock for both CSI1 and CSI2 */
+ MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x07
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c1_pca9546: i2c1-pca9546grp {
+ fsl,pins = <
+#define GP_I2C1_PCA9546_RESET <&gpio1 4 GPIO_ACTIVE_LOW>
+ MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x49
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c2_csi1: i2c2-csi1grp {
+ fsl,pins = <
+#define GP_CSI1_MIPI_PWDN <&gpio3 3 GPIO_ACTIVE_HIGH>
+ MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x61
+#define GP_CSI1_MIPI_RESET <&gpio3 17 GPIO_ACTIVE_LOW>
+ MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x61
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c3_csi2: i2c3-csi2grp {
+ fsl,pins = <
+#define GP_CSI2_MIPI_PWDN <&gpio3 2 GPIO_ACTIVE_HIGH>
+ MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x61
+#define GP_CSI2_MIPI_RESET <&gpio2 19 GPIO_ACTIVE_LOW>
+ MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x61
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c4_gt911: i2c4-gt911grp {
+ fsl,pins = <
+#define GPIRQ_GT911 <&gpio3 12 IRQ_TYPE_LEVEL_HIGH>
+#define GP_GT911_IRQ <&gpio3 12 GPIO_ACTIVE_HIGH>
+ MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0xd6
+ /* driver writes levels, instead of active/inactive */
+#define GP_GT911_RESET <&gpio3 13 GPIO_ACTIVE_HIGH>
+ MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x49
+ >;
+ };
+
+ pinctrl_i2c4_ft5x06: i2c4-ft5x06grp {
+ fsl,pins = <
+#define GPIRQ_I2C4_FT5X06 <&gpio3 12 IRQ_TYPE_EDGE_FALLING>
+#define GP_I2C4_FT5X06_WAKE <&gpio3 12 GPIO_ACTIVE_LOW>
+ MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x49
+#define GP_I2C4_FT5X06_RESET <&gpio3 13 GPIO_ACTIVE_LOW>
+ MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x49
+ >;
+ };
+
+ pinctrl_i2c4_st1633: i2c4-st1633grp {
+ fsl,pins = <
+#define GPIRQ_ST1633 <&gpio3 12 IRQ_TYPE_EDGE_FALLING>
+#define GP_ST1633_IRQ <&gpio3 12 GPIO_ACTIVE_LOW>
+ MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0xd6
+#define GP_ST1633_RESET <&gpio3 13 GPIO_ACTIVE_LOW>
+ MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x49
+ >;
+ };
+
+ pinctrl_i2c4_sn65dsi83: i2c4-sn65dsi83grp {
+ fsl,pins = <
+#define GPIRQ_I2C4_SN65DSI83 <&gpio1 1 IRQ_TYPE_LEVEL_HIGH>
+ MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x04
+#define GP_I2C4_SN65DSI83_EN <&gpio3 15 GPIO_ACTIVE_HIGH>
+ MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x06
+ >;
+ };
+
+ pinctrl_i2c4_pca9546: i2c4-pca9546grp {
+ fsl,pins = <
+#define GP_I2C4_PCA9546_RESET <&gpio3 5 GPIO_ACTIVE_LOW>
+ MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x49 /* Pin 151 */
+ >;
+ };
+
+ pinctrl_i2c4b_wm8960: i2c4b-wm8960grp {
+ fsl,pins = <
+#define GP_WM8960_HP_DET <&gpio3 14 GPIO_ACTIVE_HIGH>
+ MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* Pin 53 */
+ >;
+ };
+
+ pinctrl_i2c4d_rv4162: i2c4d-rv4162grp {
+ fsl,pins = <
+#define GPIRQ_RV4162 <&gpio1 6 IRQ_TYPE_LEVEL_LOW>
+ MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x49
+ >;
+ };
+
+ pinctrl_lcm_jm430: lcm-jm430grp {
+ fsl,pins = <
+#define GP_TC358762_EN <&gpio3 15 GPIO_ACTIVE_HIGH>
+ MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16
+ >;
+ };
+
+ pinctrl_ltk0680ytmdb: ltk0680ytmdbgrp {
+ fsl,pins = <
+#define GP_MIPI_RESET <&gpio1 1 GPIO_ACTIVE_LOW>
+ MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16
+ >;
+ };
+
+ pinctrl_ltk080a60a004t: ltk080a60a004tgrp {
+ fsl,pins = <
+#define GP_LTK08_MIPI_EN <&gpio1 1 GPIO_ACTIVE_HIGH>
+ MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16
+ >;
+ };
+
+ pinctrl_pcie0: pcie0grp {
+ fsl,pins = <
+#define GP_PCIE0_RESET <&gpio5 7 GPIO_ACTIVE_LOW>
+ MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x16
+#define GP_PCIE0_DISABLE <&gpio5 6 GPIO_ACTIVE_LOW>
+ MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x16
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x16
+ >;
+ };
+
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x16
+ >;
+ };
+
+ pinctrl_reg_arm_dram: reg-arm-dram {
+ fsl,pins = <
+#define GP_ARM_DRAM_VSEL <&gpio3 24 GPIO_ACTIVE_HIGH>
+ MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16
+ >;
+ };
+
+ pinctrl_reg_dram_1p1v: reg-dram-1p1v {
+ fsl,pins = <
+#define GP_DRAM_1P1_VSEL <&gpio2 11 GPIO_ACTIVE_HIGH>
+ MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x16
+ >;
+ };
+
+ pinctrl_reg_soc_gpu_vpu: reg-soc-gpu-vpu {
+ fsl,pins = <
+#define GP_SOC_GPU_VPU_VSEL <&gpio2 20 GPIO_ACTIVE_HIGH>
+ MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x16
+ >;
+ };
+
+ pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp {
+ fsl,pins = <
+#define GP_REG_USB_OTG_VBUS <&gpio1 12 GPIO_ACTIVE_HIGH>
+ MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x16
+ >;
+ };
+
+ pinctrl_reg_wlan_vmmc: reg-wlan-vmmcgrp {
+ fsl,pins = <
+#define GP_REG_WLAN_VMMC <&gpio3 20 GPIO_ACTIVE_HIGH>
+ MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x16
+ >;
+ };
+
+ pinctrl_sai1: sai1grp {
+ fsl,pins = <
+ /* wm8960 */
+ MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6
+ MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6
+ MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6
+ MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6
+ MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6
+ >;
+ };
+
+ pinctrl_sai2: sai2grp {
+ fsl,pins = <
+ /* our carrier, unused */
+ MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 /* Pin 166 */
+ MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0xd6 /* Pin 168 */
+ MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 /* Pin 170 */
+ MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 /* Pin 172 */
+ MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0xd6 /* Pin 174 */
+ MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 /* Pin 176 */
+ MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 /* Pin 168 */
+ >;
+ };
+
+ pinctrl_sai3: sai3grp {
+ fsl,pins = <
+ /* Bluetooth PCM */
+ MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
+ MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
+ MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
+ MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45
+ MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45
+ MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x45
+ MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x45
+ MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x45
+ MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x45
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x45
+ MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x45
+ >;
+ };
+
+ pinctrl_usb3_0: usb3-0grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x16
+ >;
+ };
+
+ pinctrl_usb3_1: usb3-1grp {
+ fsl,pins = <
+#define GP_USB3_1_HUB_RESET <&gpio1 14 GPIO_ACTIVE_LOW>
+ MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
+#if 0
+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
+#else
+#define GP_EMMC_RESET <&gpio2 10 GPIO_ACTIVE_LOW>
+ MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
+#endif
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x03
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
+ /* Bluetooth slow clock */
+ MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x03
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x0d
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x1e
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xce
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xce
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xce
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xce
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xce
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
+
+/ {
+ model = "Boundary Devices i.MX8MQ Nitrogen8M_som";
+ compatible = "boundary,imx8mq-nitrogen8m_som", "fsl,imx8mq";
+
+#if 0
+ aliases {
+ backlight_mipi = &backlight_mipi;
+ dcss = &dcss;
+ fb_mipi = &fb_mipi;
+ fb_hdmi = &hdmi;
+ lcdif = &lcdif;
+ mipi = &fb_mipi;
+ mipi_cmds_lcm_jm430 = &mipi_cmds_lcm_jm430;
+ mipi_cmds_ltk0680ytmdb = &mipi_cmds_ltk0680ytmdb;
+ mipi_cmds_ltk080a60a004t = &mipi_cmds_ltk080a60a004t;
+ mipi_cmds_m101nwwb = &mipi_cmds_ltk080a60a004t; /* Same commands work for both */
+ mipi_dsi = &mipi_dsi;
+ mipi_dsi_bridge = &mipi_dsi_bridge;
+ mipi_dsi_phy = &mipi_dsi_phy;
+ mipi_to_lvds = &mipi_to_lvds;
+ pinctrl_lcm_jm430 = &pinctrl_lcm_jm430;
+ pinctrl_ltk0680ytmdb = &pinctrl_ltk0680ytmdb;
+ pinctrl_ltk080a60a004t = &pinctrl_ltk080a60a004t;
+ sound_hdmi = &sound_hdmi;
+ t_mipi = &t_mipi;
+ };
+
+ alias_create_phandles {
+ p1 = <&mipi_cmds_lcm_jm430>;
+ p2 = <&mipi_cmds_ltk0680ytmdb>;
+ p3 = <&mipi_cmds_ltk080a60a004t>;
+ p4 = <&mipi_to_lvds>;
+ p5 = <&pinctrl_lcm_jm430>;
+ p6 = <&pinctrl_ltk0680ytmdb>;
+ p7 = <&pinctrl_ltk080a60a004t>;
+ };
+
+ backlight_mipi: backlight-mipi {
+ brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>;
+ compatible = "pwm-backlight";
+ default-brightness-level = <8>;
+ display = <&lcdif>;
+ pwms = <&pwm3 0 30000>; /* 33.3 Khz */
+ status = "disabled";
+ };
+#endif
+
+ bt-rfkill {
+ compatible = "net,rfkill-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_bt_rfkill>;
+ name = "bt-rfkill";
+ type = <2>; /* Bluetooth */
+ reset-gpios = GP_BT_RFKILL_RESET;
+ status = "okay";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ power {
+ label = "Power Button";
+ gpios = GP_GPIOKEY_POWER;
+ linux,code = <KEY_POWER>;
+ gpio-key,wakeup;
+ };
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usbotg_vbus>;
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = GP_REG_USB_OTG_VBUS;
+ enable-active-high;
+ };
+
+ reg_vref_0v9: regulator-vref-0v9 {
+ compatible = "regulator-fixed";
+ regulator-name = "vref-0v9";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ };
+
+ reg_vref_1v8: regulator-vref-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "vref-1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ reg_vref_2v5: regulator-vref-2v5 {
+ compatible = "regulator-fixed";
+ regulator-name = "vref-2v5";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ };
+
+ reg_vref_3v3: regulator-vref-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vref-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_vref_5v: regulator-vref-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vref-5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_wlan_vmmc: regulator-wlan-vmmc {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_wlan_vmmc>;
+ regulator-name = "reg_wlan_vmmc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = GP_REG_WLAN_VMMC;
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+#if 0
+ sound-wm8960 {
+ compatible = "fsl,imx-audio-wm8960";
+ model = "wm8960-audio";
+ cpu-dai = <&sai1>;
+ codec-master;
+ audio-codec = <&wm8960>;
+ audio-routing =
+ "Headphone Jack", "HP_L",
+ "Headphone Jack", "HP_R",
+ "Ext Spk", "SPK_LP",
+ "Ext Spk", "SPK_LN",
+ "Ext Spk", "SPK_RP",
+ "Ext Spk", "SPK_RN",
+ "LINPUT1", "Main MIC",
+ "Main MIC", "MICB";
+ /* JD2: hp detect high for headphone*/
+ hp-det = <2 0>;
+ hp-det-gpios = GP_WM8960_HP_DET;
+ };
+
+ sound_hdmi: sound-hdmi {
+ compatible = "fsl,imx-audio-cdnhdmi";
+ model = "imx-audio-hdmi";
+ audio-cpu = <&sai4>;
+ constraint-rate = <32000 44100 48000 96000 192000>;
+ protocol = <1>;
+ status = "okay";
+ };
+#endif
+};
+
+&A53_0 {
+ operating-points = <
+ /* kHz uV */
+ 1500000 1000000
+ 1300000 1000000
+ 1000000 900000
+ 800000 900000
+ >;
+};
+
+&clk {
+ assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>;
+ assigned-clock-rates = <786432000>, <722534400>;
+};
+
+#if 0
+&csi1_bridge {
+ fsl,mipi-mode;
+ fsl,two-8bit-sensor-mode;
+ status = "okay";
+
+ port {
+ csi1_ep: endpoint {
+ remote-endpoint = <&csi1_mipi_ep>;
+ };
+ };
+};
+
+&csi2_bridge {
+ fsl,mipi-mode;
+ fsl,two-8bit-sensor-mode;
+ status = "okay";
+
+ port {
+ csi2_ep: endpoint {
+ remote-endpoint = <&csi2_mipi_ep>;
+ };
+ };
+};
+
+&dcss {
+ status = "okay";
+ disp-dev = "hdmi_disp";
+};
+
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = GP_ECSPI2_CS0;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ spidev@0 {
+ compatible = "spidev";
+ spi-max-frequency = <2000000>;
+ reg = <0>;
+ };
+};
+#endif
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+#if 0
+ phy-reset-gpios = GP_FEC1_RESET;
+#endif
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <4>;
+ interrupts-extended = GPIRQ_FEC1_PHY;
+ };
+ };
+};
+
+#if 0
+&gpu {
+#if 0
+ clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
+ <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
+ <&clk IMX8MQ_CLK_GPU_AXI_DIV>,
+ <&clk IMX8MQ_CLK_GPU_AHB_DIV>;
+ clock-names = "gpu3d_clk", "gpu3d_shader_clk", "gpu3d_axi_clk", "gpu3d_ahb_clk";
+ assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
+ <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
+ <&clk IMX8MQ_CLK_GPU_AXI_SRC>,
+ <&clk IMX8MQ_CLK_GPU_AHB_SRC>;
+ assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
+ <&clk IMX8MQ_SYS2_PLL_1000M>,
+ <&clk IMX8MQ_GPU_PLL_OUT>,
+ <&clk IMX8MQ_GPU_PLL_OUT>;
+ assigned-clock-rates = <800000000>,
+ <1000000000>,
+ <800000000>,
+ <800000000>;
+#endif
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+#endif
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ i2cmux@70 {
+ compatible = "pca9546";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_pca9546>;
+ reg = <0x70>;
+ reset-gpios = GP_I2C1_PCA9546_RESET;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c1a: i2c1@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1b: i2c1@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1c: i2c1@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1d: i2c1@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&i2c1a {
+ reg_arm_dram: fan53555@60 {
+ compatible = "fcs,fan53555";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_arm_dram>;
+ reg = <0x60>;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ vsel-gpios = GP_ARM_DRAM_VSEL;
+ };
+};
+
+&i2c1b {
+ reg_dram_1p1v: fan53555@60 {
+ compatible = "fcs,fan53555";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_dram_1p1v>;
+ reg = <0x60>;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ vsel-gpios = GP_DRAM_1P1_VSEL;
+ };
+};
+
+&i2c1c {
+ reg_soc_gpu_vpu: fan53555@60 {
+ compatible = "fcs,fan53555";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>;
+ reg = <0x60>;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ vsel-gpios = GP_SOC_GPU_VPU_VSEL;
+ };
+};
+
+&i2c1d {
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+#if 0
+ ov5640-mipi1@3c {
+ compatible = "ov5640_mipisubdev";
+ reg = <0x3c>;
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2_csi1>;
+ clocks = <&clk IMX8MQ_CLK_CLKO2_DIV>;
+ clock-names = "csi_mclk";
+ assigned-clocks = <&clk IMX8MQ_CLK_CLKO2_SRC>,
+ <&clk IMX8MQ_CLK_CLKO2_DIV>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>;
+ assigned-clock-rates = <0>, <25000000>;
+ csi_id = <0>;
+ AVDD-supply = <®_vref_2v5>;
+ DVDD-supply = <®_vref_3v3>;
+ DOVDD-supply = <®_vref_1v8>;
+ pwn-gpios = GP_CSI1_MIPI_PWDN;
+ rst-gpios = GP_CSI1_MIPI_RESET;
+ mclk = <25000000>;
+ mipi_csi;
+
+ port {
+ ov5640_mipi1_ep: endpoint {
+ remote-endpoint = <&mipi1_sensor_ep>;
+ };
+ };
+ };
+#endif
+
+ pcie-clock@6a {
+ compatible = "idt,9FGV0241AKILF";
+ /* TODO */
+ reg = <0x6a>;
+ };
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+#if 0
+ ov5640-mipi2@3c {
+ compatible = "ov5640_mipisubdev";
+ reg = <0x3c>;
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3_csi2>;
+ clocks = <&clk IMX8MQ_CLK_CLKO2_DIV>;
+ clock-names = "csi_mclk";
+ assigned-clocks = <&clk IMX8MQ_CLK_CLKO2_SRC>,
+ <&clk IMX8MQ_CLK_CLKO2_DIV>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>;
+ assigned-clock-rates = <0>, <25000000>;
+ csi_id = <1>;
+ AVDD-supply = <®_vref_2v5>;
+ DVDD-supply = <®_vref_3v3>;
+ DOVDD-supply = <®_vref_1v8>;
+ pwn-gpios = GP_CSI2_MIPI_PWDN;
+ rst-gpios = GP_CSI2_MIPI_RESET;
+ mclk = <25000000>;
+ mipi_csi;
+
+ port {
+ ov5640_mipi2_ep: endpoint {
+ remote-endpoint = <&mipi2_sensor_ep>;
+ };
+ };
+ };
+#endif
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ touchscreen@5d {
+ compatible = "goodix,gt9271";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4_gt911>;
+ reg = <0x5d>;
+ esd-recovery-timeout-ms = <2000>;
+ interrupts-extended = GPIRQ_GT911;
+ irq-gpios = GP_GT911_IRQ;
+ reset-gpios = GP_GT911_RESET;
+ };
+
+#if 0
+ mipi_to_lvds: mipi-to-lvds@2c {
+ clocks = <&mipi_dsi_phy 0>;
+ clock-names = "mipi_clk";
+ compatible = "ti,sn65dsi83";
+ display = <&lcdif>;
+ display-dsi = <&fb_mipi>;
+ enable-gpios = GP_I2C4_SN65DSI83_EN;
+ interrupts-extended = GPIRQ_I2C4_SN65DSI83;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4_sn65dsi83>;
+ reg = <0x2c>;
+ status = "disabled";
+ };
+#endif
+
+ touchscreen@38 {
+ compatible = "ft5x06-ts";
+ interrupts-extended = GPIRQ_I2C4_FT5X06;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4_ft5x06>;
+ reg = <0x38>;
+ wakeup-gpios = GP_I2C4_FT5X06_WAKE;
+ reset-gpios = GP_I2C4_FT5X06_RESET;
+ };
+
+ touchscreen@55 {
+ compatible = "sitronix,st1633i";
+ reg = <0x55>;
+ interrupts-extended = GPIRQ_ST1633;
+ /* pins used by touchscreen */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4_st1633>;
+ reset-gpios = GP_ST1633_RESET;
+
+ wakeup-gpios = GP_ST1633_IRQ;
+ };
+
+ i2cmux@70 {
+ compatible = "pca9546";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4_pca9546>;
+ reg = <0x70>;
+ reset-gpios = GP_I2C4_PCA9546_RESET;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c4a: i2c4@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c4b: i2c4@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c4c: i2c4@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c4d: i2c4@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&i2c4a {
+ /* pciei */
+};
+
+&i2c4b {
+ wm8960: codec@1a {
+ compatible = "wlf,wm8960";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4b_wm8960>;
+ reg = <0x1a>;
+ clocks = <&clk IMX8MQ_CLK_SAI1_ROOT>;
+ clock-names = "mclk";
+ wlf,shared-lrclk;
+ };
+};
+
+&i2c4c {
+ /* unused */
+};
+
+&i2c4d {
+ rtc@68 {
+ compatible = "microcrystal,rv4162";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4d_rv4162>;
+ reg = <0x68>;
+ interrupts-extended = GPIRQ_RV4162;
+ wakeup-source;
+ };
+};
+
+#if 0
+&lcdif {
+ status = "disabled";
+ assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_SRC>,
+ <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>;
+ assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
+ <&clk IMX8MQ_CLK_25M>;
+ max-res = <1920>, <1920>;
+
+ port@0 {
+ lcdif_mipi_dsi: mipi-dsi-endpoint {
+ remote-endpoint = <&mipi_dsi_in>;
+ };
+ };
+};
+
+&mipi_csi_1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ port {
+ mipi1_sensor_ep: endpoint1 {
+ remote-endpoint = <&ov5640_mipi1_ep>;
+ data-lanes = <1 2>;
+ };
+
+ csi1_mipi_ep: endpoint2 {
+ remote-endpoint = <&csi1_ep>;
+ };
+ };
+};
+
+&mipi_csi_2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ port {
+ mipi2_sensor_ep: endpoint1 {
+ remote-endpoint = <&ov5640_mipi2_ep>;
+ data-lanes = <1 2>;
+ };
+
+ csi2_mipi_ep: endpoint2 {
+ remote-endpoint = <&csi2_ep>;
+ };
+ };
+};
+
+&mipi_dsi_phy {
+ status = "disabled";
+};
+
+&mipi_dsi {
+ status = "disabled";
+ as_bridge;
+ assigned-clocks = <&clk IMX8MQ_CLK_DSI_CORE_SRC>,
+ <&clk IMX8MQ_CLK_DSI_PHY_REF_SRC>,
+ <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
+ <&clk IMX8MQ_VIDEO_PLL1_OUT>,
+ <&clk IMX8MQ_CLK_25M>;
+ assigned-clock-rates = <266000000>;
+
+ clocks = <&clk IMX8MQ_CLK_DSI_CORE_DIV>,
+ <&clk IMX8MQ_CLK_DSI_PHY_REF_DIV>,
+ <&clk IMX8MQ_VIDEO_PLL1>;
+ clock-names = "core", "phy_ref", "pixel_pll";
+
+ port@1 {
+ mipi_dsi_in: endpoint {
+ remote-endpoint = <&lcdif_mipi_dsi>;
+ };
+ };
+};
+
+&mipi_dsi_bridge {
+ status = "disabled";
+
+ fb_mipi: panel@0 {
+ bits-per-color = <8>;
+ bridge-de-active = <0>;
+ bridge-sync-active = <1>;
+ bus-format = "rgb888";
+ compatible = "panel,simple";
+ dsi-format = "rgb888";
+ dsi-lanes = <4>;
+ mode-skip-eot;
+ mode-video;
+ mode-video-burst;
+ panel-height-mm = <136>;
+ panel-width-mm = <217>;
+ power-supply = <®_vref_5v>;
+ reg = <0>;
+ spwg;
+
+ display-timings {
+ t_mipi: t-dsi-default {
+ /* m101nwwb by default */
+ clock-frequency = <70000000>;
+ hactive = <1280>;
+ vactive = <800>;
+ hback-porch = <5>;
+ hfront-porch = <123>;
+ vback-porch = <3>;
+ vfront-porch = <24>;
+ hsync-len = <1>;
+ vsync-len = <1>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ };
+ };
+
+ port {
+ panel1_in: endpoint {
+ remote-endpoint = <&mipi_dsi_bridge_out>;
+ };
+ };
+ };
+
+ port@1 {
+ mipi_dsi_bridge_out: endpoint {
+ remote-endpoint = <&panel1_in>;
+ };
+ };
+};
+
+&mu {
+ status = "okay";
+};
+
+&pcie0 {
+#if 1
+ clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
+ <&clk IMX8MQ_CLK_PCIE1_AUX_CG>,
+ <&clk IMX8MQ_CLK_PCIE1_PHY_CG>,
+ <&clk IMX8MQ_CLK_CLK2_CG>;
+ clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_ext_src";
+ ext_osc = <0>;
+#else
+ ext_osc = <1>;
+#endif
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0>;
+ /* TODO check clock */
+ disable-gpio = GP_PCIE0_DISABLE;
+ reset-gpio = GP_PCIE0_RESET;
+ status = "okay";
+};
+
+&pcie1 {
+ /* TODO check clock */
+ ext_osc = <1>;
+ hard-wired = <1>;
+ status = "disabled";
+};
+#endif
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
+
+#if 0
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+ status = "okay";
+};
+
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+ status = "okay";
+};
+
+&sai1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai1>;
+ assigned-clocks = <&clk IMX8MQ_CLK_SAI1_SRC>,
+ <&clk IMX8MQ_CLK_SAI1_DIV>;
+ assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <0>, <12288000>;
+ status = "okay";
+};
+
+&sai2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai2>;
+ status = "disabled";
+};
+
+&sai3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai3>;
+ status = "okay";
+};
+
+&sai4 {
+ assigned-clocks = <&clk IMX8MQ_CLK_SAI4_SRC>,
+ <&clk IMX8MQ_CLK_SAI4_DIV>;
+ assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <0>, <24576000>;
+ clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, <&clk IMX8MQ_CLK_DUMMY>,
+ <&clk IMX8MQ_CLK_SAI4_ROOT>, <&clk IMX8MQ_CLK_DUMMY>,
+ <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>,
+ <&clk IMX8MQ_AUDIO_PLL2_OUT>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
+ status = "okay";
+};
+#endif
+
+#if 0
+&uart1 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>;
+ assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ assigned-clocks = <&clk IMX8MQ_CLK_UART2_SRC>;
+ assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ assigned-clocks = <&clk IMX8MQ_CLK_UART4_SRC>;
+ assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
+ status = "okay";
+};
+#endif
+
+&usb3_phy0 {
+ status = "okay";
+};
+
+&usb3_0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb3_0>;
+ status = "okay";
+};
+
+&usb_dwc3_0 {
+#if 0
+ status = "okay";
+#endif
+ dr_mode = "otg";
+ vbus-supply = <®_usb_otg_vbus>;
+};
+
+&usb3_phy1 {
+ status = "okay";
+};
+
+&usb3_1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb3_1>;
+ reset-gpios = GP_USB3_1_HUB_RESET;
+ status = "okay";
+};
+
+&usb_dwc3_1 {
+#if 0
+ status = "okay";
+#endif
+ dr_mode = "host";
+};
+
+&usdhc1 {
+ bus-width = <8>;
+ fsl,strobe-dll-delay-target = <5>;
+ fsl,tuning-start-tap = <63>;
+ fsl,tuning-step = <2>;
+ no-mmc-hs400;
+ non-removable;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ status = "okay";
+ vmmc-supply = <®_vref_1v8>;
+ vqmmc-1-8-v;
+};
+
+#if 0
+&usdhc2 {
+ bus-width = <4>;
+ fsl,tuning-start-tap = <70>;
+ fsl,tuning-step = <2>;
+ no-sd-uhs-sdr104;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ non-removable;
+ status = "okay";
+ tuning-delay = <32>;
+ tuning-mode = <1>;
+ vmmc-supply = <®_wlan_vmmc>;
+ vqmmc-1-8-v;
+};
+
+&vpu {
+ regulator-supply = <®_vref_0v9>;
+ status = "okay";
+};
+#endif
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 5661df07272..01d388394c0 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -21,6 +21,11 @@ config TARGET_NITROGEN8M
select IMX8MQ
select SUPPORT_SPL
+config TARGET_NITROGEN8M_SOM
+ bool "nitrogen8m_som"
+ select IMX8MQ
+ select SUPPORT_SPL
+
config TARGET_IMX8MM_EVK
bool "imx8mm_evk"
select IMX8MM
@@ -32,5 +37,6 @@ config SYS_SOC
default "imx8m"
source "board/boundary/nitrogen8m/Kconfig"
+source "board/boundary/nitrogen8m_som/Kconfig"
source "board/freescale/imx8mm_evk/Kconfig"
endif
diff --git a/board/boundary/nitrogen8m_som/Kconfig b/board/boundary/nitrogen8m_som/Kconfig
new file mode 100644
index 00000000000..3d71f9e0251
--- /dev/null
+++ b/board/boundary/nitrogen8m_som/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_NITROGEN8M_SOM
+
+config SYS_BOARD
+ default "nitrogen8m_som"
+
+config SYS_VENDOR
+ default "boundary"
+
+config SYS_CONFIG_NAME
+ default "nitrogen8m_som"
+
+source "board/boundary/common/Kconfig"
+
+endif
diff --git a/board/boundary/nitrogen8m_som/Makefile b/board/boundary/nitrogen8m_som/Makefile
new file mode 100644
index 00000000000..7c271d6192a
--- /dev/null
+++ b/board/boundary/nitrogen8m_som/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2016 Freescale Semiconductor
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += nitrogen8m_som.o mmc.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-y += lpddr4_timing.o
+endif
diff --git a/board/boundary/nitrogen8m_som/lpddr4_timing.c b/board/boundary/nitrogen8m_som/lpddr4_timing.c
new file mode 100644
index 00000000000..ac02c88e6c9
--- /dev/null
+++ b/board/boundary/nitrogen8m_som/lpddr4_timing.c
@@ -0,0 +1,1262 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <config.h>
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/ddr_memory_map.h>
+#include <asm/arch/lpddr4_define.h>
+#include <asm/arch/imx8m_ddr.h>
+
+#define LPDDR4_CS 0x3 /* 2 ranks */
+#define DDR_BOOT_P1 /* default DDR boot frequency point */
+
+#define WR_POST_EXT_3200
+#ifdef WR_POST_EXT_3200 // recommend to define
+#define VAL_INIT4 ((LPDDR4_MR3 << 16) | 0x00020008)
+#else
+#define VAL_INIT4 ((LPDDR4_MR3 << 16) | 0x00000008)
+#endif
+
+#if CONFIG_DDR_MB == 2048
+#define VAL_DDRC_RFSHTMG 0x00610090
+#define VAL_DDRC_DRAMTMG14 0x00000096
+#define VAL_DDRC_FREQ1_RFSHTMG 0x0014001F
+#define VAL_DDRC_FREQ1_DRAMTMG14 0x00000020
+#define VAL_DDRC_FREQ2_RFSHTMG 0x00030005
+#define VAL_DDRC_FREQ2_DRAMTMG14 0x00000005
+ /* Address map is from MSB 28: cs, r14, r13-r0, b2-b0, c9-c0 */
+#define VAL_DDRC_ADDRMAP0 0x00000016
+#define VAL_DDRC_ADDRMAP6 0x0f070707
+#elif CONFIG_DDR_MB == 3072
+#define VAL_DDRC_RFSHTMG 0x006100E0
+#define VAL_DDRC_DRAMTMG14 0x000000E6
+#define VAL_DDRC_FREQ1_RFSHTMG 0x0014002F
+#define VAL_DDRC_FREQ1_DRAMTMG14 0x00000031
+#define VAL_DDRC_FREQ2_RFSHTMG 0x00030007
+#define VAL_DDRC_FREQ2_DRAMTMG14 0x00000008
+ /* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
+#define VAL_DDRC_ADDRMAP0 0x00000015
+#define VAL_DDRC_ADDRMAP6 0x48080707
+#elif CONFIG_DDR_MB == 4096
+#define VAL_DDRC_RFSHTMG 0x006100E0
+#define VAL_DDRC_DRAMTMG14 0x000000E6
+#define VAL_DDRC_FREQ1_RFSHTMG 0x0014002F
+#define VAL_DDRC_FREQ1_DRAMTMG14 0x00000031
+#define VAL_DDRC_FREQ2_RFSHTMG 0x00030007
+#define VAL_DDRC_FREQ2_DRAMTMG14 0x00000008
+ /* Address map is from MSB 29: cs, r15, r14, r13-r0, b2-b0, c9-c0 */
+#define VAL_DDRC_ADDRMAP0 0x00000017
+#define VAL_DDRC_ADDRMAP6 0x07070707
+#else
+#error unsupported memory size
+#endif
+
+static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
+ /* Start to config, default 3200mbps */
+ /* dis_dq=1, indicates no reads or writes are issued to SDRAM */
+ { DDRC_DBG1(0), 0x00000001 },
+ /* selfref_en=1, SDRAM enter self-refresh state */
+ { DDRC_PWRCTL(0), 0x00000001 },
+ { DDRC_MSTR(0), 0xa3080020 },
+ { DDRC_MSTR2(0), 0x00000000 },
+ { DDRC_DERATEEN(0), 0x00000203 },
+ { DDRC_DERATEINT(0), 0x0186A000 },
+ { DDRC_RFSHTMG(0), VAL_DDRC_RFSHTMG },
+ { DDRC_INIT0(0), 0xC003061C },
+ { DDRC_INIT1(0), 0x009E0000 },
+ { DDRC_INIT3(0), 0x00D4002D },
+ { DDRC_INIT4(0), VAL_INIT4 },
+ { DDRC_INIT6(0), 0x0066004A },
+ { DDRC_INIT7(0), 0x0016004A },
+
+ { DDRC_DRAMTMG0(0), 0x1A201B22 },
+ { DDRC_DRAMTMG1(0), 0x00060633 },
+ { DDRC_DRAMTMG3(0), 0x00C0C000 },
+ { DDRC_DRAMTMG4(0), 0x0F04080F },
+ { DDRC_DRAMTMG5(0), 0x02040C0C },
+ { DDRC_DRAMTMG6(0), 0x01010007 },
+ { DDRC_DRAMTMG7(0), 0x00000401 },
+ { DDRC_DRAMTMG12(0), 0x00020600 },
+ { DDRC_DRAMTMG13(0), 0x0C100002 },
+ { DDRC_DRAMTMG14(0), VAL_DDRC_DRAMTMG14 },
+ { DDRC_DRAMTMG17(0), 0x00A00050 },
+
+ { DDRC_ZQCTL0(0), 0xC3200018 },
+ { DDRC_ZQCTL1(0), 0x028061A8 },
+ { DDRC_ZQCTL2(0), 0x00000000 },
+
+ { DDRC_DFITMG0(0), 0x0497820A },
+ { DDRC_DFITMG1(0), 0x00080303 },
+ { DDRC_DFIUPD0(0), 0xE0400018 },
+ { DDRC_DFIUPD1(0), 0x00DF00E4 },
+ { DDRC_DFIUPD2(0), 0x80000000 },
+ { DDRC_DFIMISC(0), 0x00000011 },
+ { DDRC_DFITMG2(0), 0x0000170A },
+
+ { DDRC_DBICTL(0), 0x00000001 },
+ { DDRC_DFIPHYMSTR(0), 0x00000001 },
+
+ /* need be refined by ddrphy trained value */
+ { DDRC_RANKCTL(0), 0x639 },
+ { DDRC_DRAMTMG2(0), 0x070e1214 },
+
+ /* address mapping */
+ { DDRC_ADDRMAP0(0), VAL_DDRC_ADDRMAP0 },
+ { DDRC_ADDRMAP3(0), 0x00000000 },
+ /* addrmap_col_b10 and addrmap_col_b11 set to de-activated (5-bit width) */
+ { DDRC_ADDRMAP4(0), 0x00001F1F },
+ /* bank interleave */
+ /* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */
+ { DDRC_ADDRMAP1(0), 0x00080808 },
+ /* addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 */
+ { DDRC_ADDRMAP5(0), 0x07070707 },
+ /* addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 */
+ { DDRC_ADDRMAP6(0), VAL_DDRC_ADDRMAP6 },
+ { DDRC_ADDRMAP7(0), 0x00000f0f },
+
+ /* 667mts frequency setting */
+ { DDRC_FREQ1_DERATEEN(0), 0x0000001 },
+ { DDRC_FREQ1_DERATEINT(0), 0x00518B00 },
+ { DDRC_FREQ1_RFSHCTL0(0), 0x0020D040 },
+ { DDRC_FREQ1_RFSHTMG(0), VAL_DDRC_FREQ1_RFSHTMG },
+ { DDRC_FREQ1_INIT3(0), 0x00940009 },
+ { DDRC_FREQ1_INIT4(0), VAL_INIT4 },
+ { DDRC_FREQ1_INIT6(0), 0x0066004A },
+ { DDRC_FREQ1_INIT7(0), 0x0016004A },
+ { DDRC_FREQ1_DRAMTMG0(0), 0x0B070508 },
+ { DDRC_FREQ1_DRAMTMG1(0), 0x0003040B },
+ { DDRC_FREQ1_DRAMTMG2(0), 0x0305090C },
+ { DDRC_FREQ1_DRAMTMG3(0), 0x00505000 },
+ { DDRC_FREQ1_DRAMTMG4(0), 0x04040204 },
+ { DDRC_FREQ1_DRAMTMG5(0), 0x02030303 },
+ { DDRC_FREQ1_DRAMTMG6(0), 0x01010004 },
+ { DDRC_FREQ1_DRAMTMG7(0), 0x00000301 },
+ { DDRC_FREQ1_DRAMTMG12(0), 0x00020300 },
+ { DDRC_FREQ1_DRAMTMG13(0), 0x0A100002 },
+ { DDRC_FREQ1_DRAMTMG14(0), VAL_DDRC_FREQ1_DRAMTMG14 },
+ { DDRC_FREQ1_DRAMTMG17(0), 0x00220011 },
+ { DDRC_FREQ1_ZQCTL0(0), 0xC0A70006 },
+ { DDRC_FREQ1_DFITMG0(0), 0x03858202 },
+ { DDRC_FREQ1_DFITMG1(0), 0x00080303 },
+ { DDRC_FREQ1_DFITMG2(0), 0x00000502 },
+
+ /* 100mts frequency setting */
+ { DDRC_FREQ2_DERATEEN(0), 0x0000001 },
+ { DDRC_FREQ2_DERATEINT(0), 0x000C3500 },
+ { DDRC_FREQ2_RFSHCTL0(0), 0x0020D040 },
+ { DDRC_FREQ2_RFSHTMG(0), VAL_DDRC_FREQ2_RFSHTMG },
+ { DDRC_FREQ2_INIT3(0), 0x00840000 },
+ { DDRC_FREQ2_INIT4(0), VAL_INIT4 },
+ { DDRC_FREQ2_INIT6(0), 0x0066004A },
+ { DDRC_FREQ2_INIT7(0), 0x0016004A },
+ { DDRC_FREQ2_DRAMTMG0(0), 0x0A010102 },
+ { DDRC_FREQ2_DRAMTMG1(0), 0x00030404 },
+ { DDRC_FREQ2_DRAMTMG2(0), 0x0203060B },
+ { DDRC_FREQ2_DRAMTMG3(0), 0x00505000 },
+ { DDRC_FREQ2_DRAMTMG4(0), 0x02040202 },
+ { DDRC_FREQ2_DRAMTMG5(0), 0x02030202 },
+ { DDRC_FREQ2_DRAMTMG6(0), 0x01010004 },
+ { DDRC_FREQ2_DRAMTMG7(0), 0x00000301 },
+ { DDRC_FREQ2_DRAMTMG12(0), 0x00020300 },
+ { DDRC_FREQ2_DRAMTMG13(0), 0x0A100002 },
+ { DDRC_FREQ2_DRAMTMG14(0), VAL_DDRC_FREQ2_DRAMTMG14 },
+ { DDRC_FREQ2_DRAMTMG17(0), 0x00050003 },
+ { DDRC_FREQ2_ZQCTL0(0), 0xC0190004 },
+ { DDRC_FREQ2_DFITMG0(0), 0x03818200 },
+ { DDRC_FREQ2_DFITMG1(0), 0x00080303 },
+ { DDRC_FREQ2_DFITMG2(0), 0x00000100 },
+
+ /* performance setting */
+ { DDRC_ODTCFG(0), 0x0b060908 },
+ { DDRC_ODTMAP(0), 0x00000000 },
+ { DDRC_SCHED(0), 0x29001505 },
+ { DDRC_SCHED1(0), 0x0000002c },
+ { DDRC_PERFHPR1(0), 0x5900575b },
+ /* 150T starve and 0x90 max tran len */
+ { DDRC_PERFLPR1(0), 0x90000096 },
+ /* 300T starve and 0x10 max tran len */
+ { DDRC_PERFWR1(0), 0x1000012c },
+
+ { DDRC_DBG0(0), 0x00000016 },
+ { DDRC_DBG1(0), 0x00000000 },
+ { DDRC_DBGCMD(0), 0x00000000 },
+ { DDRC_SWCTL(0), 0x00000001 },
+ { DDRC_POISONCFG(0), 0x00000011 },
+ { DDRC_PCCFG(0), 0x00000111 },
+ { DDRC_PCFGR_0(0), 0x000010f3 },
+ { DDRC_PCFGW_0(0), 0x000072ff },
+ { DDRC_PCTRL_0(0), 0x00000001 },
+ /* disable Read Qos*/
+ { DDRC_PCFGQOS0_0(0), 0x00000e00 },
+ { DDRC_PCFGQOS1_0(0), 0x0062ffff },
+ /* disable Write Qos*/
+ { DDRC_PCFGWQOS0_0(0), 0x00000e00 },
+ { DDRC_PCFGWQOS1_0(0), 0x0000ffff },
+
+ /* boot start point */
+#ifdef DDR_BOOT_P2
+ { DDRC_MSTR2(0), 0x2 },
+#elif defined(DDR_BOOT_P1)
+ { DDRC_MSTR2(0), 0x1 },
+#endif
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
+ { 0x20110, 0x02 }, /* MapCAB0toDFI */
+ { 0x20111, 0x03 }, /* MapCAB1toDFI */
+ { 0x20112, 0x04 }, /* MapCAB2toDFI */
+ { 0x20113, 0x05 }, /* MapCAB3toDFI */
+ { 0x20114, 0x00 }, /* MapCAB4toDFI */
+ { 0x20115, 0x01 }, /* MapCAB5toDFI */
+
+ /* Initialize PHY Configuration */
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x1205f, 0x1ff },
+ { 0x1215f, 0x1ff },
+ { 0x1305f, 0x1ff },
+ { 0x1315f, 0x1ff },
+
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x11205f, 0x1ff },
+ { 0x11215f, 0x1ff },
+ { 0x11305f, 0x1ff },
+ { 0x11315f, 0x1ff },
+
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x21205f, 0x1ff },
+ { 0x21215f, 0x1ff },
+ { 0x21305f, 0x1ff },
+ { 0x21315f, 0x1ff },
+
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+
+ { 0x200c5, 0x19 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x1 },
+ { 0x22002e, 0x2 },
+
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+
+ { 0x20024, 0xe3 },
+ { 0x2003a, 0x2 },
+
+ { 0x120024, 0xa3 },
+ { 0x2003a, 0x2 },
+
+ { 0x220024, 0xa3 },
+ { 0x2003a, 0x2 },
+
+ { 0x20056, 0x3 },
+ { 0x120056, 0xa },
+ { 0x220056, 0xa },
+
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x1204d, 0xe00 },
+ { 0x1214d, 0xe00 },
+ { 0x1304d, 0xe00 },
+ { 0x1314d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x11204d, 0xe00 },
+ { 0x11214d, 0xe00 },
+ { 0x11304d, 0xe00 },
+ { 0x11314d, 0xe00 },
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x21204d, 0xe00 },
+ { 0x21214d, 0xe00 },
+ { 0x21304d, 0xe00 },
+ { 0x21314d, 0xe00 },
+
+ { 0x10049, 0xfbe },
+ { 0x10149, 0xfbe },
+ { 0x11049, 0xfbe },
+ { 0x11149, 0xfbe },
+ { 0x12049, 0xfbe },
+ { 0x12149, 0xfbe },
+ { 0x13049, 0xfbe },
+ { 0x13149, 0xfbe },
+
+ { 0x110049, 0xfbe },
+ { 0x110149, 0xfbe },
+ { 0x111049, 0xfbe },
+ { 0x111149, 0xfbe },
+ { 0x112049, 0xfbe },
+ { 0x112149, 0xfbe },
+ { 0x113049, 0xfbe },
+ { 0x113149, 0xfbe },
+
+ { 0x210049, 0xfbe },
+ { 0x210149, 0xfbe },
+ { 0x211049, 0xfbe },
+ { 0x211149, 0xfbe },
+ { 0x212049, 0xfbe },
+ { 0x212149, 0xfbe },
+ { 0x213049, 0xfbe },
+ { 0x213149, 0xfbe },
+
+ { 0x43, 0x63 },
+ { 0x1043, 0x63 },
+ { 0x2043, 0x63 },
+ { 0x3043, 0x63 },
+ { 0x4043, 0x63 },
+ { 0x5043, 0x63 },
+ { 0x6043, 0x63 },
+ { 0x7043, 0x63 },
+ { 0x8043, 0x63 },
+ { 0x9043, 0x63 },
+
+ { 0x20018, 0x3 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x320 },
+ { 0x120008, 0xa7 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0x104 },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x12043, 0x5a1 },
+ { 0x12143, 0x5a1 },
+ { 0x13043, 0x5a1 },
+ { 0x13143, 0x5a1 },
+ { 0x1200b2, 0x104 },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x112043, 0x5a1 },
+ { 0x112143, 0x5a1 },
+ { 0x113043, 0x5a1 },
+ { 0x113143, 0x5a1 },
+ { 0x2200b2, 0x104 },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x212043, 0x5a1 },
+ { 0x212143, 0x5a1 },
+ { 0x213043, 0x5a1 },
+ { 0x213143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+ { 0x200f0, 0x600 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5655 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
+};
+
+/* P0 message block parameter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x0 },
+ { 0x54003, 0xc80 },
+ { 0x54004, 0x2 },
+ { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
+ { 0x54006, LPDDR4_PHY_VREF_VALUE },
+ { 0x54007, 0x0 },
+ { 0x54008, 0x131f },
+ { 0x54009, LPDDR4_HDT_CTL_3200_1D },
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x2 },
+ { 0x5400c, 0x0 },
+ { 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) },
+ { 0x5400e, 0x0 },
+ { 0x5400f, 0x0 },
+ { 0x54010, 0x0 },
+ { 0x54011, 0x0 },
+ { 0x54012, (LPDDR4_CS << 8) | 0x10 },
+ { 0x54013, 0x0 },
+ { 0x54014, 0x0 },
+ { 0x54015, 0x0 },
+ { 0x54016, 0x0 },
+ { 0x54017, 0x0 },
+ { 0x54018, 0x0 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
+ { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
+ { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
+ { 0x5401d, 0x0 },
+ { 0x5401e, LPDDR4_MR22_RANK0 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
+ { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
+ { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
+ { 0x54023, 0x0 },
+ { 0x54024, LPDDR4_MR22_RANK1 },
+ { 0x54025, 0x0 },
+ { 0x54026, 0x0 },
+ { 0x54027, 0x0 },
+ { 0x54028, 0x0 },
+ { 0x54029, 0x0 },
+ { 0x5402a, 0x0 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x5402d, 0x0 },
+ { 0x5402e, 0x0 },
+ { 0x5402f, 0x0 },
+ { 0x54030, 0x0 },
+ { 0x54031, 0x0 },
+ { 0x54032, 0xd400 },
+ { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
+ { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
+ { 0x54035, (0x0800|LPDDR4_VREF_VALUE_CA) },
+ { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
+ { 0x54037, (LPDDR4_MR22_RANK0 << 8) },
+ { 0x54038, 0xd400 },
+ { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
+ { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
+ { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
+ { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
+ { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
+ { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
+ { 0x5403e, 0x0 },
+ { 0x5403f, 0x0 },
+ { 0x54040, 0x0 },
+ { 0x54041, 0x0 },
+ { 0x54042, 0x0 },
+ { 0x54043, 0x0 },
+ { 0x54044, 0x0 },
+ { 0xd0000, 0x1 },
+};
+
+static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x0 },
+ { 0x54003, 0xc80 },
+ { 0x54004, 0x2 },
+ { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
+ { 0x54006, LPDDR4_PHY_VREF_VALUE },
+ { 0x54007, 0x0 },
+ { 0x54008, 0x61 },
+ { 0x54009, LPDDR4_HDT_CTL_2D },
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x2 },
+ { 0x5400c, 0x0 },
+ { 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) },
+ { 0x5400e, 0x0 },
+ { 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 },
+ { 0x54010, LPDDR4_2D_WEIGHT },
+ { 0x54011, 0x0 },
+ { 0x54012, (LPDDR4_CS << 8) | 0x10 },
+ { 0x54013, 0x0 },
+ { 0x54014, 0x0 },
+ { 0x54015, 0x0 },
+ { 0x54016, 0x0 },
+ { 0x54017, 0x0 },
+ { 0x54018, 0x0 },
+ { 0x54024, 0x5 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
+ { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
+ { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
+ { 0x5401d, 0x0 },
+ { 0x5401e, LPDDR4_MR22_RANK0 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
+ { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
+ { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
+ { 0x54023, 0x0 },
+ { 0x54024, LPDDR4_MR22_RANK1 },
+ { 0x54025, 0x0 },
+ { 0x54026, 0x0 },
+ { 0x54027, 0x0 },
+ { 0x54028, 0x0 },
+ { 0x54029, 0x0 },
+ { 0x5402a, 0x0 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x5402d, 0x0 },
+ { 0x5402e, 0x0 },
+ { 0x5402f, 0x0 },
+ { 0x54030, 0x0 },
+ { 0x54031, 0x0 },
+ { 0x54032, 0xd400 },
+ { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
+ { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
+ { 0x54035, (0x0800|LPDDR4_VREF_VALUE_CA) },
+ { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
+ { 0x54037, (LPDDR4_MR22_RANK0 << 8) },
+ { 0x54038, 0xd400 },
+ { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
+ { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
+ { 0x5403b, (0x0800|LPDDR4_VREF_VALUE_CA) },
+ { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
+ { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
+ { 0x5403e, 0x0 },
+ { 0x5403f, 0x0 },
+ { 0x54040, 0x0 },
+ { 0x54041, 0x0 },
+ { 0x54042, 0x0 },
+ { 0x54043, 0x0 },
+ { 0x54044, 0x0 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block parameter for training firmware */
+static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54000, 0x0 },
+ { 0x54001, 0x0 },
+ { 0x54002, 0x1 },
+ { 0x54003, 0x29c },
+ { 0x54004, 0x2 },
+ { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
+ { 0x54006, LPDDR4_PHY_VREF_VALUE },
+ { 0x54007, 0x0 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400a, 0x0 },
+ { 0x5400b, 0x2 },
+ { 0x5400c, 0x0 },
+ { 0x5400d, 0x0 },
+ { 0x5400e, 0x0 },
+ { 0x5400f, 0x0 },
+ { 0x54010, 0x0 },
+ { 0x54011, 0x0 },
+ { 0x54012, (LPDDR4_CS << 8) | 0x10 },
+ { 0x54013, 0x0 },
+ { 0x54014, 0x0 },
+ { 0x54015, 0x0 },
+ { 0x54016, 0x0 },
+ { 0x54017, 0x0 },
+ { 0x54018, 0x0 },
+ { 0x54019, 0x914 },
+ { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
+ { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
+ { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
+ { 0x5401e, 0x6 },
+ { 0x5401f, 0x914 },
+ { 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
+ { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
+ { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
+ { 0x54023, 0x0 },
+ { 0x54024, LPDDR4_MR22_RANK1 },
+ { 0x54025, 0x0 },
+ { 0x54026, 0x0 },
+ { 0x54027, 0x0 },
+ { 0x54028, 0x0 },
+ { 0x54029, 0x0 },
+ { 0x5402a, 0x0 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x5402d, 0x0 },
+ { 0x5402e, 0x0 },
+ { 0x5402f, 0x0 },
+ { 0x54030, 0x0 },
+ { 0x54031, 0x0 },
+ { 0x54032, 0x1400 },
+ { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 },
+ { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
+ { 0x54035, (0x0800|LPDDR4_VREF_VALUE_CA) },
+ { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
+ { 0x54037, 0x600 },
+ { 0x54038, 0x1400 },
+ { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 },
+ { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
+ { 0x5403b, (0x0800|LPDDR4_VREF_VALUE_CA) },
+ { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
+ { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
+ { 0x5403e, 0x0 },
+ { 0x5403f, 0x0 },
+ { 0x54040, 0x0 },
+ { 0x54041, 0x0 },
+ { 0x54042, 0x0 },
+ { 0x54043, 0x0 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param lpddr4_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x0 },
+ { 0x90033, 0xe8 },
+ { 0x90034, 0x109 },
+ { 0x90035, 0x2 },
+ { 0x90036, 0x10 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0xb },
+ { 0x90039, 0x7c0 },
+ { 0x9003a, 0x139 },
+ { 0x9003b, 0x44 },
+ { 0x9003c, 0x630 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x14f },
+ { 0x9003f, 0x630 },
+ { 0x90040, 0x159 },
+ { 0x90041, 0x47 },
+ { 0x90042, 0x630 },
+ { 0x90043, 0x149 },
+ { 0x90044, 0x4f },
+ { 0x90045, 0x630 },
+ { 0x90046, 0x179 },
+ { 0x90047, 0x8 },
+ { 0x90048, 0xe0 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x7c8 },
+ { 0x9004c, 0x109 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x1 },
+ { 0x9004f, 0x8 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x45a },
+ { 0x90052, 0x9 },
+ { 0x90053, 0x0 },
+ { 0x90054, 0x448 },
+ { 0x90055, 0x109 },
+ { 0x90056, 0x40 },
+ { 0x90057, 0x630 },
+ { 0x90058, 0x179 },
+ { 0x90059, 0x1 },
+ { 0x9005a, 0x618 },
+ { 0x9005b, 0x109 },
+ { 0x9005c, 0x40c0 },
+ { 0x9005d, 0x630 },
+ { 0x9005e, 0x149 },
+ { 0x9005f, 0x8 },
+ { 0x90060, 0x4 },
+ { 0x90061, 0x48 },
+ { 0x90062, 0x4040 },
+ { 0x90063, 0x630 },
+ { 0x90064, 0x149 },
+ { 0x90065, 0x0 },
+ { 0x90066, 0x4 },
+ { 0x90067, 0x48 },
+ { 0x90068, 0x40 },
+ { 0x90069, 0x630 },
+ { 0x9006a, 0x149 },
+ { 0x9006b, 0x10 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x18 },
+ { 0x9006e, 0x0 },
+ { 0x9006f, 0x4 },
+ { 0x90070, 0x78 },
+ { 0x90071, 0x549 },
+ { 0x90072, 0x630 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0xd49 },
+ { 0x90075, 0x630 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x94a },
+ { 0x90078, 0x630 },
+ { 0x90079, 0x159 },
+ { 0x9007a, 0x441 },
+ { 0x9007b, 0x630 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x42 },
+ { 0x9007e, 0x630 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x1 },
+ { 0x90081, 0x630 },
+ { 0x90082, 0x149 },
+ { 0x90083, 0x0 },
+ { 0x90084, 0xe0 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0xa },
+ { 0x90087, 0x10 },
+ { 0x90088, 0x109 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x149 },
+ { 0x9008c, 0x9 },
+ { 0x9008d, 0x3c0 },
+ { 0x9008e, 0x159 },
+ { 0x9008f, 0x18 },
+ { 0x90090, 0x10 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x0 },
+ { 0x90093, 0x3c0 },
+ { 0x90094, 0x109 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x48 },
+ { 0x90098, 0x18 },
+ { 0x90099, 0x4 },
+ { 0x9009a, 0x58 },
+ { 0x9009b, 0xa },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x2 },
+ { 0x9009f, 0x10 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x5 },
+ { 0x900a2, 0x7c0 },
+ { 0x900a3, 0x109 },
+ { 0x900a4, 0xd },
+ { 0x900a5, 0x7c0 },
+ { 0x900a6, 0x109 },
+ { 0x900a7, 0x4 },
+ { 0x900a8, 0x7c0 },
+ { 0x900a9, 0x109 },
+ { 0x40000, 0x811 },
+ { 0x40020, 0x880 },
+ { 0x40040, 0x0 },
+ { 0x40060, 0x0 },
+ { 0x40001, 0x4008 },
+ { 0x40021, 0x83 },
+ { 0x40041, 0x4f },
+ { 0x40061, 0x0 },
+ { 0x40002, 0x4040 },
+ { 0x40022, 0x83 },
+ { 0x40042, 0x51 },
+ { 0x40062, 0x0 },
+ { 0x40003, 0x811 },
+ { 0x40023, 0x880 },
+ { 0x40043, 0x0 },
+ { 0x40063, 0x0 },
+ { 0x40004, 0x720 },
+ { 0x40024, 0xf },
+ { 0x40044, 0x1740 },
+ { 0x40064, 0x0 },
+ { 0x40005, 0x16 },
+ { 0x40025, 0x83 },
+ { 0x40045, 0x4b },
+ { 0x40065, 0x0 },
+ { 0x40006, 0x716 },
+ { 0x40026, 0xf },
+ { 0x40046, 0x2001 },
+ { 0x40066, 0x0 },
+ { 0x40007, 0x716 },
+ { 0x40027, 0xf },
+ { 0x40047, 0x2800 },
+ { 0x40067, 0x0 },
+ { 0x40008, 0x716 },
+ { 0x40028, 0xf },
+ { 0x40048, 0xf00 },
+ { 0x40068, 0x0 },
+ { 0x40009, 0x720 },
+ { 0x40029, 0xf },
+ { 0x40049, 0x1400 },
+ { 0x40069, 0x0 },
+ { 0x4000a, 0xe08 },
+ { 0x4002a, 0xc15 },
+ { 0x4004a, 0x0 },
+ { 0x4006a, 0x0 },
+ { 0x4000b, 0x623 },
+ { 0x4002b, 0x15 },
+ { 0x4004b, 0x0 },
+ { 0x4006b, 0x0 },
+ { 0x4000c, 0x4028 },
+ { 0x4002c, 0x80 },
+ { 0x4004c, 0x0 },
+ { 0x4006c, 0x0 },
+ { 0x4000d, 0xe08 },
+ { 0x4002d, 0xc1a },
+ { 0x4004d, 0x0 },
+ { 0x4006d, 0x0 },
+ { 0x4000e, 0x623 },
+ { 0x4002e, 0x1a },
+ { 0x4004e, 0x0 },
+ { 0x4006e, 0x0 },
+ { 0x4000f, 0x4040 },
+ { 0x4002f, 0x80 },
+ { 0x4004f, 0x0 },
+ { 0x4006f, 0x0 },
+ { 0x40010, 0x2604 },
+ { 0x40030, 0x15 },
+ { 0x40050, 0x0 },
+ { 0x40070, 0x0 },
+ { 0x40011, 0x708 },
+ { 0x40031, 0x5 },
+ { 0x40051, 0x0 },
+ { 0x40071, 0x2002 },
+ { 0x40012, 0x8 },
+ { 0x40032, 0x80 },
+ { 0x40052, 0x0 },
+ { 0x40072, 0x0 },
+ { 0x40013, 0x2604 },
+ { 0x40033, 0x1a },
+ { 0x40053, 0x0 },
+ { 0x40073, 0x0 },
+ { 0x40014, 0x708 },
+ { 0x40034, 0xa },
+ { 0x40054, 0x0 },
+ { 0x40074, 0x2002 },
+ { 0x40015, 0x4040 },
+ { 0x40035, 0x80 },
+ { 0x40055, 0x0 },
+ { 0x40075, 0x0 },
+ { 0x40016, 0x60a },
+ { 0x40036, 0x15 },
+ { 0x40056, 0x1200 },
+ { 0x40076, 0x0 },
+ { 0x40017, 0x61a },
+ { 0x40037, 0x15 },
+ { 0x40057, 0x1300 },
+ { 0x40077, 0x0 },
+ { 0x40018, 0x60a },
+ { 0x40038, 0x1a },
+ { 0x40058, 0x1200 },
+ { 0x40078, 0x0 },
+ { 0x40019, 0x642 },
+ { 0x40039, 0x1a },
+ { 0x40059, 0x1300 },
+ { 0x40079, 0x0 },
+ { 0x4001a, 0x4808 },
+ { 0x4003a, 0x880 },
+ { 0x4005a, 0x0 },
+ { 0x4007a, 0x0 },
+ { 0x900aa, 0x0 },
+ { 0x900ab, 0x790 },
+ { 0x900ac, 0x11a },
+ { 0x900ad, 0x8 },
+ { 0x900ae, 0x7aa },
+ { 0x900af, 0x2a },
+ { 0x900b0, 0x10 },
+ { 0x900b1, 0x7b2 },
+ { 0x900b2, 0x2a },
+ { 0x900b3, 0x0 },
+ { 0x900b4, 0x7c8 },
+ { 0x900b5, 0x109 },
+ { 0x900b6, 0x10 },
+ { 0x900b7, 0x10 },
+ { 0x900b8, 0x109 },
+ { 0x900b9, 0x10 },
+ { 0x900ba, 0x2a8 },
+ { 0x900bb, 0x129 },
+ { 0x900bc, 0x8 },
+ { 0x900bd, 0x370 },
+ { 0x900be, 0x129 },
+ { 0x900bf, 0xa },
+ { 0x900c0, 0x3c8 },
+ { 0x900c1, 0x1a9 },
+ { 0x900c2, 0xc },
+ { 0x900c3, 0x408 },
+ { 0x900c4, 0x199 },
+ { 0x900c5, 0x14 },
+ { 0x900c6, 0x790 },
+ { 0x900c7, 0x11a },
+ { 0x900c8, 0x8 },
+ { 0x900c9, 0x4 },
+ { 0x900ca, 0x18 },
+ { 0x900cb, 0xe },
+ { 0x900cc, 0x408 },
+ { 0x900cd, 0x199 },
+ { 0x900ce, 0x8 },
+ { 0x900cf, 0x8568 },
+ { 0x900d0, 0x108 },
+ { 0x900d1, 0x18 },
+ { 0x900d2, 0x790 },
+ { 0x900d3, 0x16a },
+ { 0x900d4, 0x8 },
+ { 0x900d5, 0x1d8 },
+ { 0x900d6, 0x169 },
+ { 0x900d7, 0x10 },
+ { 0x900d8, 0x8558 },
+ { 0x900d9, 0x168 },
+ { 0x900da, 0x70 },
+ { 0x900db, 0x788 },
+ { 0x900dc, 0x16a },
+ { 0x900dd, 0x1ff8 },
+ { 0x900de, 0x85a8 },
+ { 0x900df, 0x1e8 },
+ { 0x900e0, 0x50 },
+ { 0x900e1, 0x798 },
+ { 0x900e2, 0x16a },
+ { 0x900e3, 0x60 },
+ { 0x900e4, 0x7a0 },
+ { 0x900e5, 0x16a },
+ { 0x900e6, 0x8 },
+ { 0x900e7, 0x8310 },
+ { 0x900e8, 0x168 },
+ { 0x900e9, 0x8 },
+ { 0x900ea, 0xa310 },
+ { 0x900eb, 0x168 },
+ { 0x900ec, 0xa },
+ { 0x900ed, 0x408 },
+ { 0x900ee, 0x169 },
+ { 0x900ef, 0x6e },
+ { 0x900f0, 0x0 },
+ { 0x900f1, 0x68 },
+ { 0x900f2, 0x0 },
+ { 0x900f3, 0x408 },
+ { 0x900f4, 0x169 },
+ { 0x900f5, 0x0 },
+ { 0x900f6, 0x8310 },
+ { 0x900f7, 0x168 },
+ { 0x900f8, 0x0 },
+ { 0x900f9, 0xa310 },
+ { 0x900fa, 0x168 },
+ { 0x900fb, 0x1ff8 },
+ { 0x900fc, 0x85a8 },
+ { 0x900fd, 0x1e8 },
+ { 0x900fe, 0x68 },
+ { 0x900ff, 0x798 },
+ { 0x90100, 0x16a },
+ { 0x90101, 0x78 },
+ { 0x90102, 0x7a0 },
+ { 0x90103, 0x16a },
+ { 0x90104, 0x68 },
+ { 0x90105, 0x790 },
+ { 0x90106, 0x16a },
+ { 0x90107, 0x8 },
+ { 0x90108, 0x8b10 },
+ { 0x90109, 0x168 },
+ { 0x9010a, 0x8 },
+ { 0x9010b, 0xab10 },
+ { 0x9010c, 0x168 },
+ { 0x9010d, 0xa },
+ { 0x9010e, 0x408 },
+ { 0x9010f, 0x169 },
+ { 0x90110, 0x58 },
+ { 0x90111, 0x0 },
+ { 0x90112, 0x68 },
+ { 0x90113, 0x0 },
+ { 0x90114, 0x408 },
+ { 0x90115, 0x169 },
+ { 0x90116, 0x0 },
+ { 0x90117, 0x8b10 },
+ { 0x90118, 0x168 },
+ { 0x90119, 0x0 },
+ { 0x9011a, 0xab10 },
+ { 0x9011b, 0x168 },
+ { 0x9011c, 0x0 },
+ { 0x9011d, 0x1d8 },
+ { 0x9011e, 0x169 },
+ { 0x9011f, 0x80 },
+ { 0x90120, 0x790 },
+ { 0x90121, 0x16a },
+ { 0x90122, 0x18 },
+ { 0x90123, 0x7aa },
+ { 0x90124, 0x6a },
+ { 0x90125, 0xa },
+ { 0x90126, 0x0 },
+ { 0x90127, 0x1e9 },
+ { 0x90128, 0x8 },
+ { 0x90129, 0x8080 },
+ { 0x9012a, 0x108 },
+ { 0x9012b, 0xf },
+ { 0x9012c, 0x408 },
+ { 0x9012d, 0x169 },
+ { 0x9012e, 0xc },
+ { 0x9012f, 0x0 },
+ { 0x90130, 0x68 },
+ { 0x90131, 0x9 },
+ { 0x90132, 0x0 },
+ { 0x90133, 0x1a9 },
+ { 0x90134, 0x0 },
+ { 0x90135, 0x408 },
+ { 0x90136, 0x169 },
+ { 0x90137, 0x0 },
+ { 0x90138, 0x8080 },
+ { 0x90139, 0x108 },
+ { 0x9013a, 0x8 },
+ { 0x9013b, 0x7aa },
+ { 0x9013c, 0x6a },
+ { 0x9013d, 0x0 },
+ { 0x9013e, 0x8568 },
+ { 0x9013f, 0x108 },
+ { 0x90140, 0xb7 },
+ { 0x90141, 0x790 },
+ { 0x90142, 0x16a },
+ { 0x90143, 0x1f },
+ { 0x90144, 0x0 },
+ { 0x90145, 0x68 },
+ { 0x90146, 0x8 },
+ { 0x90147, 0x8558 },
+ { 0x90148, 0x168 },
+ { 0x90149, 0xf },
+ { 0x9014a, 0x408 },
+ { 0x9014b, 0x169 },
+ { 0x9014c, 0xc },
+ { 0x9014d, 0x0 },
+ { 0x9014e, 0x68 },
+ { 0x9014f, 0x0 },
+ { 0x90150, 0x408 },
+ { 0x90151, 0x169 },
+ { 0x90152, 0x0 },
+ { 0x90153, 0x8558 },
+ { 0x90154, 0x168 },
+ { 0x90155, 0x8 },
+ { 0x90156, 0x3c8 },
+ { 0x90157, 0x1a9 },
+ { 0x90158, 0x3 },
+ { 0x90159, 0x370 },
+ { 0x9015a, 0x129 },
+ { 0x9015b, 0x20 },
+ { 0x9015c, 0x2aa },
+ { 0x9015d, 0x9 },
+ { 0x9015e, 0x0 },
+ { 0x9015f, 0x400 },
+ { 0x90160, 0x10e },
+ { 0x90161, 0x8 },
+ { 0x90162, 0xe8 },
+ { 0x90163, 0x109 },
+ { 0x90164, 0x0 },
+ { 0x90165, 0x8140 },
+ { 0x90166, 0x10c },
+ { 0x90167, 0x10 },
+ { 0x90168, 0x8138 },
+ { 0x90169, 0x10c },
+ { 0x9016a, 0x8 },
+ { 0x9016b, 0x7c8 },
+ { 0x9016c, 0x101 },
+ { 0x9016d, 0x8 },
+ { 0x9016e, 0x0 },
+ { 0x9016f, 0x8 },
+ { 0x90170, 0x8 },
+ { 0x90171, 0x448 },
+ { 0x90172, 0x109 },
+ { 0x90173, 0xf },
+ { 0x90174, 0x7c0 },
+ { 0x90175, 0x109 },
+ { 0x90176, 0x0 },
+ { 0x90177, 0xe8 },
+ { 0x90178, 0x109 },
+ { 0x90179, 0x47 },
+ { 0x9017a, 0x630 },
+ { 0x9017b, 0x109 },
+ { 0x9017c, 0x8 },
+ { 0x9017d, 0x618 },
+ { 0x9017e, 0x109 },
+ { 0x9017f, 0x8 },
+ { 0x90180, 0xe0 },
+ { 0x90181, 0x109 },
+ { 0x90182, 0x0 },
+ { 0x90183, 0x7c8 },
+ { 0x90184, 0x109 },
+ { 0x90185, 0x8 },
+ { 0x90186, 0x8140 },
+ { 0x90187, 0x10c },
+ { 0x90188, 0x0 },
+ { 0x90189, 0x1 },
+ { 0x9018a, 0x8 },
+ { 0x9018b, 0x8 },
+ { 0x9018c, 0x4 },
+ { 0x9018d, 0x8 },
+ { 0x9018e, 0x8 },
+ { 0x9018f, 0x7c8 },
+ { 0x90190, 0x101 },
+ { 0x90006, 0x0 },
+ { 0x90007, 0x0 },
+ { 0x90008, 0x8 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x0 },
+ { 0x9000b, 0x0 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x9001f, 0x2b },
+ { 0x90026, 0x6c },
+ { 0x400d0, 0x0 },
+ { 0x400d1, 0x101 },
+ { 0x400d2, 0x105 },
+ { 0x400d3, 0x107 },
+ { 0x400d4, 0x10f },
+ { 0x400d5, 0x202 },
+ { 0x400d6, 0x20a },
+ { 0x400d7, 0x20b },
+ { 0x2003a, 0x2 },
+ { 0x2000b, 0x64 },
+ { 0x2000c, 0xc8 },
+ { 0x2000d, 0x7d0 },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0x14 },
+ { 0x12000c, 0x29 },
+ { 0x12000d, 0x1a1 },
+ { 0x12000e, 0x10 },
+ { 0x22000b, 0x3 },
+ { 0x22000c, 0x6 },
+ { 0x22000d, 0x3e },
+ { 0x22000e, 0x10 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0x60 },
+ { 0x90013, 0x6152 },
+ { 0x20010, 0x5a },
+ { 0x20011, 0x3 },
+ { 0x40080, 0xe0 },
+ { 0x40081, 0x12 },
+ { 0x40082, 0xe0 },
+ { 0x40083, 0x12 },
+ { 0x40084, 0xe0 },
+ { 0x40085, 0x12 },
+ { 0x140080, 0xe0 },
+ { 0x140081, 0x12 },
+ { 0x140082, 0xe0 },
+ { 0x140083, 0x12 },
+ { 0x140084, 0xe0 },
+ { 0x140085, 0x12 },
+ { 0x240080, 0xe0 },
+ { 0x240081, 0x12 },
+ { 0x240082, 0xe0 },
+ { 0x240083, 0x12 },
+ { 0x240084, 0xe0 },
+ { 0x240085, 0x12 },
+ { 0x400fd, 0xf },
+ { 0x10011, 0x1 },
+ { 0x10012, 0x1 },
+ { 0x10013, 0x180 },
+ { 0x10018, 0x1 },
+ { 0x10002, 0x6209 },
+ { 0x100b2, 0x1 },
+ { 0x101b4, 0x1 },
+ { 0x102b4, 0x1 },
+ { 0x103b4, 0x1 },
+ { 0x104b4, 0x1 },
+ { 0x105b4, 0x1 },
+ { 0x106b4, 0x1 },
+ { 0x107b4, 0x1 },
+ { 0x108b4, 0x1 },
+ { 0x11011, 0x1 },
+ { 0x11012, 0x1 },
+ { 0x11013, 0x180 },
+ { 0x11018, 0x1 },
+ { 0x11002, 0x6209 },
+ { 0x110b2, 0x1 },
+ { 0x111b4, 0x1 },
+ { 0x112b4, 0x1 },
+ { 0x113b4, 0x1 },
+ { 0x114b4, 0x1 },
+ { 0x115b4, 0x1 },
+ { 0x116b4, 0x1 },
+ { 0x117b4, 0x1 },
+ { 0x118b4, 0x1 },
+ { 0x12011, 0x1 },
+ { 0x12012, 0x1 },
+ { 0x12013, 0x180 },
+ { 0x12018, 0x1 },
+ { 0x12002, 0x6209 },
+ { 0x120b2, 0x1 },
+ { 0x121b4, 0x1 },
+ { 0x122b4, 0x1 },
+ { 0x123b4, 0x1 },
+ { 0x124b4, 0x1 },
+ { 0x125b4, 0x1 },
+ { 0x126b4, 0x1 },
+ { 0x127b4, 0x1 },
+ { 0x128b4, 0x1 },
+ { 0x13011, 0x1 },
+ { 0x13012, 0x1 },
+ { 0x13013, 0x180 },
+ { 0x13018, 0x1 },
+ { 0x13002, 0x6209 },
+ { 0x130b2, 0x1 },
+ { 0x131b4, 0x1 },
+ { 0x132b4, 0x1 },
+ { 0x133b4, 0x1 },
+ { 0x134b4, 0x1 },
+ { 0x135b4, 0x1 },
+ { 0x136b4, 0x1 },
+ { 0x137b4, 0x1 },
+ { 0x138b4, 0x1 },
+ { 0x20089, 0x1 },
+ { 0x20088, 0x19 },
+ { 0xc0080, 0x2 },
+ { 0xd0000, 0x1 },
+};
+
+static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
+ {
+ /* P0 3200mts 1D */
+ .drate = 3200,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = lpddr4_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
+ },
+ {
+ /* P0 3200mts 2D */
+ .drate = 3200,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = lpddr4_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = lpddr4_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
+ },
+#if 0
+ {
+ /* P1 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = lpddr4_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
+ },
+#endif
+};
+
+struct dram_timing_info lpddr4_timing = {
+ .ddrc_cfg = lpddr4_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
+ .ddrphy_cfg = lpddr4_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
+ .fsp_msg = lpddr4_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
+ .ddrphy_pie = lpddr4_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+};
diff --git a/board/boundary/nitrogen8m_som/mmc.c b/board/boundary/nitrogen8m_som/mmc.c
new file mode 100644
index 00000000000..fcb35fce30d
--- /dev/null
+++ b/board/boundary/nitrogen8m_som/mmc.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+#include <stdbool.h>
+
+/* This should be defined for each board */
+__weak int mmc_map_to_kernel_blk(int dev_no)
+{
+ return dev_no;
+}
+
+void board_late_mmc_env_init(void)
+{
+ env_set_ulong("mmcdev", 0);
+
+ /* Set mmcblk env */
+ env_set("mmcroot", "/dev/mmcblk0p2 rootwait rw");
+ run_command("mmc dev 0", 0);
+}
diff --git a/board/boundary/nitrogen8m_som/nitrogen8m_som.c b/board/boundary/nitrogen8m_som/nitrogen8m_som.c
new file mode 100644
index 00000000000..b17f192391f
--- /dev/null
+++ b/board/boundary/nitrogen8m_som/nitrogen8m_som.c
@@ -0,0 +1,403 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/fbpanel.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/video.h>
+#include <video_fb.h>
+#include <spl.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include <dm.h>
+#include <usb.h>
+#include <dwc3-uboot.h>
+#include <linux/usb/dwc3.h>
+#include "../common/padctrl.h"
+#include "../common/bd_common.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static iomux_v3_cfg_t const init_pads[] = {
+ IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+ IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+#define GP_LCM_JM430_BKL_EN IMX_GPIO_NR(1, 1)
+/* This enables 5V power on LTK080A60A004T mipi display */
+#define GP_LTK08_MIPI_EN IMX_GPIO_NR(1, 1)
+ IMX8MQ_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(0x16),
+
+#define GPIRQ_GT911 IMX_GPIO_NR(3, 12)
+ IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 | MUX_PAD_CTRL(0xd6),
+#define GP_GT911_RESET IMX_GPIO_NR(3, 13)
+#define GP_ST1633_RESET IMX_GPIO_NR(3, 13)
+ IMX8MQ_PAD_NAND_DATA07__GPIO3_IO13 | MUX_PAD_CTRL(0x49),
+
+#define GP_ARM_DRAM_VSEL IMX_GPIO_NR(3, 24)
+ IMX8MQ_PAD_SAI5_RXD3__GPIO3_IO24 | MUX_PAD_CTRL(0x16),
+#define GP_DRAM_1P1_VSEL IMX_GPIO_NR(2, 11)
+ IMX8MQ_PAD_SD1_STROBE__GPIO2_IO11 | MUX_PAD_CTRL(0x16),
+#define GP_SOC_GPU_VPU_VSEL IMX_GPIO_NR(2, 20)
+ IMX8MQ_PAD_SD2_WP__GPIO2_IO20 | MUX_PAD_CTRL(0x16),
+
+#define GP_FASTBOOT_KEY IMX_GPIO_NR(1, 7)
+ IMX8MQ_PAD_GPIO1_IO07__GPIO1_IO7 | MUX_PAD_CTRL(WEAK_PULLUP),
+
+#define GP_I2C1_PCA9546_RESET IMX_GPIO_NR(1, 4)
+ IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(0x46),
+
+#define GP_TC358762_EN IMX_GPIO_NR(3, 15)
+#define GP_I2C4_SN65DSI83_EN IMX_GPIO_NR(3, 15)
+#define GP_MIPI_RESET IMX_GPIO_NR(3, 15)
+ IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 | MUX_PAD_CTRL(0x6),
+
+
+#define GP_EMMC_RESET IMX_GPIO_NR(2, 10)
+ IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(0x41),
+
+#define GP_CSI1_MIPI_PWDN IMX_GPIO_NR(3, 3)
+ IMX8MQ_PAD_NAND_CE2_B__GPIO3_IO3 | MUX_PAD_CTRL(0x61),
+#define GP_CSI1_MIPI_RESET IMX_GPIO_NR(3, 17)
+ IMX8MQ_PAD_NAND_WE_B__GPIO3_IO17 | MUX_PAD_CTRL(0x61),
+
+#define GP_CSI2_MIPI_PWDN IMX_GPIO_NR(3, 2)
+ IMX8MQ_PAD_NAND_CE1_B__GPIO3_IO2 | MUX_PAD_CTRL(0x61),
+#define GP_CSI2_MIPI_RESET IMX_GPIO_NR(2, 19)
+ IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 |MUX_PAD_CTRL(0x61),
+#ifdef CONFIG_FEC_MXC
+ /* PHY - AR8035 */
+ IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, PAD_CTRL_ENET_MDIO),
+ IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, PAD_CTRL_ENET_MDC),
+ IOMUX_PAD_CTRL(ENET_TX_CTL__ENET_RGMII_TX_CTL, PAD_CTRL_ENET_TX),
+ IOMUX_PAD_CTRL(ENET_TD0__ENET_RGMII_TD0, PAD_CTRL_ENET_TX),
+ IOMUX_PAD_CTRL(ENET_TD1__ENET_RGMII_TD1, PAD_CTRL_ENET_TX),
+ IOMUX_PAD_CTRL(ENET_TD2__ENET_RGMII_TD2, PAD_CTRL_ENET_TX),
+ IOMUX_PAD_CTRL(ENET_TD3__ENET_RGMII_TD3, PAD_CTRL_ENET_TX),
+ IOMUX_PAD_CTRL(ENET_TXC__ENET_RGMII_TXC, PAD_CTRL_ENET_TX),
+#endif
+#define GP_RGMII_PHY_RESET IMX_GPIO_NR(1, 9)
+ IOMUX_PAD_CTRL(GPIO1_IO09__GPIO1_IO9, WEAK_PULLUP),
+#define GPIRQ_ENET_PHY IMX_GPIO_NR(1, 2)
+ IOMUX_PAD_CTRL(GPIO1_IO11__GPIO1_IO11, WEAK_PULLUP),
+};
+
+int board_early_init_f(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+ imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
+ set_wdog_reset(wdog);
+
+ gpio_direction_output(GP_ARM_DRAM_VSEL, 0);
+ gpio_direction_output(GP_DRAM_1P1_VSEL, 0);
+ gpio_direction_output(GP_SOC_GPU_VPU_VSEL, 0);
+ gpio_direction_output(GP_EMMC_RESET, 1);
+ gpio_direction_output(GP_I2C1_PCA9546_RESET, 0);
+ gpio_direction_output(GP_I2C4_SN65DSI83_EN, 0);
+ gpio_direction_output(GP_CSI1_MIPI_PWDN, 1);
+ gpio_direction_output(GP_CSI1_MIPI_RESET, 0);
+ gpio_direction_output(GP_CSI2_MIPI_PWDN, 1);
+ gpio_direction_output(GP_CSI2_MIPI_RESET, 0);
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_POSTCLK_INIT
+int board_postclk_init(void)
+{
+ /* TODO */
+ return 0;
+}
+#endif
+
+#define MAX_LOW_SIZE (0x100000000ULL - CONFIG_SYS_SDRAM_BASE)
+#define SDRAM_SIZE ((1ULL * CONFIG_DDR_MB) << 20)
+
+#if SDRAM_SIZE > MAX_LOW_SIZE
+#define MEM_SIZE MAX_LOW_SIZE
+#else
+#define MEM_SIZE SDRAM_SIZE
+#endif
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = SDRAM_SIZE;
+ return 0;
+}
+
+int dram_init(void)
+{
+ /* rom_pointer[1] contains the size of TEE occupies */
+ gd->ram_size = MEM_SIZE - rom_pointer[1];
+ return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ return 0;
+}
+#endif
+
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
+
+#define USB_PHY_CTRL0 0xF0040
+#define USB_PHY_CTRL0_REF_SSP_EN BIT(2)
+
+#define USB_PHY_CTRL1 0xF0044
+#define USB_PHY_CTRL1_RESET BIT(0)
+#define USB_PHY_CTRL1_COMMONONN BIT(1)
+#define USB_PHY_CTRL1_ATERESET BIT(3)
+#define USB_PHY_CTRL1_VDATSRCENB0 BIT(19)
+#define USB_PHY_CTRL1_VDATDETENB0 BIT(20)
+
+#define USB_PHY_CTRL2 0xF0048
+#define USB_PHY_CTRL2_TXENABLEN0 BIT(8)
+
+static struct dwc3_device dwc3_device_data = {
+ .maximum_speed = USB_SPEED_SUPER,
+ .base = USB1_BASE_ADDR,
+ .dr_mode = USB_DR_MODE_PERIPHERAL,
+ .index = 0,
+// .power_down_scale = 2,
+};
+
+int usb_gadget_handle_interrupts(void)
+{
+ dwc3_uboot_handle_interrupt(0);
+ return 0;
+}
+
+static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3)
+{
+ struct dwc3 *dwc3_reg = (struct dwc3 *)(dwc3->base + DWC3_REG_OFFSET);
+ u32 val;
+
+ val = readl(dwc3->base + USB_PHY_CTRL1);
+ val &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
+ USB_PHY_CTRL1_COMMONONN);
+ val |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
+ writel(val, dwc3->base + USB_PHY_CTRL1);
+
+ val = readl(dwc3->base + USB_PHY_CTRL0);
+ val |= USB_PHY_CTRL0_REF_SSP_EN;
+ writel(val, dwc3->base + USB_PHY_CTRL0);
+
+ val = readl(dwc3->base + USB_PHY_CTRL2);
+ val |= USB_PHY_CTRL2_TXENABLEN0;
+ writel(val, dwc3->base + USB_PHY_CTRL2);
+
+ val = readl(dwc3->base + USB_PHY_CTRL1);
+ val &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET);
+ writel(val, dwc3->base + USB_PHY_CTRL1);
+
+ val = readl(&dwc3_reg->g_ctl);
+ val &= ~(DWC3_GCTL_PWRDNSCALE_MASK);
+ val |= DWC3_GCTL_PWRDNSCALE(2);
+
+ writel(val, &dwc3_reg->g_ctl);
+}
+#endif
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
+int board_usb_init(int index, enum usb_init_type init)
+{
+ int ret = 0;
+ imx8m_usb_power(index, true);
+
+ if (index == 0 && init == USB_INIT_DEVICE) {
+ dwc3_nxp_usb_phy_init(&dwc3_device_data);
+ return dwc3_uboot_init(&dwc3_device_data);
+ } else if (index == 0 && init == USB_INIT_HOST) {
+ return ret;
+ }
+
+ if (index == 1) {
+ /* Release HUB reset */
+#define GP_USB1_HUB_RESET IMX_GPIO_NR(1, 14)
+ imx_iomux_v3_setup_pad(IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 |
+ MUX_PAD_CTRL(WEAK_PULLUP));
+ gpio_request(GP_USB1_HUB_RESET, "usb1_rst");
+ gpio_direction_output(GP_USB1_HUB_RESET, 1);
+ }
+
+ return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ int ret = 0;
+ if (index == 0 && init == USB_INIT_DEVICE)
+ dwc3_uboot_exit(index);
+
+ imx8m_usb_power(index, false);
+
+ return ret;
+}
+#endif
+
+#ifdef CONFIG_CMD_FBPANEL
+
+int board_detect_hdmi(struct display_info_t const *di)
+{
+ return hdmi_hpd_status() ? 1 : 0;
+}
+
+int board_detect_gt911(struct display_info_t const *di)
+{
+ int ret;
+ struct udevice *dev, *chip;
+
+ if (di->bus_gp)
+ gpio_direction_output(di->bus_gp, 1);
+ gpio_set_value(GP_GT911_RESET, 0);
+ mdelay(20);
+ gpio_direction_output(GPIRQ_GT911, di->addr_num == 0x14 ? 1 : 0);
+ udelay(100);
+ gpio_set_value(GP_GT911_RESET, 1);
+ mdelay(6);
+ gpio_set_value(GPIRQ_GT911, 0);
+ mdelay(50);
+ gpio_direction_input(GPIRQ_GT911);
+ ret = uclass_get_device(UCLASS_I2C, di->bus_num, &dev);
+ if (ret)
+ return 0;
+
+ ret = dm_i2c_probe(dev, di->addr_num, 0x0, &chip);
+ if (ret && di->bus_gp)
+ gpio_direction_input(di->bus_gp);
+ return (ret == 0);
+}
+
+static const struct display_info_t displays[] = {
+ /* hdmi */
+ VD_1920_1080M_60(HDMI, board_detect_hdmi, 0, 0x50),
+ VD_1280_720M_60(HDMI, NULL, 0, 0x50),
+ VD_MIPI_M101NWWB(MIPI, fbp_detect_i2c, fbp_bus_gp(0, GP_I2C4_SN65DSI83_EN, 0, 0), 0x2c),
+ VD_LTK080A60A004T(MIPI, board_detect_gt911, fbp_bus_gp(0, GP_LTK08_MIPI_EN, GP_LTK08_MIPI_EN, 0), 0x5d), /* Goodix touchscreen */
+ VD_LCM_JM430(MIPI, fbp_detect_i2c, fbp_bus_gp(0, GP_ST1633_RESET, GP_TC358762_EN, 30), fbp_addr_gp(0x55, GP_LCM_JM430_BKL_EN, 0, 0)), /* Sitronix touch */
+ VD_LTK0680YTMDB(MIPI, NULL, fbp_bus_gp(0, GP_MIPI_RESET, GP_MIPI_RESET, 0), 0x0),
+};
+#define display_cnt ARRAY_SIZE(displays)
+#else
+#define displays NULL
+#define display_cnt 0
+#endif
+
+int board_init(void)
+{
+ gpio_request(GP_I2C4_SN65DSI83_EN, "sn65dsi83_enable");
+ gpio_request(GP_GT911_RESET, "gt911_reset");
+ gpio_request(GPIRQ_GT911, "gt911_irq");
+ gpio_request(GP_LTK08_MIPI_EN, "lkt08_mipi_en");
+ gpio_direction_output(GP_GT911_RESET, 0);
+#ifdef CONFIG_DM_ETH
+ board_eth_init(gd->bd);
+#endif
+#ifdef CONFIG_CMD_FBPANEL
+ fbp_setup_display(displays, display_cnt);
+#endif
+
+ return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+ return 0;
+}
+
+#if defined(CONFIG_CMD_FASTBOOT) || defined(CONFIG_CMD_DFU)
+extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
+static void addserial_env(const char* env_var)
+{
+ unsigned char mac_address[8];
+ char serialbuf[20];
+
+ if (!env_get(env_var)) {
+ imx_get_mac_from_fuse(0, mac_address);
+ snprintf(serialbuf, sizeof(serialbuf), "%02x%02x%02x%02x%02x%02x",
+ mac_address[0], mac_address[1], mac_address[2],
+ mac_address[3], mac_address[4], mac_address[5]);
+ env_set(env_var, serialbuf);
+ }
+}
+#endif
+
+#ifdef CONFIG_CMD_BMODE
+const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"emmc0", MAKE_CFGVAL(0x22, 0x20, 0x00, 0x10)},
+ {NULL, 0},
+};
+#endif
+
+static int fastboot_key_pressed(void)
+{
+ gpio_request(GP_FASTBOOT_KEY, "fastboot_key");
+ gpio_direction_input(GP_FASTBOOT_KEY);
+ return !gpio_get_value(GP_FASTBOOT_KEY);
+}
+
+void board_late_mmc_env_init(void);
+void init_usb_clk(int usbno);
+
+static void set_env_vars(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ if (!env_get("board"))
+ env_set("board", "nitrogen8m_som");
+ env_set("soc", "imx8mq");
+ env_set("imx_cpu", get_imx_type((get_cpu_rev() & 0xFF000) >> 12));
+ env_set("uboot_defconfig", CONFIG_DEFCONFIG);
+#endif
+}
+
+void board_set_default_env(void)
+{
+ set_env_vars();
+#ifdef CONFIG_CMD_FBPANEL
+ fbp_setup_env_cmds();
+#endif
+ board_eth_addresses();
+}
+
+int board_late_init(void)
+{
+ set_env_vars();
+#if defined(CONFIG_USB_FUNCTION_FASTBOOT) || defined(CONFIG_CMD_DFU)
+ addserial_env("serial#");
+ if (fastboot_key_pressed()) {
+ printf("Starting fastboot...\n");
+ env_set("preboot", "fastboot 0");
+ }
+#endif
+#ifdef CONFIG_ENV_IS_IN_MMC
+ board_late_mmc_env_init();
+#endif
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+ init_usb_clk(0);
+ init_usb_clk(1);
+ return 0;
+}
diff --git a/board/boundary/nitrogen8m_som/spl.c b/board/boundary/nitrogen8m_som/spl.c
new file mode 100644
index 00000000000..ab1ba983af4
--- /dev/null
+++ b/board/boundary/nitrogen8m_som/spl.c
@@ -0,0 +1,226 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <asm/arch/ddr.h>
+#ifdef CONFIG_IMX8M_LPDDR4
+#include <asm/arch/imx8m_ddr.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_dram_init(void)
+{
+ /* ddr init */
+ ddr_init(&lpddr4_timing);
+}
+
+#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
+ .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
+ .gp = IMX_GPIO_NR(5, 14),
+ },
+ .sda = {
+ .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
+ .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
+ .gp = IMX_GPIO_NR(5, 15),
+ },
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+ switch (cfg->esdhc_base) {
+ case USDHC1_BASE_ADDR:
+ return 1;
+ }
+ return 0;
+}
+
+#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
+ PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
+
+static iomux_v3_cfg_t const init_pads[] = {
+#define GP_I2C1_PCA9546_RESET IMX_GPIO_NR(1, 4)
+ IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(0x46),
+
+ IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+#define GP_EMMC_RESET IMX_GPIO_NR(2, 10)
+ IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[] = {
+ {.esdhc_base = USDHC1_BASE_ADDR, .bus_width = 8,
+ .gp_reset = GP_EMMC_RESET},
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ int i, ret;
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-Boot device node) (Physical Port)
+ * mmc0 USDHC1
+ * mmc1 USDHC2
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
+ gpio_request(GP_EMMC_RESET, "usdhc1_reset");
+ gpio_direction_output(GP_EMMC_RESET, 0);
+ udelay(500);
+ gpio_direction_output(GP_EMMC_RESET, 1);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) than supported by the board\n", i + 1);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+#define GP_ARM_DRAM_VSEL IMX_GPIO_NR(3, 24)
+#define GP_DRAM_1P1_VSEL IMX_GPIO_NR(2, 11)
+#define GP_SOC_GPU_VPU_VSEL IMX_GPIO_NR(2, 20)
+
+#define I2C_MUX_ADDR 0x70
+#define I2C_FAN53555_ADDR 0x60
+void ddr_voltage_init(void)
+{
+ u8 val8;
+
+ gpio_set_value(GP_I2C1_PCA9546_RESET, 1);
+ gpio_set_value(GP_ARM_DRAM_VSEL, 0);
+ gpio_set_value(GP_DRAM_1P1_VSEL, 0);
+ gpio_set_value(GP_SOC_GPU_VPU_VSEL, 0);
+ printf("Setting voltages\n");
+ /*
+ * 9e (1e = 30) default .9 V
+ * 0.6V to 1.23V in 10 MV steps
+ */
+
+ /* Enable I2C1A, ARM/DRAM */
+ i2c_write(I2C_MUX_ADDR, 1, 1, NULL, 0);
+ /*
+ * .6 + .40 = 1.00
+ */
+ val8 = 0x80 + 40;
+ i2c_write(I2C_FAN53555_ADDR, 0, 1, &val8, 1);
+ i2c_write(I2C_FAN53555_ADDR, 1, 1, &val8, 1);
+
+ /* Enable I2C1B, DRAM 1.1V */
+ i2c_write(I2C_MUX_ADDR, 2, 1, NULL, 0);
+ /*
+ * .6 + .50 = 1.10
+ */
+ val8 = 0x80 + 50;
+ i2c_write(I2C_FAN53555_ADDR, 0, 1, &val8, 1);
+ i2c_write(I2C_FAN53555_ADDR, 1, 1, &val8, 1);
+
+ /* Enable I2C1C, soc/gpu/vpu */
+ i2c_write(I2C_MUX_ADDR, 4, 1, NULL, 0);
+ /*
+ * .6 + .30 = .90
+ */
+ val8 = 0x80 + 30;
+ i2c_write(I2C_FAN53555_ADDR, 0, 1, &val8, 1);
+ i2c_write(I2C_FAN53555_ADDR, 1, 1, &val8, 1);
+
+ /* Enable I2C1D */
+ i2c_write(I2C_MUX_ADDR, 8, 1, NULL, 0);
+}
+
+int power_init_board(void)
+{
+ /* nitrogen8m_som I2C write */
+ ddr_voltage_init();
+ return 0;
+}
+
+void spl_board_init(void)
+{
+ enable_tzc380();
+ imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
+
+ /* Adjust pmic voltage to 1.0V for 800M */
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+ power_init_board();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Serial download mode */
+ if (is_usb_boot()) {
+ puts("Back to ROM, SDP\n");
+ restore_boot_params();
+ }
+ puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+ /* Clear global data */
+ memset((void *)gd, 0, sizeof(gd_t));
+
+ arch_cpu_init();
+
+ board_early_init_f();
+ init_uart_clk(0);
+ timer_init();
+
+ preloader_console_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ board_init_r(NULL, 0);
+}
diff --git a/configs/nitrogen8m_som_2g_defconfig b/configs/nitrogen8m_som_2g_defconfig
new file mode 100644
index 00000000000..b934f1eed80
--- /dev/null
+++ b/configs/nitrogen8m_som_2g_defconfig
@@ -0,0 +1,94 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_IMX8M_LPDDR4=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_NITROGEN8M_SOM=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0x30860000
+CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mq-nitrogen8m_som"
+CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,DDR_MB=2048,DEFCONFIG=\"nitrogen8m_som_2g\""
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x40480000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DEBUG_UART_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Boundary"
+CONFIG_USB_GADGET_VENDOR_NUM=0x3016
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0001
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
+CONFIG_USBNET_DEVADDR="00:19:b8:00:00:02"
+CONFIG_USBNET_HOST_ADDR="00:19:b8:00:00:01"
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMXDCSS=y
+CONFIG_VIDEO_IMX8_HDMI=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
diff --git a/include/configs/nitrogen8m_som.h b/include/configs/nitrogen8m_som.h
new file mode 100644
index 00000000000..dc1a7111dab
--- /dev/null
+++ b/include/configs/nitrogen8m_som.h
@@ -0,0 +1,259 @@
+/*
+ * Copyright 2018 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __NITROGEN8M_SOM_H
+#define __NITROGEN8M_SOM_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CSF_SIZE 0x2000 /* 8K region */
+#endif
+
+#define CONFIG_SPL_TEXT_BASE 0x7E1000
+#define CONFIG_SPL_MAX_SIZE (124 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+
+#ifdef CONFIG_SPL_BUILD
+/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_STACK 0x187FF0
+#define CONFIG_SPL_BSS_START_ADDR 0x00180000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x00182000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x2000 /* 8 KB */
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
+
+#undef CONFIG_DM_MMC
+#undef CONFIG_DM_PMIC
+#undef CONFIG_DM_PMIC_PFUZE100
+
+#define CONFIG_SYS_I2C
+
+#endif
+
+#define CONFIG_PREBOOT
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_POSTCLK_INIT
+#define CONFIG_BOARD_LATE_INIT
+
+/* Flat Device Tree Definitions */
+#define CONFIG_OF_BOARD_SETUP
+
+#undef CONFIG_CMD_EXPORTENV
+#undef CONFIG_CMD_IMPORTENV
+#undef CONFIG_CMD_IMLS
+
+/* #define CONFIG_CMD_BMODE */
+#undef CONFIG_CMD_CRC32
+#undef CONFIG_BOOTM_NETBSD
+
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_MII
+#define CONFIG_ETHPRIME "FEC"
+
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_MXC_PHYADDR 4
+#define FEC_QUIRK_ENET_MAC
+#define GP_RGMII_PHY_RESET IMX_GPIO_NR(1, 9)
+
+#define CONFIG_PHY_GIGE
+#define IMX_FEC_BASE 0x30BE0000
+
+#endif
+
+/* Link Definitions */
+#define CONFIG_LOADADDR 0x40480000
+#define CONFIG_SYS_TEXT_BASE 0x40200000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
+#define CONFIG_SYS_MMC_ENV_PART 1 /* mmcblk0boot0 */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2*1024) + (16*1024)) * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM 0x40000000
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 2048
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_IMX_BOOTAUX
+
+#define CONFIG_FSL_USDHC
+
+#define CONFIG_SYS_FSL_USDHC_NUM 1
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+#define CONFIG_SUPPORT_EMMC_RPMB
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_OCOTP
+#define CONFIG_CMD_FUSE
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* USB configs */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
+#define CONFIG_USB_DWC3
+#define CONFIG_USB_DWC3_GADGET
+#define CONFIG_USBD_HS
+
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+#define CONFIG_USB_GADGET_DUALSPEED
+
+#endif
+
+#define CONFIG_OF_SYSTEM_SETUP
+
+/* Framebuffer */
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#endif
+
+#ifndef BD_CONSOLE
+#if CONFIG_MXC_UART_BASE == UART2_BASE_ADDR
+#define BD_CONSOLE "ttymxc1"
+#elif CONFIG_MXC_UART_BASE == UART1_BASE_ADDR
+#define BD_CONSOLE "ttymxc0"
+#endif
+#endif
+
+#ifdef CONFIG_CMD_MMC
+#if (CONFIG_SYS_FSL_USDHC_NUM == 1)
+#define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0)
+#elif (CONFIG_SYS_FSL_USDHC_NUM == 2)
+#define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
+#else
+#define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) func(MMC, mmc, 2)
+#endif
+#else
+#define DISTRO_BOOT_DEV_MMC(func)
+#endif
+
+#ifdef CONFIG_USB_STORAGE
+#define DISTRO_BOOT_DEV_USB(func) func(USB, usb, 0)
+#else
+#define DISTRO_BOOT_DEV_USB(func)
+#endif
+
+#ifndef BOOT_TARGET_DEVICES
+#define BOOT_TARGET_DEVICES(func) \
+ DISTRO_BOOT_DEV_USB(func) \
+ DISTRO_BOOT_DEV_MMC(func)
+#endif
+
+#include <config_distro_bootcmd.h>
+#define CONFIG_CMD_FBPANEL
+
+#define BD_RAM_BASE 0x80000000
+#define BD_RAM_SCRIPT "40008000"
+#define BD_RAM_KERNEL "40800000"
+#define BD_RAM_RAMDISK "42800000"
+#define BD_RAM_FDT "43000000"
+
+/* M4 specific */
+#define SYS_AUXCORE_BOOTDATA_DDR 0x80000000
+#define SYS_AUXCORE_BOOTDATA_TCM 0x007E0000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console=" BD_CONSOLE "\0" \
+ "env_dev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+ "env_part=" __stringify(CONFIG_SYS_MMC_ENV_PART) "\0" \
+ "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+ "fdt_addr=0x43000000\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "m4boot=load ${devtype} ${devnum}:1 ${m4loadaddr} ${m4image}; " \
+ "dcache flush; bootaux ${m4loadaddr}\0" \
+ "m4image=m4_fw.bin\0" \
+ "m4loadaddr="__stringify(SYS_AUXCORE_BOOTDATA_TCM)"\0" \
+ "netargs=setenv bootargs console=${console},115200 root=/dev/nfs rw " \
+ "ip=dhcp nfsroot=${tftpserverip}:${nfsroot},v3,tcp\0" \
+ "netboot=run netargs; " \
+ "if test -z \"${fdt_file}\" -a -n \"${soc}\"; then " \
+ "setenv fdt_file ${soc}-${board}${boardver}.dtb; " \
+ "fi; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${loadaddr} ${tftpserverip}:Image; " \
+ "if ${get_cmd} ${fdt_addr} ${tftpserverip}:${fdt_file}; then " \
+ "booti ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi;\0" \
+ "net_upgradeu=dhcp " BD_RAM_SCRIPT " net_upgradeu.scr && source " BD_RAM_SCRIPT "\0" \
+ "otg_upgradeu=run usbnetwork; tftp " BD_RAM_SCRIPT " net_upgradeu.scr && source " BD_RAM_SCRIPT "\0" \
+ "upgradeu=setenv boot_scripts upgrade.scr; boot;" \
+ "echo Upgrade failed!; setenv boot_scripts boot.scr\0" \
+ "usbnet_devaddr=00:19:b8:00:00:02\0" \
+ "usbnet_hostaddr=00:19:b8:00:00:01\0" \
+ "usbnetwork=setenv ethact usb_ether; " \
+ "setenv ipaddr 10.0.0.2; " \
+ "setenv netmask 255.255.255.0; " \
+ "setenv serverip 10.0.0.1;\0" \
+ BOOTENV
+
+/*
+ * PCI express
+ */
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#endif
+#endif
--
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