diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
index 23b12cf7a80f72244cf5ef082960e248af01898b..bd138997bc69a28667e6b2b58b1fe2f39792e961 100644
--- a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
+++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
@@ -408,22 +408,6 @@ struct clk_root_map {
 	uint8_t src_mux[8];
 };
 
-enum dram_pll_out_val {
-	DRAM_PLL_OUT_100M,
-	DRAM_PLL_OUT_266M,
-	DRAM_PLL_OUT_667M,
-	DRAM_PLL_OUT_400M,
-	DRAM_PLL_OUT_600M,
-	DRAM_PLL_OUT_750M,
-	DRAM_PLL_OUT_800M,
-};
-
-enum dram_bypassclk_val {
-	DRAM_BYPASSCLK_100M,
-	DRAM_BYPASSCLK_250M,
-	DRAM_BYPASSCLK_400M,
-};
-
 #define INTPLL_LOCK_MASK			BIT(31)
 #define INTPLL_LOCK_SEL_MASK			BIT(29)
 #define INTPLL_EXT_BYPASS_MASK			BIT(28)
@@ -587,8 +571,8 @@ enum enet_freq {
 	ENET_50MHZ,
 	ENET_125MHZ,
 };
-void dram_pll_init(enum dram_pll_out_val pll_val);
-void dram_enable_bypass(enum dram_bypassclk_val clk_val);
+void dram_pll_init(ulong pll_val);
+void dram_enable_bypass(ulong clk_val);
 void dram_disable_bypass(void);
 u32 imx_get_fecclk(void);
 u32 imx_get_uartclk(void);
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 1d44f485319cc63e8e98b1d318406b6c2db2a49b..86b39b59f87dd5edf6987c8a292bde83ee29732a 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -299,7 +299,7 @@ struct imx_int_pll_rate_table {
 	}
 
 struct dram_bypass_clk_setting {
-	enum dram_bypassclk_val clk;
+	ulong clk;
 	int alt_root_sel;
 	enum root_pre_div alt_pre_div;
 	int apb_root_sel;
@@ -320,9 +320,9 @@ static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
 };
 
 static struct dram_bypass_clk_setting imx8mm_dram_bypass_tbl[] = {
-	DRAM_BYPASS_ROOT_CONFIG(DRAM_BYPASSCLK_100M, 2, CLK_ROOT_PRE_DIV1, 2, CLK_ROOT_PRE_DIV2),
-	DRAM_BYPASS_ROOT_CONFIG(DRAM_BYPASSCLK_250M, 3, CLK_ROOT_PRE_DIV2, 2, CLK_ROOT_PRE_DIV2),
-	DRAM_BYPASS_ROOT_CONFIG(DRAM_BYPASSCLK_400M, 1, CLK_ROOT_PRE_DIV2, 3, CLK_ROOT_PRE_DIV2),
+	DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2, CLK_ROOT_PRE_DIV2),
+	DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2, CLK_ROOT_PRE_DIV2),
+	DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3, CLK_ROOT_PRE_DIV2),
 };
 
 int fracpll_configure(enum pll_clocks clock, u32 freq)
@@ -393,37 +393,12 @@ int fracpll_configure(enum pll_clocks clock, u32 freq)
 	return ret;
 }
 
-void dram_pll_init(enum dram_pll_out_val pll_val)
+void dram_pll_init(ulong pll_val)
 {
-	u32 freq;
-
-	switch (pll_val) {
-	case DRAM_PLL_OUT_100M:
-		freq = 100000000UL;
-		break;
-	case DRAM_PLL_OUT_667M:
-		freq = 667000000UL;
-		break;
-	case DRAM_PLL_OUT_400M:
-		freq = 400000000UL;
-		break;
-	case DRAM_PLL_OUT_600M:
-		freq = 600000000UL;
-		break;
-	case DRAM_PLL_OUT_750M:
-		freq = 750000000UL;
-		break;
-	case DRAM_PLL_OUT_800M:
-		freq = 800000000UL;
-		break;
-	default:
-		return;
-	}
-
-	fracpll_configure(ANATOP_DRAM_PLL, freq);
+	fracpll_configure(ANATOP_DRAM_PLL, pll_val);
 }
 
-void dram_enable_bypass(enum dram_bypassclk_val clk_val)
+void dram_enable_bypass(ulong clk_val)
 {
 	int i;
 	struct dram_bypass_clk_setting *config;
@@ -434,7 +409,7 @@ void dram_enable_bypass(enum dram_bypassclk_val clk_val)
 	}
 
 	if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) {
-		printf("No matched freq table %u\n", clk_val);
+		printf("No matched freq table %lu\n", clk_val);
 		return;
 	}
 
diff --git a/drivers/ddr/imx8m/ddrphy_utils.c b/drivers/ddr/imx8m/ddrphy_utils.c
index a58ae0dda01997812187e8f6e150030eedc8a2c0..b26e8dd17bd748dcd16b3648f988729c587bf368 100644
--- a/drivers/ddr/imx8m/ddrphy_utils.c
+++ b/drivers/ddr/imx8m/ddrphy_utils.c
@@ -101,27 +101,11 @@ void wait_ddrphy_training_complete(void)
 
 void ddrphy_init_set_dfi_clk(unsigned int drate)
 {
-	switch (drate) {
-	case 3000:
-		dram_pll_init(DRAM_PLL_OUT_750M);
+	if (drate >= 1600) {
+		dram_pll_init(MHZ(drate/4));
 		dram_disable_bypass();
-		break;
-	case 2400:
-		dram_pll_init(DRAM_PLL_OUT_600M);
-		dram_disable_bypass();
-		break;
-	case 1600:
-		dram_pll_init(DRAM_PLL_OUT_400M);
-		dram_disable_bypass();
-		break;
-	case 400:
-		dram_enable_bypass(DRAM_BYPASSCLK_400M);
-		break;
-	case 100:
-		dram_enable_bypass(DRAM_BYPASSCLK_100M);
-		break;
-	default:
-		return;
+	} if (drate <= 400) {
+		dram_enable_bypass(MHZ(drate));
 	}
 }
 
diff --git a/drivers/ddr/imx8m/lpddr4/lpddr4_init.c b/drivers/ddr/imx8m/lpddr4/lpddr4_init.c
index 17a51bea831f51d4fc8f262b68cb446efb481f80..0a02e5da4c7df3c4714864b4c099c3f225a60b4a 100644
--- a/drivers/ddr/imx8m/lpddr4/lpddr4_init.c
+++ b/drivers/ddr/imx8m/lpddr4/lpddr4_init.c
@@ -50,7 +50,7 @@ void ddr_init(struct dram_timing_info *dram_timing)
 	reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */
 
 	debug("DDRINFO: cfg clk\n");
-	dram_pll_init(DRAM_PLL_OUT_750M);
+	dram_pll_init(MHZ(750));
 
 	/*
 	 * release [0]ddr1_preset_n, [1]ddr1_core_reset_n,