diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index b00decec6d45c40331ad2512060638bc212414a6..9a46340deb318a5457cdf3c32946a115fad61ed8 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -1171,6 +1171,7 @@ struct emif_regs {
 	u32 sdram_tim1;
 	u32 sdram_tim2;
 	u32 sdram_tim3;
+	u32 ocp_config;
 	u32 read_idle_ctrl;
 	u32 zq_config;
 	u32 temp_alert_config;
diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c
index 6acf30c5db00fe4e363a0fe449e1193cc8306643..690487e7c38b5a5581eee9479b50c162ed396a17 100644
--- a/arch/arm/mach-omap2/am33xx/ddr.c
+++ b/arch/arm/mach-omap2/am33xx/ddr.c
@@ -180,6 +180,10 @@ void config_sdram(const struct emif_regs *regs, int nr)
 	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 	writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 	writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
+
+	/* Write REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT. */
+	if (regs->ocp_config)
+		writel(regs->ocp_config, &emif_reg[nr]->emif_l3_config);
 }
 
 /**
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 111ed3556cc3c603107e796209c23ea7399b3873..8eaf3e9a5c95023246387bc8fb1b9f615a839088 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -109,6 +109,16 @@ static const struct emif_regs ddr2_emif_reg_data = {
 	.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
 };
 
+static const struct emif_regs ddr2_evm_emif_reg_data = {
+	.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
+	.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
+	.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
+	.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
+	.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
+	.ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
+	.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
+};
+
 static const struct ddr_data ddr3_data = {
 	.datardsratio0 = MT41J128MJT125_RD_DQS,
 	.datawdsratio0 = MT41J128MJT125_WR_DQS,
@@ -198,6 +208,7 @@ static struct emif_regs ddr3_beagleblack_emif_reg_data = {
 	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
 	.zq_config = MT41K256M16HA125E_ZQ_CFG,
 	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 };
@@ -208,6 +219,7 @@ static struct emif_regs ddr3_evm_emif_reg_data = {
 	.sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
 	.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
 	.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
+	.ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
 	.zq_config = MT41J512M8RH125_ZQ_CFG,
 	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
 				PHY_EN_DYN_PWRDN,
@@ -486,6 +498,9 @@ void sdram_init(void)
 		config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
 			   &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
 			   0);
+	else if (board_is_gp_evm())
+		config_ddr(266, &ioregs, &ddr2_data,
+			   &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
 	else
 		config_ddr(266, &ioregs, &ddr2_data,
 			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h
index 9776df79592825fdfec53caa42f1dfd16e317f58..48c139a817d52cca651bdf6720426c2f94af48dd 100644
--- a/board/ti/am335x/board.h
+++ b/board/ti/am335x/board.h
@@ -11,6 +11,19 @@
 #ifndef _BOARD_H_
 #define _BOARD_H_
 
+/**
+ * AM335X (EMIF_4D) EMIF REG_COS_COUNT_1, REG_COS_COUNT_2, and
+ * REG_PR_OLD_COUNT values to avoid LCDC DMA FIFO underflows and Frame
+ * Synchronization Lost errors. The values are the biggest that work
+ * reliably with offered video modes and the memory subsystem on the
+ * boards. These register have are briefly documented in "7.3.3.5.2
+ * Command Starvation" section of AM335x TRM. The REG_COS_COUNT_1 and
+ * REG_COS_COUNT_2 do not have any effect on current versions of
+ * AM335x.
+ */
+#define EMIF_OCP_CONFIG_BEAGLEBONE_BLACK       0x00141414
+#define EMIF_OCP_CONFIG_AM335X_EVM             0x003d3d3d
+
 static inline int board_is_bone(void)
 {
 	return board_ti_is("A335BONE");