From 79b4ec27baab7f03640a62fec181185a1e2954ec Mon Sep 17 00:00:00 2001
From: Troy Kisky <troy.kisky@boundarydevices.com>
Date: Fri, 26 Jan 2018 18:10:03 -0800
Subject: [PATCH] nitrogen51_e: initial addition, Boundary Devices board
nitrogen51_e: MAINTAINERS: s/NITROGEN6_VM/NITROGEN6_E/
nitrogen51_e: add comment for ddr
nitrogen51_e: port to v2018.07
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
arch/arm/mach-imx/mx5/Kconfig | 5 +
board/boundary/nitrogen51_e/Kconfig | 24 +
board/boundary/nitrogen51_e/MAINTAINERS | 7 +
board/boundary/nitrogen51_e/Makefile | 7 +
board/boundary/nitrogen51_e/nitrogen51_e.c | 598 ++++++++++++++++++
board/boundary/nitrogen51_e/nitrogen51_e.cfg | 140 ++++
.../nitrogen_bootscript_upgrade.txt | 128 ++++
configs/nitrogen51_e_256m_defconfig | 70 ++
configs/nitrogen51_e_512m_defconfig | 70 ++
configs/nitrogen51_e_rev0_256m_defconfig | 68 ++
configs/nitrogen51_e_rev0_512m_defconfig | 68 ++
include/configs/nitrogen51_e.h | 129 ++++
12 files changed, 1314 insertions(+)
create mode 100644 board/boundary/nitrogen51_e/Kconfig
create mode 100644 board/boundary/nitrogen51_e/MAINTAINERS
create mode 100644 board/boundary/nitrogen51_e/Makefile
create mode 100644 board/boundary/nitrogen51_e/nitrogen51_e.c
create mode 100644 board/boundary/nitrogen51_e/nitrogen51_e.cfg
create mode 100644 board/boundary/nitrogen51_e/nitrogen_bootscript_upgrade.txt
create mode 100644 configs/nitrogen51_e_256m_defconfig
create mode 100644 configs/nitrogen51_e_512m_defconfig
create mode 100644 configs/nitrogen51_e_rev0_256m_defconfig
create mode 100644 configs/nitrogen51_e_rev0_512m_defconfig
create mode 100644 include/configs/nitrogen51_e.h
diff --git a/arch/arm/mach-imx/mx5/Kconfig b/arch/arm/mach-imx/mx5/Kconfig
index 3654670442f..3b597676d9d 100644
--- a/arch/arm/mach-imx/mx5/Kconfig
+++ b/arch/arm/mach-imx/mx5/Kconfig
@@ -73,12 +73,17 @@ config TARGET_USBARMORY
bool "Support USB armory"
select MX53
+config TARGET_NITROGEN51_E
+ bool "Support Boundary Devices nitrogen51_e board"
+ select CPU_V7
+
endchoice
config SYS_SOC
default "mx5"
source "board/beckhoff/mx53cx9020/Kconfig"
+source "board/boundary/nitrogen51_e/Kconfig"
source "board/freescale/mx51evk/Kconfig"
source "board/freescale/mx53ard/Kconfig"
source "board/freescale/mx53evk/Kconfig"
diff --git a/board/boundary/nitrogen51_e/Kconfig b/board/boundary/nitrogen51_e/Kconfig
new file mode 100644
index 00000000000..7d3ff6b71d4
--- /dev/null
+++ b/board/boundary/nitrogen51_e/Kconfig
@@ -0,0 +1,24 @@
+if TARGET_NITROGEN51_E
+
+config SYS_CPU
+ default "armv7"
+
+config SYS_BOARD
+ default "nitrogen51_e"
+
+config SYS_VENDOR
+ default "boundary"
+
+config SYS_SOC
+ default "mx5"
+
+config SYS_CONFIG_NAME
+ default "nitrogen51_e"
+
+config BOARD_LATE_SPECIFIC_INIT
+ bool
+ default y
+
+source "board/boundary/common/Kconfig"
+
+endif
diff --git a/board/boundary/nitrogen51_e/MAINTAINERS b/board/boundary/nitrogen51_e/MAINTAINERS
new file mode 100644
index 00000000000..1bbd28a4b41
--- /dev/null
+++ b/board/boundary/nitrogen51_e/MAINTAINERS
@@ -0,0 +1,7 @@
+NITROGEN6_E BOARD
+M: Troy Kisky <troy.kisky@boundarydevices.com>
+S: Maintained
+F: board/boundary/nitrogen51_e/
+F: include/configs/nitrogen51_e.h
+F: configs/nitrogen51_e_256m_defconfig
+F: configs/nitrogen51_e_512m_defconfig
diff --git a/board/boundary/nitrogen51_e/Makefile b/board/boundary/nitrogen51_e/Makefile
new file mode 100644
index 00000000000..5c37d638065
--- /dev/null
+++ b/board/boundary/nitrogen51_e/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2018, Boundary Devices <info@boundarydevices.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := nitrogen51_e.o
diff --git a/board/boundary/nitrogen51_e/nitrogen51_e.c b/board/boundary/nitrogen51_e/nitrogen51_e.c
new file mode 100644
index 00000000000..b67ae78a8ac
--- /dev/null
+++ b/board/boundary/nitrogen51_e/nitrogen51_e.c
@@ -0,0 +1,598 @@
+/*
+ * Copyright (C) 2018, Boundary Devices <info@boundarydevices.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx51.h>
+#include <asm/arch/sys_proto.h>
+#include <malloc.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/fbpanel.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/spi.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <asm/arch/crm_regs.h>
+#include <i2c.h>
+#include <input.h>
+#include <power/pmic.h>
+#include <fsl_pmic.h>
+#include <mc13892.h>
+#include <usb/ehci-ci.h>
+#include "../common/bd_common.h"
+#include "../common/padctrl.h"
+
+/* Special MXCFB sync flags are here. */
+#include "../drivers/video/mxcfb.h"
+
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define AUD_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH | \
+ PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+#define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_DSE_MED | \
+ PAD_CTL_HYS)
+
+#define CEC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | \
+ PAD_CTL_DSE_MED | PAD_CTL_SRE_FAST)
+
+#define CSI_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_DSE_MED | \
+ PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+#define ESDHC_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_DVS | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define I2C2_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define RGB_PAD_CTRL (PAD_CTL_DSE_MED | PAD_CTL_SRE_FAST)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_MED | PAD_CTL_SRE_FAST)
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_DSE_MED | \
+ PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+/*
+ *
+ */
+static const iomux_v3_cfg_t init_pads[] = {
+ /* AUDMUX */
+ IOMUX_PAD_CTRL(AUD3_BB_TXD__AUD3_TXD, AUD_PAD_CTRL),
+ IOMUX_PAD_CTRL(AUD3_BB_RXD__AUD3_RXD, AUD_PAD_CTRL),
+ IOMUX_PAD_CTRL(AUD3_BB_CK__AUD3_TXC, AUD_PAD_CTRL),
+ IOMUX_PAD_CTRL(AUD3_BB_FS__AUD3_TXFS, AUD_PAD_CTRL),
+
+ /* ECSPI1 */
+ IOMUX_PAD_CTRL(CSPI1_MISO__ECSPI1_MISO, SPI_PAD_CTRL),
+ IOMUX_PAD_CTRL(CSPI1_MOSI__ECSPI1_MOSI, SPI_PAD_CTRL),
+ IOMUX_PAD_CTRL(CSPI1_SCLK__ECSPI1_SCLK, SPI_PAD_CTRL),
+#define GP_ECSPI1_PMIC IMX_GPIO_NR(4, 24)
+ IOMUX_PAD_CTRL(CSPI1_SS0__GPIO4_24, WEAK_PULLDN), /* SS0 - active high */
+#define GP_ECSPI1_FLASH IMX_GPIO_NR(4, 25)
+ IOMUX_PAD_CTRL(CSPI1_SS1__GPIO4_25, WEAK_PULLUP), /* SS1 - active low */
+
+ /* ESDHC1 - FULL sd */
+ IOMUX_PAD_CTRL(SD1_CLK__SD1_CLK, ESDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD1_CMD__SD1_CMD, ESDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD1_DATA0__SD1_DATA0, ESDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD1_DATA1__SD1_DATA1, ESDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD1_DATA2__SD1_DATA2, ESDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD1_DATA3__SD1_DATA3, ESDHC_PAD_CTRL),
+#define GP_ESDHC1_CD IMX_GPIO_NR(1, 0)
+ IOMUX_PAD_CTRL(GPIO1_0__GPIO1_0, WEAK_PULLUP),
+#define GP_ESDHC1_WP IMX_GPIO_NR(1, 1)
+ IOMUX_PAD_CTRL(GPIO1_1__GPIO1_1, WEAK_PULLUP),
+
+ /* ESDHC2 */
+ IOMUX_PAD_CTRL(SD2_CLK__SD2_CLK, ESDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD2_CMD__SD2_CMD, ESDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD2_DATA0__SD2_DATA0, ESDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD2_DATA1__SD2_DATA1, ESDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD2_DATA2__SD2_DATA2, ESDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD2_DATA3__SD2_DATA3, ESDHC_PAD_CTRL),
+#define GP_ESDHC2_SPARE IMX_GPIO_NR(4, 30)
+ IOMUX_PAD_CTRL(UART1_RTS__GPIO4_30, 0x1e5), /* spare */
+#define GPIRQ_ESDHC2 IMX_GPIO_NR(4, 31)
+ IOMUX_PAD_CTRL(UART1_CTS__GPIO4_31, 0x1e5), /* sdio_int */
+
+ /* FEC pads */
+ IOMUX_PAD_CTRL(EIM_EB2__FEC_MDIO, 0x01f5),
+ IOMUX_PAD_CTRL(NANDF_CS3__FEC_MDC, 0x2004),
+ IOMUX_PAD_CTRL(NANDF_RDY_INT__FEC_TX_CLK, 0x2180),
+ IOMUX_PAD_CTRL(NANDF_CS2__FEC_TX_ER, 0x2004), /* unused */
+ IOMUX_PAD_CTRL(NANDF_CS7__FEC_TX_EN, 0x2004),
+ IOMUX_PAD_CTRL(NANDF_D8__FEC_TDATA0, 0x2004),
+ IOMUX_PAD_CTRL(NANDF_CS4__FEC_TDATA1, 0x2004),
+ IOMUX_PAD_CTRL(NANDF_CS5__FEC_TDATA2, 0x2004),
+ IOMUX_PAD_CTRL(NANDF_CS6__FEC_TDATA3, 0x2004),
+ IOMUX_PAD_CTRL(NANDF_RB3__FEC_RX_CLK, 0x0180),
+ IOMUX_PAD_CTRL(EIM_CS4__FEC_RX_ER, 0x0180),
+ IOMUX_PAD_CTRL(NANDF_D11__FEC_RX_DV, 0x20a4),
+ IOMUX_PAD_CTRL(EIM_CS5__FEC_CRS, 0x0180),
+ IOMUX_PAD_CTRL(NANDF_RB2__FEC_COL, 0x0180),
+ IOMUX_PAD_CTRL(NANDF_D9__FEC_RDATA0, 0x2180),
+ IOMUX_PAD_CTRL(EIM_EB3__FEC_RDATA1, 0x0085),
+ IOMUX_PAD_CTRL(EIM_CS2__FEC_RDATA2, 0x0085),
+ IOMUX_PAD_CTRL(EIM_CS3__FEC_RDATA3, 0x0085),
+
+ /* GPIO_KEYS */
+#define GP_GPIOKEYS_1 IMX_GPIO_NR(1, 9)
+ IOMUX_PAD_CTRL(GPIO1_9__GPIO1_9, WEAK_PULLUP),
+#define GP_GPIOKEYS_2 IMX_GPIO_NR(1, 4)
+ IOMUX_PAD_CTRL(GPIO1_4__GPIO1_4, WEAK_PULLUP),
+#define GPIRQ_TP29 IMX_GPIO_NR(1, 3)
+ IOMUX_PAD_CTRL(GPIO1_3__GPIO1_3, WEAK_PULLUP),
+
+ /* GPIO_LEDS */
+#define GP_GPIOLEDS_GREEN IMX_GPIO_NR(1, 5)
+ IOMUX_PAD_CTRL(GPIO1_5__GPIO1_5, WEAK_PULLDN_OUTPUT),
+#define GP_GPIOLEDS_RED IMX_GPIO_NR(1, 6)
+ IOMUX_PAD_CTRL(GPIO1_6__GPIO1_6, WEAK_PULLDN_OUTPUT),
+#define GP_DRY_CONTACT IMX_GPIO_NR(1, 7)
+ IOMUX_PAD_CTRL(GPIO1_7__GPIO1_7, WEAK_PULLDN_OUTPUT),
+
+ /* Hog, adc_trig */
+ IOMUX_PAD_CTRL(CSI2_VSYNC__GPIO4_13, 0xe5),
+
+ /* hs_i2c1 */
+ IOMUX_PAD_CTRL(I2C1_CLK__I2C1_CLK, I2C_PAD_CTRL),
+ IOMUX_PAD_CTRL(I2C1_DAT__I2C1_DAT, I2C_PAD_CTRL),
+
+ /* hs_i2c1_tfp410 */
+#define GPIRQ_DVI IMX_GPIO_NR(3, 28)
+ IOMUX_PAD_CTRL(NANDF_D12__GPIO3_28, WEAK_PULLUP),
+#define GP_TFP410_I2C_SEL IMX_GPIO_NR(3, 5)
+ IOMUX_PAD_CTRL(DISPB2_SER_DIN__GPIO3_5, WEAK_PULLDN),
+
+ /* i2c1 SGTL5000 */
+#define GP_SGTL5000_HP_MUTE IMX_GPIO_NR(2, 17)
+ IOMUX_PAD_CTRL(EIM_A23__GPIO2_17, WEAK_PULLDN_OUTPUT),
+
+ /* i2c2 - ov5642 parallel camera */
+ IOMUX_PAD_CTRL(CSI1_D8__CSI1_D8, 0x85),
+ IOMUX_PAD_CTRL(CSI1_D9__CSI1_D9, 0x85),
+ IOMUX_PAD_CTRL(CSI1_D10__CSI1_D10, 0),
+ IOMUX_PAD_CTRL(CSI1_D11__CSI1_D11, 0),
+ IOMUX_PAD_CTRL(CSI1_D12__CSI1_D12, 0),
+ IOMUX_PAD_CTRL(CSI1_D13__CSI1_D13, 0),
+ IOMUX_PAD_CTRL(CSI1_D14__CSI1_D14, 0),
+ IOMUX_PAD_CTRL(CSI1_D15__CSI1_D15, 0),
+ IOMUX_PAD_CTRL(CSI1_D16__CSI1_D16, 0),
+ IOMUX_PAD_CTRL(CSI1_D17__CSI1_D17, 0),
+ IOMUX_PAD_CTRL(CSI1_D18__CSI1_D18, 0),
+ IOMUX_PAD_CTRL(CSI1_D19__CSI1_D19, 0),
+ IOMUX_PAD_CTRL(CSI1_PIXCLK__CSI1_PIXCLK, 0),
+ IOMUX_PAD_CTRL(CSI1_HSYNC__CSI1_HSYNC, 0),
+ IOMUX_PAD_CTRL(CSI1_VSYNC__CSI1_VSYNC, 0),
+ IOMUX_PAD_CTRL(CSI1_MCLK__CSI1_MCLK, 0x85),
+ IOMUX_PAD_CTRL(CSI2_D12__GPIO4_9, 0x85),
+ IOMUX_PAD_CTRL(CSI2_D13__GPIO4_10, 0x85),
+#define GP_OV5642_RESET IMX_GPIO_NR(4, 14)
+ IOMUX_PAD_CTRL(CSI2_HSYNC__GPIO4_14, WEAK_PULLDN),
+#define GP_OV5642_POWER_DOWN IMX_GPIO_NR(4, 15)
+ IOMUX_PAD_CTRL(CSI2_PIXCLK__GPIO4_15, WEAK_PULLUP),
+
+ /* ipu_disp1 */
+ IOMUX_PAD_CTRL(DI1_DISP_CLK__DI1_DISP_CLK, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DI1_PIN15__DI1_PIN15, RGB_PAD_CTRL), /* DRDY */
+ IOMUX_PAD_CTRL(DI1_PIN2__DI1_PIN2, RGB_PAD_CTRL), /* HSYNC */
+ IOMUX_PAD_CTRL(DI1_PIN3__DI1_PIN3, RGB_PAD_CTRL), /* VSYNC */
+ IOMUX_PAD_CTRL(DISP1_DAT0__DISP1_DAT0, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP1_DAT1__DISP1_DAT1, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP1_DAT2__DISP1_DAT2, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP1_DAT3__DISP1_DAT3, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP1_DAT4__DISP1_DAT4, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP1_DAT5__DISP1_DAT5, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP1_DAT6__DISP1_DAT6, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP1_DAT7__DISP1_DAT7, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP1_DAT8__DISP1_DAT8, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP1_DAT9__DISP1_DAT9, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP1_DAT10__DISP1_DAT10, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP1_DAT11__DISP1_DAT11, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP1_DAT12__DISP1_DAT12, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP1_DAT13__DISP1_DAT13, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP1_DAT14__DISP1_DAT14, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP1_DAT15__DISP1_DAT15, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP1_DAT16__DISP1_DAT16, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP1_DAT17__DISP1_DAT17, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP1_DAT18__DISP1_DAT18, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP1_DAT19__DISP1_DAT19, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP1_DAT20__DISP1_DAT20, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP1_DAT21__DISP1_DAT21, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP1_DAT22__DISP1_DAT22, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP1_DAT23__DISP1_DAT23, RGB_PAD_CTRL),
+
+ /* ipu_disp2 */
+ IOMUX_PAD_CTRL(DI2_DISP_CLK__DI2_DISP_CLK, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DI_GP4__DI2_PIN15, RGB_PAD_CTRL), /* DRDY */
+ IOMUX_PAD_CTRL(DISP2_DAT0__DISP2_DAT0, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP2_DAT1__DISP2_DAT1, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP2_DAT2__DISP2_DAT2, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP2_DAT3__DISP2_DAT3, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP2_DAT4__DISP2_DAT4, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP2_DAT5__DISP2_DAT5, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP2_DAT6__DISP2_DAT6, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP2_DAT7__DISP2_DAT7, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP2_DAT8__DISP2_DAT8, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP2_DAT9__DISP2_DAT9, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP2_DAT10__DISP2_DAT10, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP2_DAT11__DISP2_DAT11, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP2_DAT12__DISP2_DAT12, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP2_DAT13__DISP2_DAT13, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP2_DAT14__DISP2_DAT14, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(DISP2_DAT15__DISP2_DAT15, RGB_PAD_CTRL),
+
+ /* PMIC */
+#define GPIRQ_PMIC IMX_GPIO_NR(1, 8)
+ IOMUX_PAD_CTRL(GPIO1_8__GPIO1_8, WEAK_PULLUP),
+
+ /* PWM1 - lcd backlight */
+#define GP_LCD_BACKLIGHT IMX_GPIO_NR(1, 2)
+ IOMUX_PAD_CTRL(GPIO1_2__GPIO1_2, WEAK_PULLDN_OUTPUT),
+
+ /* reg 3p3v - always enabled */
+#define GP_REG3P3V_EN IMX_GPIO_NR(2, 6)
+ IOMUX_PAD_CTRL(EIM_D22__GPIO2_6, WEAK_PULLUP_OUTPUT),
+
+ /* Short pins 4 & 5 of J8 to enable uart1 */
+#define GP_UART1_REQ IMX_GPIO_NR(4, 26)
+ IOMUX_PAD_CTRL(CSPI1_RDY__GPIO4_26, WEAK_PULLUP),
+
+ /* UART2 */
+ IOMUX_PAD_CTRL(UART2_TXD__UART2_TXD, UART_PAD_CTRL),
+ IOMUX_PAD_CTRL(UART2_RXD__UART2_RXD, UART_PAD_CTRL),
+
+ /* UART3 */
+ IOMUX_PAD_CTRL(UART3_TXD__UART3_TXD, UART_PAD_CTRL),
+ IOMUX_PAD_CTRL(UART3_RXD__UART3_RXD, UART_PAD_CTRL),
+
+ /* USBH1 */
+ IOMUX_PAD_CTRL(USBH1_CLK__USBH1_CLK, 0x1e5),
+ IOMUX_PAD_CTRL(USBH1_DIR__USBH1_DIR, 0x1e5),
+ IOMUX_PAD_CTRL(USBH1_NXT__USBH1_NXT, 0x1e5),
+#define GP_USBH1_STP IMX_GPIO_NR(1, 27)
+ IOMUX_PAD_CTRL(USBH1_STP__GPIO1_27, 0x1e5),
+ IOMUX_PAD_CTRL(USBH1_DATA0__USBH1_DATA0, 0x1e5),
+ IOMUX_PAD_CTRL(USBH1_DATA1__USBH1_DATA1, 0x1e5),
+ IOMUX_PAD_CTRL(USBH1_DATA2__USBH1_DATA2, 0x1e5),
+ IOMUX_PAD_CTRL(USBH1_DATA3__USBH1_DATA3, 0x1e5),
+ IOMUX_PAD_CTRL(USBH1_DATA4__USBH1_DATA4, 0x1e5),
+ IOMUX_PAD_CTRL(USBH1_DATA5__USBH1_DATA5, 0x1e5),
+ IOMUX_PAD_CTRL(USBH1_DATA6__USBH1_DATA6, 0x1e5),
+ IOMUX_PAD_CTRL(USBH1_DATA7__USBH1_DATA7, 0x1e5),
+#define GP_USBH1_RESET IMX_GPIO_NR(2, 5)
+ IOMUX_PAD_CTRL(EIM_D21__GPIO2_5, WEAK_PULLDN_OUTPUT),
+
+ /* USBOTG */
+#define GPIRQ_USBOTG_OC IMX_GPIO_NR(3, 0)
+ IOMUX_PAD_CTRL(DI1_PIN11__GPIO3_0, PAD_CTRL_INPUT),
+};
+
+static const iomux_v3_cfg_t usbh1_stp_gpio[] = {
+ IOMUX_PAD_CTRL(USBH1_STP__GPIO1_27, 0x1e5),
+};
+
+static const iomux_v3_cfg_t usbh1_stp_usb[] = {
+ IOMUX_PAD_CTRL(USBH1_STP__USBH1_STP, 0x1e5),
+};
+
+static const iomux_v3_cfg_t usbotg_power_on_pads[] = {
+ IOMUX_PAD_CTRL(EIM_D26__KEY_COL7, WEAK_PULLDN_OUTPUT), /* low is on */
+};
+
+static const iomux_v3_cfg_t usbotg_power_off_pads[] = {
+ IOMUX_PAD_CTRL(EIM_D26__KEY_COL7, WEAK_PULLUP_OUTPUT), /* high is off */
+};
+
+/* UART1 */
+static const iomux_v3_cfg_t uart1_pads[] = {
+ IOMUX_PAD_CTRL(UART1_TXD__UART1_TXD, UART_PAD_CTRL),
+ IOMUX_PAD_CTRL(UART1_RXD__UART1_RXD, UART_PAD_CTRL),
+};
+
+#ifndef CONFIG_SPI_FLASH_ATMEL
+static const iomux_v3_cfg_t uart1_gpio_pads[] = {
+ IOMUX_PAD_CTRL(UART1_TXD__GPIO4_29, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(UART1_RXD__GPIO4_28, WEAK_PULLUP),
+};
+#endif
+
+static const struct i2c_pads_info i2c_pads[] = {
+ /* I2C1, SGTL5000 */
+ I2C_PADS_INFO_ENTRY(I2C1, EIM_D19, 2, 3, EIM_D16, 2, 0, I2C_PAD_CTRL),
+ /* I2C2 */
+ I2C_PADS_INFO_ENTRY(I2C2, EIM_D27, 2, 9, EIM_D24, 2, 8, I2C2_PAD_CTRL),
+};
+#define I2C_BUS_CNT 2
+
+#ifdef CONFIG_USB_EHCI_MX5
+int board_ehci_hcd_init(int port)
+{
+ if (port) {
+ /* Set USBH1_STP to GPIO and toggle it */
+ gpio_set_value(GP_USBH1_RESET, 0);
+ gpio_set_value(GP_USBH1_STP, 0);
+ SETUP_IOMUX_PADS(usbh1_stp_gpio);
+ mdelay(10);
+ gpio_set_value(GP_USBH1_STP, 1);
+ SETUP_IOMUX_PADS(usbh1_stp_usb);
+ mdelay(2);
+
+ gpio_set_value(GP_USBH1_RESET, 1);
+ return 0;
+ }
+ SETUP_IOMUX_PADS(usbotg_power_on_pads);
+ return 0;
+}
+
+#endif
+
+#define REV_ATLAS_LITE_1_0 0x8
+#define REV_ATLAS_LITE_1_1 0x9
+#define REV_ATLAS_LITE_2_0 0x10
+#define REV_ATLAS_LITE_2_1 0x11
+
+#define SREV3_0 0x10
+
+static unsigned get_srev(void)
+{
+ struct iim_regs *piim = (struct iim_regs *)IIM_BASE_ADDR;
+ return readl(&piim->srev);
+}
+
+static void power_init(void)
+{
+ unsigned val, sw1, sw2, sw3;
+ unsigned sw1_volt, sw2_volt, sw3_volt;
+ unsigned mode;
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
+ struct pmic *p;
+ int ret;
+
+ ret = pmic_init(CONFIG_FSL_PMIC_BUS);
+ if (ret)
+ return;
+
+ p = pmic_get("FSL_PMIC");
+ if (!p)
+ return;
+
+ /* Write needed to Power Gate 2 register */
+ pmic_reg_read(p, REG_POWER_MISC, &val);
+ val &= ~PWGT2SPIEN;
+ pmic_reg_write(p, REG_POWER_MISC, val);
+
+ /* Externally powered */
+ pmic_reg_read(p, REG_CHARGE, &val);
+ val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
+ pmic_reg_write(p, REG_CHARGE, val);
+
+ /* power up the system first */
+ pmic_reg_write(p, REG_POWER_MISC, PWUP);
+
+ /* Set core voltage to 1.1V */
+ sw1_volt = SWx_1_100V;
+ /* Setup VCC (SW2) to 1.25 */
+ sw2_volt = SWx_1_250V;
+ /* Setup 1V2_DIG1 (SW3) to 1.275 */
+ sw3_volt = SWx_1_275V;
+
+ pmic_reg_read(p, REG_SW_0, &sw1);
+ sw1 = (sw1 & ~SWx_VOLT_MASK) | sw1_volt;
+ pmic_reg_write(p, REG_SW_0, sw1);
+
+ pmic_reg_read(p, REG_SW_1, &sw2);
+ sw2 = (sw2 & ~SWx_VOLT_MASK) | sw2_volt;
+ pmic_reg_write(p, REG_SW_1, sw2);
+
+ pmic_reg_read(p, REG_SW_2, &sw3);
+ sw3 = (sw3 & ~SWx_VOLT_MASK) | sw3_volt;
+ pmic_reg_write(p, REG_SW_2, sw3);
+
+ if (get_srev() < SREV3_0) {
+ udelay(50);
+
+ /* Raise the core frequency to 800MHz */
+ writel(CONFIG_SYS_ARM_PODF, &mxc_ccm->cacrr);
+ }
+
+ pmic_reg_read(p, REG_IDENTIFICATION, &val);
+ if (((val & 0x1f) < REV_ATLAS_LITE_2_0) || (((val >> 9) & 0x3) == 0)) {
+ mode = SWMODE_PWM_PWM;
+ } else {
+ mode = SWMODE_AUTO_AUTO;
+ }
+ /* Set switchers in Auto in NORMAL mode & STANDBY mode */
+ /* Setup the switcher mode for SW1 & SW2*/
+ pmic_reg_read(p, REG_SW_4, &val);
+ val &= ~((SWMODE_MASK << SWMODE1_SHIFT) |
+ (SWMODE_MASK << SWMODE2_SHIFT));
+ val |= (mode << SWMODE1_SHIFT) |
+ (mode << SWMODE2_SHIFT);
+ pmic_reg_write(p, REG_SW_4, val);
+
+ /* Setup the switcher mode for SW3 & SW4 */
+ pmic_reg_read(p, REG_SW_5, &val);
+ val &= ~((SWMODE_MASK << SWMODE3_SHIFT) |
+ (SWMODE_MASK << SWMODE4_SHIFT));
+ val |= (mode << SWMODE3_SHIFT) |
+ (mode << SWMODE4_SHIFT);
+ pmic_reg_write(p, REG_SW_5, val);
+
+ /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.5V */
+ pmic_reg_read(p, REG_SETTING_0, &val);
+ val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
+ val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_5;
+ pmic_reg_write(p, REG_SETTING_0, val);
+
+ /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
+ pmic_reg_read(p, REG_SETTING_1, &val);
+ val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
+ val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
+ pmic_reg_write(p, REG_SETTING_1, val);
+
+ /* Configure VGEN3 and VCAM regulators to use external PNP */
+ val = VGEN3CONFIG | VCAMCONFIG;
+ pmic_reg_write(p, REG_MODE_1, val);
+ udelay(200);
+
+ /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
+ val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
+ VVIDEOEN | VAUDIOEN | VSDEN;
+ pmic_reg_write(p, REG_MODE_1, val);
+
+ udelay(500);
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg board_usdhc_cfg[] = {
+ {.esdhc_base = MMC_SDHC1_BASE_ADDR, .bus_width = 4,
+ .gp_cd = GP_ESDHC1_CD},
+ {.esdhc_base = MMC_SDHC2_BASE_ADDR, .bus_width = 4,},
+};
+#endif
+
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ if (bus == 0 && cs == 0)
+ return GP_ECSPI1_PMIC;
+ if (bus == 0 && cs == 1)
+ return GP_ECSPI1_FLASH;
+ return -1;
+}
+#endif
+
+#ifdef CONFIG_CMD_FBPANEL
+void board_enable_lcd(const struct display_info_t *di, int enable)
+{
+ gpio_direction_output(GP_LCD_BACKLIGHT, enable);
+}
+
+static const struct display_info_t displays[] = {
+ /* PIC16F616 */
+ VD_NEON_TOUCH640X240(LCD2, NULL, 0, 0x38),
+ VD_HITACHI_HVGA565(LCD2, NULL, 0, 0x38),
+ /* PMIC touch controller */
+ VD_800X300_565(LCD2, NULL, 0, 0x38),
+ VD_OKAYA_480_272(LCD, NULL, 0, 0x48),
+};
+#define display_cnt ARRAY_SIZE(displays)
+#else
+#define displays NULL
+#define display_cnt 0
+#endif
+
+static const unsigned short gpios_out_low[] = {
+ GP_OV5642_RESET, /* camera reset */
+ GP_ECSPI1_PMIC,
+ GP_GPIOLEDS_GREEN,
+ GP_GPIOLEDS_RED,
+ GP_DRY_CONTACT,
+ GP_TFP410_I2C_SEL,
+ GP_SGTL5000_HP_MUTE,
+ GP_LCD_BACKLIGHT,
+ GP_USBH1_STP,
+ GP_USBH1_RESET,
+};
+
+static const unsigned short gpios_out_high[] = {
+ GP_REG3P3V_EN,
+ GP_OV5642_POWER_DOWN,
+ GP_ECSPI1_FLASH, /* SS1 of spi nor */
+};
+
+static const unsigned short gpios_in[] = {
+ GP_ESDHC1_CD,
+ GP_ESDHC1_WP,
+ GP_ESDHC2_SPARE,
+ GPIRQ_ESDHC2,
+ GP_GPIOKEYS_1,
+ GP_GPIOKEYS_2,
+ GPIRQ_TP29,
+ GPIRQ_DVI,
+ GPIRQ_PMIC,
+ GP_UART1_REQ,
+ GPIRQ_USBOTG_OC,
+};
+
+int board_early_init_f(void)
+{
+ set_gpios_in(gpios_in, ARRAY_SIZE(gpios_in));
+ set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
+ set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
+ SETUP_IOMUX_PADS(init_pads);
+ SETUP_IOMUX_PADS(usbotg_power_off_pads);
+#ifdef CONFIG_SPI_FLASH_ATMEL
+ /* Rev 0 boards cannot test GP_UART1_REQ */
+ SETUP_IOMUX_PADS(uart1_pads);
+#else
+ /* If J8 pins 4 &5 are shorted, then enable console */
+ if (!gpio_get_value(GP_UART1_REQ))
+ SETUP_IOMUX_PADS(uart1_pads);
+ else
+ SETUP_IOMUX_PADS(uart1_gpio_pads);
+#endif
+ return 0;
+}
+
+int board_init(void)
+{
+ common_board_init(i2c_pads, I2C_BUS_CNT, 0, displays, display_cnt, 0);
+ return 0;
+}
+
+void board_late_specific_init(void)
+{
+#ifdef CONFIG_MXC_SPI
+ power_init();
+#endif
+#ifndef CONFIG_SPI_FLASH_ATMEL
+ /* Rev 0 boards cannot test GP_UART1_REQ */
+ /* If J8 pins 4 & 5 are shorted, then enable console */
+ if (!gpio_get_value(GP_UART1_REQ))
+ env_set("console", "ttymxc0");
+ /*
+ * Now that the environment is available,
+ * check if we should enable uart1
+ */
+ if (env_get("console"))
+ SETUP_IOMUX_PADS(uart1_pads);
+#endif
+}
+
+const struct button_key board_buttons[] = {
+#ifndef CONFIG_SPI_FLASH_ATMEL
+ /* Rev 0 boards cannot test GP_UART1_REQ */
+ {"uart_req", GP_UART1_REQ, 'u', 1},
+#endif
+ {"tp29", GPIRQ_TP29, '9', 1},
+ {NULL, 0, 0, 0},
+};
+
+/* i.MX51 does not support BMODE yet, maybe can't */
+#ifdef CONFIG_CMD_BMODE
+const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
diff --git a/board/boundary/nitrogen51_e/nitrogen51_e.cfg b/board/boundary/nitrogen51_e/nitrogen51_e.cfg
new file mode 100644
index 00000000000..25892d6bb5d
--- /dev/null
+++ b/board/boundary/nitrogen51_e/nitrogen51_e.cfg
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* H5PS1G63JFR-S5C-C */
+
+/* image version */
+IMAGE_VERSION 1
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM spi
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/*
+ * 512MB board uses CS0 and CS1, we will disable CS1 if ram doesn't appear to work
+ */
+#if CONFIG_DDR_MB==512
+#define USE_CSD1
+#endif
+
+/* Setting IOMUXC */
+DATA 4 0x73fa8418 0x000000e0 /* SW_PAD_CTL_PAD_EIM_D26, usb OTG power off */
+DATA 4 0x73fa8084 0x00000001 /* SW_MUX_CTL_PAD_EIM_D26, ALT1 kpp column 7, GPIO on next board */
+
+DATA 4 0x73fa88a0 0x200 /* SW_PAD_CTL_GRP_INMODE1, ddr2 input type */
+DATA 4 0x73fa850c 0x20c3 /* SW_PAD_CTL_PAD_EIM_SDODT1, 100K Pull Down, medium drive strength */
+DATA 4 0x73fa8510 0x20c3 /* SW_PAD_CTL_PAD_EIM_SDODT0, 100K Pull Down, medium drive strength */
+DATA 4 0x73fa883c 0x3 /* SW_PAD_CTL_GRP_DDR_A0, (a0-a7)Medium drive strength */
+DATA 4 0x73fa8848 0x3 /* SW_PAD_CTL_GRP_DDR_A1, (a8-a14,ba0-ba2)Medium drive strength */
+DATA 4 0x73fa84b8 0xe3 /* SW_PAD_CTL_PAD_DRAM_SDCLK1, medium drive strength */
+DATA 4 0x73fa84bc 0x43 /* SW_PAD_CTL_PAD_DRAM_SDQS0, Disable pull down */
+DATA 4 0x73fa84c0 0x43 /* SW_PAD_CTL_PAD_DRAM_SDQS1, Disable pull down */
+DATA 4 0x73fa84c4 0x43 /* SW_PAD_CTL_PAD_DRAM_SDQS2, Disable pull down */
+DATA 4 0x73fa84c8 0x43 /* SW_PAD_CTL_PAD_DRAM_SDQS3, Disable pull down */
+DATA 4 0x73fa8820 0x0 /* SW_PAD_CTL_GRP_DDRPKS, select keeper */
+DATA 4 0x73fa84a4 0x3 /* SW_PAD_CTL_PAD_DRAM_RAS, Medium Drive Strength */
+DATA 4 0x73fa84a8 0x3 /* SW_PAD_CTL_PAD_DRAM_CAS, Medium Drive Strength */
+DATA 4 0x73fa84ac 0xe3 /* SW_PAD_CTL_PAD_DRAM_SDWE, Medium Drive Strength */
+DATA 4 0x73fa84b0 0xe3 /* SW_PAD_CTL_PAD_DRAM_SDCKE0, Medium Drive Strength */
+DATA 4 0x73fa84b4 0xe3 /* SW_PAD_CTL_PAD_DRAM_SDCKE1, Medium Drive Strength */
+DATA 4 0x73fa84cc 0xe3 /* SW_PAD_CTL_PAD_DRAM_CS0, Medium Drive Strength */
+DATA 4 0x73fa84d0 0xe3 /* SW_PAD_CTL_PAD_DRAM_CS1, Medium Drive Strength */
+
+#ifndef USE_CSD1
+DATA 4 0x73fa882c 0x2 /* SW_PAD_CTL_GRP_DRAM_B4 (D24-D31), Medium drive strength */
+DATA 4 0x73fa88a4 0x2 /* SW_PAD_CTL_GRP_DRAM_B0 (D0-D7), Medium drive strength */
+DATA 4 0x73fa88ac 0x2 /* SW_PAD_CTL_GRP_DRAM_B1 (D8-D15, Medium drive strength */
+DATA 4 0x73fa88b8 0x2 /* SW_PAD_CTL_GRP_DRAM_B2 (D16-D23), Medium drive strength */
+#endif
+/*
+ * Setting DDR for micron
+ * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
+ * CAS=3 BL=4
+ */
+
+DATA 4 0x83fd9000 0x82a20000 /* ESDCTL_ESDCTL0 */
+#ifdef USE_CSD1
+DATA 4 0x83fd9008 0x82a20000 /* ESDCTL_ESDCTL1 */
+#endif
+DATA 4 0x83fd9010 0x055ad0d0 /* ESDCTL_ESDMISC */
+/*
+ * Samsung K4T1G164Q[E/F]-BCE6000 - E6 means DDR2-667, tCK, CL=3 : 5 - 8 ns
+ * K4T1G164QF-BCE6000
+ * tRFC(refresh to any command) 127.5 ns (26 clocks) Bits 31-28: 3 = 26 clocks (130 ns)(ESDCTL0[23] is double tRFC)
+ * tXSR(exit self refresh) 137.5 ns (28 clocks) Bits 27-24: 3 = 28 clocks (140 ns)
+ * tXP (exit power down to command) 2 clocks Bits 23-21: 1 = 2 clocks (10 ns)
+ * tWTR(write to read command) 7.5 ns (2 clocks) Bits 20: 1 = 2 clocks (10 ns)
+ * tRP (row precharge) 15 ns (3 clocks) Bits 19-18: 1 = 3 clocks (15 ns)
+ * tMRD(load mode register) 2 clocks Bits 17-16: 1 = 2 clocks (10 ns)
+ * tRAS(Active to precharge Command) 45 ns (9 clocks) Bits 15-12: 8 = 9 clocks (45 ns), was 7 = 8 clocks (40ns)
+ * tRRD(Active Bank A to Active B) 10 ns (2 clocks) Bits 11-10: 1 = 2 clocks (10 ns)
+ * tWR (write to precharge) 15 ns (3 clocks) Bits 7: 1 = 3 clocks (15 ns)
+ * tRCD(row to columnn delay) 15 ns (3 clocks) Bits 6-4: 2 = 3 clocks (15 ns)
+ * tRC(ACTIVE to ACTIVE, same bank) 60 ns (12 clocks) Bits 3-0: 0xb - 12 clocks(60ns), was 0xa = 11 clocks (55 ns)
+ */
+DATA 4 0x83fd9004 0x333584ab /* ESDCTL_ESDCFG0 */
+#ifdef USE_CSD1
+DATA 4 0x83fd900C 0x333584ab /* ESDCTL_ESDCFG1 */
+#endif
+
+/* Init DRAM on CS0 */
+/* ESDCTL_ESDSCR */
+DATA 4 0x83fd9014 0x04008008 /* PRECHARGE ALL */
+DATA 4 0x83fd9014 0x0000801a /* emrs(2) */
+DATA 4 0x83fd9014 0x0000801b /* emrs(3) */
+DATA 4 0x83fd9014 0x00428019 /* emrs(1) - 150 ohms ODT */
+DATA 4 0x83fd9014 0x07328018 /* MRS (load mode register) */
+DATA 4 0x83fd9014 0x04008008 /* PRECHARGE ALL */
+DATA 4 0x83fd9014 0x00008010 /* auto-refresh */
+DATA 4 0x83fd9014 0x00008010 /* auto-refresh */
+DATA 4 0x83fd9014 0x06328018 /* MRS (load mode register) */
+DATA 4 0x83fd9014 0x03c28019 /* emrs(1) - calibrate */
+DATA 4 0x83fd9014 0x00428019 /* emrs(1) - OCD calibration mode exit */
+DATA 4 0x83fd9014 0x00008000 /* nop */
+
+#ifdef USE_CSD1
+/* Init DRAM on CS1 */
+DATA 4 0x83fd9014 0x0400800c /* PRECHARGE ALL */
+DATA 4 0x83fd9014 0x0000801e /* emrs(2) */
+DATA 4 0x83fd9014 0x0000801f /* emrs(3) */
+DATA 4 0x83fd9014 0x0042801d /* emrs(1) - 50 ohms ODT vs 0x0000801d */
+DATA 4 0x83fd9014 0x0732801c /* MRS (load mode register) */
+DATA 4 0x83fd9014 0x0400800c /* PRECHARGE ALL */
+DATA 4 0x83fd9014 0x00008014 /* auto-refresh */
+DATA 4 0x83fd9014 0x00008014 /* auto-refresh */
+DATA 4 0x83fd9014 0x0632801c /* MRS (load mode register) */
+DATA 4 0x83fd9014 0x03c2801d /* emrs(1) - calibrate */
+DATA 4 0x83fd9014 0x0042801d /* emrs(1) - OCD calibration mode exit */
+DATA 4 0x83fd9014 0x00008004 /* nop */
+#endif
+
+/* Write to CTL0 */
+DATA 4 0x83fd9000 0xb2a20000 /* refresh 4 rows each refresh clock */
+
+#ifdef USE_CSD1
+/* Write to CTL1 */
+DATA 4 0x83fd9008 0xb2a20000
+#endif
+
+
+DATA 4 0x83fd9010 0x055af6d0 /* ESDMISC */
+DATA 4 0x83fd9020 0x00f48c00 /* ESD_DLY1 - D0-D7 read delay */
+DATA 4 0x83fd9024 0x00f48c00 /* ESD_DLY2 - D8-D15 read delay */
+DATA 4 0x83fd9028 0x00f48c00 /* ESD_DLY3 - D16-D23 read delay */
+DATA 4 0x83fd902c 0x00f48c00 /* ESD_DLY4 - D24-D31 read delay */
+DATA 4 0x83fd9030 0x00f48000 /* ESD_DLY5 - D0-D31 write delay */
+
+DATA 4 0x83fd9034 0x88000000 /* DQS gating delays */
+DATA 4 0x83fd9014 0x00000000 /* ESDSCR, AXI address readies normal operation */
diff --git a/board/boundary/nitrogen51_e/nitrogen_bootscript_upgrade.txt b/board/boundary/nitrogen51_e/nitrogen_bootscript_upgrade.txt
new file mode 100644
index 00000000000..8f783ff094b
--- /dev/null
+++ b/board/boundary/nitrogen51_e/nitrogen_bootscript_upgrade.txt
@@ -0,0 +1,128 @@
+offset=0x400
+erase_size=0xC0000
+
+a_uImage1=0x92000400
+a_uImage2=0x92400400
+a_script=0x92000000
+
+blew=0
+for addr in 0x83f98c24 0x83f98c28 0x83f98c2c 0x83f98c30 0x83f98c34 0x83f98c38 ; do
+ if itest.l *${addr} != 0 ; then
+ blew=1;
+ fi
+done
+
+setenv stdout serial,vga
+
+if itest.s "${ethaddr}_" != "_" ; then
+ if itest.l ${blew} != 0 ; then
+ echo already blew fuse;
+ iim read fecmac
+ else
+ echo blowing mac fuses ${ethaddr}
+ iim blow fecmac ${ethaddr}
+ fi
+fi
+
+if sf probe 1 27000000 || sf probe 1 27000000 ; then
+ echo "probed SPI ROM" ;
+else
+ echo "Error initializing EEPROM"
+ exit
+fi
+
+small=1
+if sf read ${a_uImage2} 0x80400 0x400 ; then
+ if sf read ${a_uImage1} 0x400 0x400 ; then
+ if cmp.b ${a_uImage1} ${a_uImage2} 0x400 ; then
+ else
+ small=0;
+ fi
+ fi
+fi
+if itest.l ${small} != 0 ; then
+ rev="rev0_"
+ erase_size=0x7e000
+ echo "small spi-nor chip, erase size changed to 0x7e000"
+fi
+
+if itest.l *0x83fd9008 < 0 ; then
+ size_str="512m"
+else
+ size_str="256m"
+fi
+
+if itest.s "${uboot_defconfig}_" == "_" ; then
+ uboot_defconfig="nitrogen51_e_${rev}${size_str}"
+fi
+
+echo "check U-Boot with u-boot.${uboot_defconfig}" ;
+
+mw.b ${a_uImage1} 0xff ${erase_size}
+
+if fatload mmc 0 ${a_uImage1} u-boot.${uboot_defconfig} ; then
+else
+ echo "File u-boot.${uboot_defconfig} not found on SD card" ;
+ exit
+fi
+echo "read $filesize bytes from SD card" ;
+if sf read ${a_uImage2} ${offset} ${filesize} ; then
+else
+ echo "Error reading boot loader from EEPROM" ;
+ exit
+fi
+
+if cmp.b ${a_uImage1} ${a_uImage2} ${filesize} ; then
+ echo "------- U-Boot versions match" ;
+ echo "------- upgrade not needed" ;
+ if itest.s "${next}_" != "_" ; then
+ if fatload mmc 0 ${a_script} ${next} ; then
+ source ${a_script}
+ else
+ echo "${next} not found on SD card"
+ fi
+ fi
+ exit
+fi
+
+echo "Need U-Boot upgrade" ;
+echo "Program in 5 seconds" ;
+for n in 5 4 3 2 1 ; do
+ echo $n ;
+ sleep 1 ;
+done
+echo "erasing" ;
+sf erase 0 ${erase_size} ;
+
+# two steps to prevent bricking
+echo "programming" ;
+a1=0x92000800
+o1=0x800
+s1=${filesize}
+sf write ${a1} ${o1} ${s1} ;
+sf write ${a_uImage1} $offset 0x400 ;
+
+
+echo "verifying" ;
+if sf read ${a_uImage2} $offset $filesize ; then
+else
+ echo "Error re-reading EEPROM" ;
+ exit
+fi
+if cmp.b ${a_uImage1} ${a_uImage2} $filesize ; then
+else
+ echo "Read verification error" ;
+ exit
+fi
+
+if itest.s "${next}_" != "_" ; then
+ if fatload mmc 0 ${a_script} ${next} ; then
+ source ${a_script}
+ else
+ echo "${next} not found on mmc 0"
+ fi
+fi
+
+while echo "---- U-Boot upgraded. reset" ; do
+ sleep 120
+done
diff --git a/configs/nitrogen51_e_256m_defconfig b/configs/nitrogen51_e_256m_defconfig
new file mode 100644
index 00000000000..a30aefe6dd3
--- /dev/null
+++ b/configs/nitrogen51_e_256m_defconfig
@@ -0,0 +1,70 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
+CONFIG_SYS_TEXT_BASE=0x97800000
+CONFIG_TARGET_NITROGEN51_E=y
+# CONFIG_CMD_BMODE is not set
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen51_e/nitrogen51_e.cfg,MX51,DDR_MB=256,DEFCONFIG=\"nitrogen51_e_256m\""
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x92000000
+CONFIG_FASTBOOT_BUF_SIZE=0x26000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FSL_ESDHC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
+CONFIG_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Boundary"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen51_e_512m_defconfig b/configs/nitrogen51_e_512m_defconfig
new file mode 100644
index 00000000000..17b21d56551
--- /dev/null
+++ b/configs/nitrogen51_e_512m_defconfig
@@ -0,0 +1,70 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
+CONFIG_SYS_TEXT_BASE=0x97800000
+CONFIG_TARGET_NITROGEN51_E=y
+# CONFIG_CMD_BMODE is not set
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen51_e/nitrogen51_e.cfg,MX51,DDR_MB=512,DEFCONFIG=\"nitrogen51_e_512m\""
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x92000000
+CONFIG_FASTBOOT_BUF_SIZE=0x26000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FSL_ESDHC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
+CONFIG_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Boundary"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen51_e_rev0_256m_defconfig b/configs/nitrogen51_e_rev0_256m_defconfig
new file mode 100644
index 00000000000..9c652775d6a
--- /dev/null
+++ b/configs/nitrogen51_e_rev0_256m_defconfig
@@ -0,0 +1,68 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
+CONFIG_SYS_TEXT_BASE=0x97800000
+CONFIG_TARGET_NITROGEN51_E=y
+# CONFIG_CMD_BMODE is not set
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen51_e/nitrogen51_e.cfg,MX51,DDR_MB=256,DEFCONFIG=\"nitrogen51_e_rev0_256m\""
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x92000000
+CONFIG_FASTBOOT_BUF_SIZE=0x26000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FSL_ESDHC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
+CONFIG_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Boundary"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/nitrogen51_e_rev0_512m_defconfig b/configs/nitrogen51_e_rev0_512m_defconfig
new file mode 100644
index 00000000000..cc4e975b6a9
--- /dev/null
+++ b/configs/nitrogen51_e_rev0_512m_defconfig
@@ -0,0 +1,68 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX5=y
+CONFIG_SYS_TEXT_BASE=0x97800000
+CONFIG_TARGET_NITROGEN51_E=y
+# CONFIG_CMD_BMODE is not set
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen51_e/nitrogen51_e.cfg,MX51,DDR_MB=512,DEFCONFIG=\"nitrogen51_e_rev0_512m\""
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x92000000
+CONFIG_FASTBOOT_BUF_SIZE=0x26000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FSL_ESDHC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_PHYLIB=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
+CONFIG_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Boundary"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/nitrogen51_e.h b/include/configs/nitrogen51_e.h
new file mode 100644
index 00000000000..e7833df4261
--- /dev/null
+++ b/include/configs/nitrogen51_e.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2018 Boundary Devices, Inc.
+ *
+ * Configuration settings for the Boundary Devices nitrogen51_e
+ * board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/***********************************/
+
+#define CONFIG_SYS_BOOTM_LEN 0x1000000
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/mach-imx/gpio.h>
+
+#define CONFIG_SYS_FSL_CLK
+
+/* ATAGs */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_LOADADDR 0x92000000
+#define CONFIG_SYS_TEXT_BASE 0x97800000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#ifndef CONFIG_BOOTDELAY
+#define CONFIG_BOOTDELAY 3
+#endif
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* Miscellaneous configurable options */
+#undef CONFIG_CMD_IMLS
+#define CONFIG_SYS_CBSIZE 512
+#define CONFIG_SYS_MAXARGS 32
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/* MMC */
+#define CONFIG_BOUNCE_BUFFER
+#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
+#define CONFIG_SYS_FSL_ESDHC_NUM 1
+
+/* Fuses */
+#define CONFIG_CMD_FUSE
+/************************************/
+#define CONFIG_FSL_IIM
+
+#define CONFIG_SYS_DDR_CLKSEL 0
+
+#define IMX_FEC_BASE FEC_BASE_ADDR
+#define CONFIG_MII
+#if 1
+#define CONFIG_MXC_USB_PORT 1
+#define CONFIG_MXC_USB_PORTSC PORT_PTS_ULPI
+#define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#endif
+#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100
+
+#define CONFIG_MACH_TYPE 3169
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (40 * 1024 * 1024)
+#define CONFIG_MXC_UART_BASE UART1_BASE
+#define CONFIG_SYS_ARM_PODF 0
+#define CONFIG_FSL_PMIC_BUS 0
+#define CONFIG_FSL_PMIC_CS 0
+#define CONFIG_FSL_PMIC_CLK 2500000
+#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
+#define CONFIG_FSL_PMIC_BITLEN 32
+
+#define CONFIG_FEC_MXC_PHYADDR 5
+#define ETH_PHY_MASK (0xf << 4)
+
+/* PMIC Configs */
+#define CONFIG_POWER
+#define CONFIG_POWER_SPI
+#define CONFIG_POWER_FSL
+#define CONFIG_FSL_PMIC_BUS 0
+#define CONFIG_FSL_PMIC_CS 0
+#define CONFIG_SF_DEFAULT_CS 1
+
+#define CONFIG_FSL_PMIC_CLK 2500000
+#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
+#define CONFIG_FSL_PMIC_BITLEN 32
+
+#define CONFIG_POWER_FSL_MC13892
+#define CONFIG_RTC_MC13XXX
+#if 0
+#define CONFIG_MMC_TRACE
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1
+#endif
+
+#if 1
+#define CONFIG_VIDEO_LOGO
+#endif
+#define BD_I2C_MASK 3
+#define BD_CONSOLE "ttymxc0"
+#define BD_MMC_DISKS "0"
+#define BD_LOG_LEVEL "7"
+#define BD_CMA "2M"
+
+#ifdef CONFIG_SPI_FLASH_ATMEL
+/* only rev0 needs this for the small 512K at45db041d spi-nor */
+#define CONFIG_ENV_OFFSET 0x7e000
+#else
+/* default to no console */
+#define BD_CONSOLE_STR ""
+#endif
+
+
+#include "boundary.h"
+
+#define CONFIG_EXTRA_ENV_SETTINGS BD_BOUNDARY_ENV_SETTINGS \
+ "fb_lcd=off\0" \
+ "fb_lcd2=off\0" \
+
+#endif /* __CONFIG_H */
--
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