From 390c2e3e8ffcf7a2b338e69072905fc2c4acfb4c Mon Sep 17 00:00:00 2001
From: Troy Kisky <troy.kisky@boundarydevices.com>
Date: Wed, 11 Feb 2015 16:14:16 -0700
Subject: [PATCH] snap: initial addition, Boundary Devices board
snap: use nitrogen6x/ddr-setup.cfg
snap: add CONFIG_CMD_GPIO
snap: use boundary.h
snap: add CONFIG_SPI_FLASH_SPANSION
snap: snap_defconfig add CONFIG_BLOCK_CACHE
snap: use common code for eth init
snap: eth.c now in common directory
snap: move misc_init_r/do_kbd to common
snap: move mmc_init/ dram_init/ overwrite_console/ common_board_init/ splash_screen_prepare/ board_cfb_skip to common
snap: use common 1066mhz_4x256mx16.cfg
snap: add CONFIG_SPI_FLASH_GIGADEVICE: to defconfigs
snap: use common ddr script
snap: port to v2018.07
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
snap: update to v2017.01
snap: update to v2017.03
Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
---
arch/arm/mach-imx/mx6/Kconfig | 4 +
board/boundary/snap/Kconfig | 20 ++
board/boundary/snap/MAINTAINERS | 6 +
board/boundary/snap/Makefile | 6 +
board/boundary/snap/snap.c | 316 ++++++++++++++++++++++++++++++++
board/boundary/snap/snap2g.cfg | 47 +++++
configs/snap_defconfig | 72 ++++++++
include/configs/snap.h | 29 +++
8 files changed, 500 insertions(+)
create mode 100644 board/boundary/snap/Kconfig
create mode 100644 board/boundary/snap/MAINTAINERS
create mode 100644 board/boundary/snap/Makefile
create mode 100644 board/boundary/snap/snap.c
create mode 100644 board/boundary/snap/snap2g.cfg
create mode 100644 configs/snap_defconfig
create mode 100644 include/configs/snap.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 6d7efdd96cb..d6e9df6a974 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -494,6 +494,9 @@ config TARGET_S
config TARGET_SES
bool "ses"
+config TARGET_SNAP
+ bool "snap"
+
config TARGET_YS
bool "ys"
select MX6SX
@@ -667,6 +670,7 @@ source "board/boundary/per/Kconfig"
source "board/boundary/rc/Kconfig"
source "board/boundary/s/Kconfig"
source "board/boundary/ses/Kconfig"
+source "board/boundary/snap/Kconfig"
source "board/boundary/ys/Kconfig"
source "board/bticino/mamoj/Kconfig"
source "board/ccv/xpress/Kconfig"
diff --git a/board/boundary/snap/Kconfig b/board/boundary/snap/Kconfig
new file mode 100644
index 00000000000..bdec0474f6a
--- /dev/null
+++ b/board/boundary/snap/Kconfig
@@ -0,0 +1,20 @@
+if TARGET_SNAP
+
+config SYS_CPU
+ default "armv7"
+
+config SYS_BOARD
+ default "snap"
+
+config SYS_VENDOR
+ default "boundary"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "snap"
+
+source "board/boundary/common/Kconfig"
+
+endif
diff --git a/board/boundary/snap/MAINTAINERS b/board/boundary/snap/MAINTAINERS
new file mode 100644
index 00000000000..25106715328
--- /dev/null
+++ b/board/boundary/snap/MAINTAINERS
@@ -0,0 +1,6 @@
+TA BOARD
+M: Troy Kisky <troy.kisky@boundarydevices.com>
+S: Maintained
+F: board/boundary/snap/
+F: include/configs/snap.h
+F: configs/snap_defconfig
diff --git a/board/boundary/snap/Makefile b/board/boundary/snap/Makefile
new file mode 100644
index 00000000000..1436c406b55
--- /dev/null
+++ b/board/boundary/snap/Makefile
@@ -0,0 +1,6 @@
+#
+# Copyright (C) 2014, Boundary Devices <info@boundarydevices.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+obj-y := snap.o
diff --git a/board/boundary/snap/snap.c b/board/boundary/snap/snap.c
new file mode 100644
index 00000000000..36cae461185
--- /dev/null
+++ b/board/boundary/snap/snap.c
@@ -0,0 +1,316 @@
+/*
+ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2014, Boundary Devices <info@boundarydevices.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+#include <malloc.h>
+#include <asm/arch/mx6-pins.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/fbpanel.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/spi.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <asm/arch/crm_regs.h>
+#include <i2c.h>
+#include <input.h>
+#include <splash.h>
+#include <usb/ehci-ci.h>
+#include "../common/bd_common.h"
+#include "../common/padctrl.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+#define USDHC_CLK_PAD_CTRL (PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (USDHC_CLK_PAD_CTRL | PAD_CTL_PUS_47K_UP)
+
+/*
+ *
+ */
+static const iomux_v3_cfg_t init_pads[] = {
+ /* ECSPI1 pads (serial nor eeprom) */
+ IOMUX_PAD_CTRL(EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
+ IOMUX_PAD_CTRL(EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
+ IOMUX_PAD_CTRL(EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
+#define GP_ECSPI1_NOR_CS IMX_GPIO_NR(3, 19)
+ IOMUX_PAD_CTRL(EIM_D19__GPIO3_IO19, WEAK_PULLUP),
+
+ /* ENET pads that don't change for PHY reset */
+ IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, PAD_CTRL_ENET_MDIO),
+ IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, PAD_CTRL_ENET_MDC),
+ IOMUX_PAD_CTRL(RGMII_TXC__RGMII_TXC, PAD_CTRL_ENET_TX),
+ IOMUX_PAD_CTRL(RGMII_TD0__RGMII_TD0, PAD_CTRL_ENET_TX),
+ IOMUX_PAD_CTRL(RGMII_TD1__RGMII_TD1, PAD_CTRL_ENET_TX),
+ IOMUX_PAD_CTRL(RGMII_TD2__RGMII_TD2, PAD_CTRL_ENET_TX),
+ IOMUX_PAD_CTRL(RGMII_TD3__RGMII_TD3, PAD_CTRL_ENET_TX),
+ IOMUX_PAD_CTRL(RGMII_TX_CTL__RGMII_TX_CTL, PAD_CTRL_ENET_TX),
+ IOMUX_PAD_CTRL(ENET_REF_CLK__ENET_TX_CLK, PAD_CTRL_ENET_TX),
+ /* pin 42 PHY nRST */
+#define GP_RGMII_PHY_RESET IMX_GPIO_NR(1, 27)
+ IOMUX_PAD_CTRL(ENET_RXD0__GPIO1_IO27, OUTPUT_40OHM),
+#define GP_ENET_PHY_INT IMX_GPIO_NR(1, 28)
+ IOMUX_PAD_CTRL(ENET_TX_EN__GPIO1_IO28, WEAK_PULLUP),
+
+ /* i2c2 ov5640 mipi Camera controls */
+#define GP_OV5640_MIPI_POWER_DOWN IMX_GPIO_NR(6, 4)
+ IOMUX_PAD_CTRL(CSI0_DAT18__GPIO6_IO04, WEAK_PULLUP),
+#define GP_OV5640_MIPI_RESET IMX_GPIO_NR(6, 5)
+ IOMUX_PAD_CTRL(CSI0_DAT19__GPIO6_IO05, WEAK_PULLDN),
+
+
+ /* I2C1 - rtc */
+ /* I2C2 - mipi camera, pcie */
+ /* I2C3 - sata */
+#define GP_I2C3_EN_SATA IMX_GPIO_NR(3, 0)
+ IOMUX_PAD_CTRL(EIM_DA0__GPIO3_IO00, WEAK_PULLDN),
+
+#define GP_PCIE_RESET IMX_GPIO_NR(6, 31)
+ IOMUX_PAD_CTRL(EIM_BCLK__GPIO6_IO31, OUTPUT_40OHM),
+
+/* PWM3 goes to mipi camera */
+#define GP_PWM3 IMX_GPIO_NR(1, 17)
+ IOMUX_PAD_CTRL(SD1_DAT1__GPIO1_IO17, OUTPUT_40OHM),
+
+ /* rtc */
+#define GPIRQ_RTC_RV4162 IMX_GPIO_NR(4, 6)
+ IOMUX_PAD_CTRL(KEY_COL0__GPIO4_IO06, WEAK_PULLUP),
+
+ /* Sata hard drive detect, high if present */
+#define GP_HD_DETECT IMX_GPIO_NR(2, 30)
+ IOMUX_PAD_CTRL(EIM_EB2__GPIO2_IO30, WEAK_PULLUP),
+
+ /* Test points */
+#define GP_TP71 IMX_GPIO_NR(1, 30)
+ IOMUX_PAD_CTRL(ENET_TXD0__GPIO1_IO30, WEAK_PULLUP),
+#define GP_TP75 IMX_GPIO_NR(3, 8)
+ IOMUX_PAD_CTRL(GPIO_18__GPIO7_IO13, WEAK_PULLUP),
+
+ /* reg_usbotg_vbus */
+#define GP_REG_USBOTG IMX_GPIO_NR(3, 22)
+ IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, WEAK_PULLDN_OUTPUT),
+
+ /* UART1 */
+ IOMUX_PAD_CTRL(SD3_DAT7__UART1_TX_DATA, UART_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DAT6__UART1_RX_DATA, UART_PAD_CTRL),
+
+ /* UART2 - console */
+ IOMUX_PAD_CTRL(EIM_D26__UART2_TX_DATA, UART_PAD_CTRL),
+ IOMUX_PAD_CTRL(EIM_D27__UART2_RX_DATA, UART_PAD_CTRL),
+
+ /* UART3 */
+ IOMUX_PAD_CTRL(EIM_D24__UART3_TX_DATA, UART_PAD_CTRL),
+ IOMUX_PAD_CTRL(EIM_D25__UART3_RX_DATA, UART_PAD_CTRL),
+ IOMUX_PAD_CTRL(EIM_D23__UART3_CTS_B, UART_PAD_CTRL),
+ IOMUX_PAD_CTRL(EIM_D31__UART3_RTS_B, UART_PAD_CTRL),
+
+ /* USBH1 */
+ IOMUX_PAD_CTRL(EIM_D30__USB_H1_OC, WEAK_PULLUP),
+#define GP_USBH1_HUB_RESET IMX_GPIO_NR(2, 28)
+ IOMUX_PAD_CTRL(EIM_EB0__GPIO2_IO28, WEAK_PULLDN_OUTPUT),
+
+ /* USBOTG */
+ IOMUX_PAD_CTRL(GPIO_1__USB_OTG_ID, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(KEY_COL4__USB_OTG_OC, WEAK_PULLUP),
+
+ /* USDHC3 - micro SD card */
+ IOMUX_PAD_CTRL(SD3_CLK__SD3_CLK, USDHC_CLK_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
+#define GP_USDHC3_CD IMX_GPIO_NR(7, 0)
+ IOMUX_PAD_CTRL(SD3_DAT5__GPIO7_IO00, WEAK_PULLUP),
+
+ /* USDHC4 - eMMC */
+ IOMUX_PAD_CTRL(SD4_CLK__SD4_CLK, USDHC_CLK_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD4_CMD__SD4_CMD, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD4_DAT4__SD4_DATA4, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD4_DAT5__SD4_DATA5, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD4_DAT6__SD4_DATA6, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD4_DAT7__SD4_DATA7, USDHC_PAD_CTRL),
+#define GP_EMMC_RESET IMX_GPIO_NR(2, 6)
+ IOMUX_PAD_CTRL(NANDF_D6__GPIO2_IO06, WEAK_PULLUP),
+
+
+ /* J8 on DB */
+#define GP_GIO1 IMX_GPIO_NR(1, 15)
+ IOMUX_PAD_CTRL(SD2_DAT0__GPIO1_IO15, WEAK_PULLUP),
+#define GP_GIO2 IMX_GPIO_NR(1, 14)
+ IOMUX_PAD_CTRL(SD2_DAT1__GPIO1_IO14, WEAK_PULLUP),
+#define GP_GIO3 IMX_GPIO_NR(1, 13)
+ IOMUX_PAD_CTRL(SD2_DAT2__GPIO1_IO13, WEAK_PULLUP),
+#define GP_GIO4 IMX_GPIO_NR(1, 12)
+ IOMUX_PAD_CTRL(SD2_DAT3__GPIO1_IO12, WEAK_PULLUP),
+#define GP_GIO5 IMX_GPIO_NR(1, 11)
+ IOMUX_PAD_CTRL(SD2_CMD__GPIO1_IO11, WEAK_PULLUP),
+#define GP_GIO6 IMX_GPIO_NR(1, 18)
+ IOMUX_PAD_CTRL(SD1_CMD__GPIO1_IO18, WEAK_PULLUP),
+
+ /* spares on DB */
+#define GP_IO00 IMX_GPIO_NR(4, 21)
+ IOMUX_PAD_CTRL(DISP0_DAT0__GPIO4_IO21, WEAK_PULLUP),
+#define GP_IO01 IMX_GPIO_NR(4, 22)
+ IOMUX_PAD_CTRL(DISP0_DAT1__GPIO4_IO22, WEAK_PULLUP),
+#define GP_IO02 IMX_GPIO_NR(4, 23)
+ IOMUX_PAD_CTRL(DISP0_DAT2__GPIO4_IO23, WEAK_PULLUP),
+#define GP_IO03 IMX_GPIO_NR(4, 24)
+ IOMUX_PAD_CTRL(DISP0_DAT3__GPIO4_IO24, WEAK_PULLUP),
+#define GP_IO04 IMX_GPIO_NR(4, 25)
+ IOMUX_PAD_CTRL(DISP0_DAT4__GPIO4_IO25, WEAK_PULLUP),
+#define GP_IO05 IMX_GPIO_NR(4, 26)
+ IOMUX_PAD_CTRL(DISP0_DAT5__GPIO4_IO26, WEAK_PULLUP),
+#define GP_IO06 IMX_GPIO_NR(4, 5)
+ IOMUX_PAD_CTRL(GPIO_19__GPIO4_IO05, WEAK_PULLUP),
+#define GP_IO07 IMX_GPIO_NR(1, 0)
+ IOMUX_PAD_CTRL(GPIO_0__GPIO1_IO00, WEAK_PULLUP),
+#define GP_IO08 IMX_GPIO_NR(1, 0)
+ IOMUX_PAD_CTRL(SD1_CLK__GPIO1_IO20, WEAK_PULLUP),
+#define GP_IO09 IMX_GPIO_NR(1, 10)
+ IOMUX_PAD_CTRL(SD2_CLK__GPIO1_IO10, WEAK_PULLUP),
+#define GP_IO10 IMX_GPIO_NR(1, 21)
+ IOMUX_PAD_CTRL(SD1_DAT3__GPIO1_IO21, WEAK_PULLUP),
+};
+
+static const struct i2c_pads_info i2c_pads[] = {
+ /* I2C1, rv4162 */
+ I2C_PADS_INFO_ENTRY(I2C1, EIM_D21, 3, 21, EIM_D28, 3, 28, I2C_PAD_CTRL),
+ I2C_PADS_INFO_ENTRY(I2C2, KEY_COL3, 4, 12, KEY_ROW3, 4, 13, I2C_PAD_CTRL),
+ I2C_PADS_INFO_ENTRY(I2C3, GPIO_5, 1, 05, GPIO_16, 7, 11, I2C_PAD_CTRL),
+};
+#define I2C_BUS_CNT 3
+
+#ifdef CONFIG_USB_EHCI_MX6
+int board_ehci_hcd_init(int port)
+{
+ return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+ int gp = port ? GP_USBH1_HUB_RESET : GP_REG_USBOTG;
+ gpio_set_value(gp, on);
+ return 0;
+}
+
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg board_usdhc_cfg[] = {
+ {.esdhc_base = USDHC3_BASE_ADDR, .bus_width = 4,
+ .gp_cd = GP_USDHC3_CD},
+ {.esdhc_base = USDHC4_BASE_ADDR, .bus_width = 8,
+ .gp_reset = GP_EMMC_RESET},
+};
+#endif
+
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ int gp = (bus == 0 && cs == 0) ? GP_ECSPI1_NOR_CS : -1;
+ return gp;
+}
+#endif
+
+static const unsigned short gpios_out_low[] = {
+ GP_RGMII_PHY_RESET,
+ GP_I2C3_EN_SATA,
+ GP_PCIE_RESET,
+ GP_USBH1_HUB_RESET,
+ GP_REG_USBOTG,
+ GP_EMMC_RESET,
+ GP_OV5640_MIPI_RESET,
+};
+
+static const unsigned short gpios_out_high[] = {
+ GP_ECSPI1_NOR_CS,
+ GP_PWM3,
+ GP_OV5640_MIPI_POWER_DOWN,
+};
+
+static const unsigned short gpios_in[] = {
+ GP_ENET_PHY_INT,
+ GPIRQ_RTC_RV4162,
+ GP_HD_DETECT,
+ GP_TP71,
+ GP_TP75,
+ GP_USDHC3_CD,
+ GP_GIO1,
+ GP_GIO2,
+ GP_GIO3,
+ GP_GIO4,
+ GP_GIO5,
+ GP_GIO6,
+ GP_IO00,
+ GP_IO01,
+ GP_IO02,
+ GP_IO03,
+ GP_IO04,
+ GP_IO05,
+ GP_IO06,
+ GP_IO07,
+ GP_IO08,
+ GP_IO09,
+ GP_IO10,
+};
+
+int board_early_init_f(void)
+{
+ set_gpios_in(gpios_in, ARRAY_SIZE(gpios_in));
+ set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
+ set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
+ SETUP_IOMUX_PADS(init_pads);
+ return 0;
+}
+
+int board_init(void)
+{
+ common_board_init(i2c_pads, I2C_BUS_CNT, IOMUXC_GPR1_OTG_ID_GPIO1,
+ NULL, 0, GP_HD_DETECT);
+ return 0;
+}
+
+const struct button_key board_buttons[] = {
+ {"b1", GP_TP71, '1', 1},
+ {NULL, 0, 0, 0},
+};
+
+#ifdef CONFIG_CMD_BMODE
+const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+ {"mmc1", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)}, /* 8-bit eMMC */
+ {NULL, 0},
+};
+#endif
diff --git a/board/boundary/snap/snap2g.cfg b/board/boundary/snap/snap2g.cfg
new file mode 100644
index 00000000000..a07c8c39d82
--- /dev/null
+++ b/board/boundary/snap/snap2g.cfg
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2014 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM spi
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* NC YET */
+#define MX6_MMDC_P0_MPDGCTRL0_VAL 0x42740304
+#define MX6_MMDC_P0_MPDGCTRL1_VAL 0x026e0265
+#define MX6_MMDC_P1_MPDGCTRL0_VAL 0x02750306
+#define MX6_MMDC_P1_MPDGCTRL1_VAL 0x02720244
+#define MX6_MMDC_P0_MPRDDLCTL_VAL 0x463d4041
+#define MX6_MMDC_P1_MPRDDLCTL_VAL 0x42413c47
+#define MX6_MMDC_P0_MPWRDLCTL_VAL 0x37414441
+#define MX6_MMDC_P1_MPWRDLCTL_VAL 0x4633473b
+#define MX6_MMDC_P0_MPWLDECTRL0_VAL 0x0025001f
+#define MX6_MMDC_P0_MPWLDECTRL1_VAL 0x00290027
+#define MX6_MMDC_P1_MPWLDECTRL0_VAL 0x001f002b
+#define MX6_MMDC_P1_MPWLDECTRL1_VAL 0x000f0029
+#define WALAT 1
+
+#include "../common/mx6/ddr-setup.cfg"
+#define RANK 0
+#define BUS_WIDTH 64
+/* BOM removed, not supported */
+#include "../common/mx6/1066mhz_256mx16.cfg"
+#include "../common/mx6/clocks.cfg"
diff --git a/configs/snap_defconfig b/configs/snap_defconfig
new file mode 100644
index 00000000000..bf701a07f56
--- /dev/null
+++ b/configs/snap_defconfig
@@ -0,0 +1,72 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_TARGET_SNAP=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/snap/snap2g.cfg,MX6Q,DDR_MB=2048,DEFCONFIG=\"snap\""
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SATA=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DWC_AHSATA=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12000000
+CONFIG_FASTBOOT_BUF_SIZE=0x26000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_FSL_ESDHC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
+CONFIG_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Boundary"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/snap.h b/include/configs/snap.h
new file mode 100644
index 00000000000..7f74cb0146d
--- /dev/null
+++ b/include/configs/snap.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Boundary Devices Snap board
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+#define CONFIG_MACH_TYPE 3778
+
+#define CONFIG_CONSOLE_MUX
+
+#define CONFIG_FEC_MXC_PHYADDR 7
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define BD_I2C_MASK 7
+#define BD_MMC_DISKS "1"
+#define BD_MMC_UMS_DISKS "1 0"
+
+#include "boundary.h"
+#define CONFIG_EXTRA_ENV_SETTINGS BD_BOUNDARY_ENV_SETTINGS \
+ "disable_giga=1\0" \
+
+#endif /* __CONFIG_H */
--
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