diff --git a/board/boundary/nitrogen8mm_som/lpddr4_timing.c b/board/boundary/nitrogen8mm_som/lpddr4_timing.c
index 5759f04f1fc4206d980187ebf6c6c73b32299580..9202ba63e54e206c8c4852017100df73b13afed5 100644
--- a/board/boundary/nitrogen8mm_som/lpddr4_timing.c
+++ b/board/boundary/nitrogen8mm_som/lpddr4_timing.c
@@ -12,6 +12,22 @@
#define LPDDR4_CS 0x3 /* 2 ranks */
+#if CONFIG_DDR_MB == 2048
+ /* Address map is from MSB 28: cs, r14, r13-r0, b2-b0, c9-c0 */
+#define VAL_DDRC_ADDRMAP0 0x00000016
+#define VAL_DDRC_ADDRMAP6 0x0f070707
+#elif CONFIG_DDR_MB == 3072
+ /* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
+#define VAL_DDRC_ADDRMAP0 0x00000015
+#define VAL_DDRC_ADDRMAP6 0x48080707
+#elif CONFIG_DDR_MB == 4096
+ /* Address map is from MSB 29: cs, r15, r14, r13-r0, b2-b0, c9-c0 */
+#define VAL_DDRC_ADDRMAP0 0x00000017
+#define VAL_DDRC_ADDRMAP6 0x07070707
+#else
+#error unsupported memory size
+#endif
+
static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
/* Start to config, default 3200mbps */
/* dis_dq=1, indicates no reads or writes are issued to SDRAM */
@@ -60,13 +76,13 @@ static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
{ DDRC_DRAMTMG2(0), 0x070E1213 },
/* address mapping */
- { DDRC_ADDRMAP0(0), 0x00000016 },
+ { DDRC_ADDRMAP0(0), VAL_DDRC_ADDRMAP0 },
{ DDRC_ADDRMAP3(0), 0x00000000 },
{ DDRC_ADDRMAP4(0), 0x00001f1f },
{ DDRC_ADDRMAP1(0), 0x00080808 },
{ DDRC_ADDRMAP2(0), 0x00000000 },
{ DDRC_ADDRMAP5(0), 0x07070707 },
- { DDRC_ADDRMAP6(0), 0x0F070707 },
+ { DDRC_ADDRMAP6(0), VAL_DDRC_ADDRMAP6 },
{ DDRC_ADDRMAP7(0), 0x00000f0f },
/* performance setting */
diff --git a/board/boundary/nitrogen8mm_som/nitrogen8mm_som.c b/board/boundary/nitrogen8mm_som/nitrogen8mm_som.c
index fff139c62a700b77341ba3c80d2fb837caafdecd..f2df500f6c7ac2c45e5e8b030401b5e0f7251034 100644
--- a/board/boundary/nitrogen8mm_som/nitrogen8mm_som.c
+++ b/board/boundary/nitrogen8mm_som/nitrogen8mm_som.c
@@ -120,14 +120,26 @@ int board_postclk_init(void)
}
#endif
+#define MAX_LOW_SIZE (0x100000000ULL - CONFIG_SYS_SDRAM_BASE)
+#define SDRAM_SIZE ((1ULL * CONFIG_DDR_MB) << 20)
+
+#if SDRAM_SIZE > MAX_LOW_SIZE
+#define MEM_SIZE MAX_LOW_SIZE
+#else
+#define MEM_SIZE SDRAM_SIZE
+#endif
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = SDRAM_SIZE;
+ return 0;
+}
+
int dram_init(void)
{
/* rom_pointer[1] contains the size of TEE occupies */
- if (rom_pointer[1])
- gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
- else
- gd->ram_size = PHYS_SDRAM_SIZE;
-
+ gd->ram_size = MEM_SIZE - rom_pointer[1];
return 0;
}
diff --git a/configs/nitrogen8mm_som_4g_defconfig b/configs/nitrogen8mm_som_4g_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..71800f5de3648ce91b6ab075761e77ca2e4dd99b
--- /dev/null
+++ b/configs/nitrogen8mm_som_4g_defconfig
@@ -0,0 +1,97 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_NITROGEN8MM_SOM=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0x30860000
+CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-nitrogen8mm_som"
+CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL_TEXT_BASE=0x7E1000,DDR_MB=4096,DEFCONFIG=\"nitrogen8mm_som_4g\""
+CONFIG_BOOTSTAGE_STASH_SIZE=4096
+CONFIG_ARCH_MISC_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET_SUPPORT=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SYS_FSL_SEC_LE=y
+CONFIG_IMX8M_LPDDR4=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x42800000
+CONFIG_FASTBOOT_BUF_SIZE=0x40000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_FSL_ESDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
+CONFIG_FEC_PHY_BITBANG=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DEBUG_UART_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Boundary"
+CONFIG_USB_GADGET_VENDOR_NUM=0x3016
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0001
+CONFIG_CI_UDC=y
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
+CONFIG_USBNET_DEVADDR="00:19:b8:00:00:02"
+CONFIG_USBNET_HOST_ADDR="00:19:b8:00:00:01"
+CONFIG_USB_HOST_ETHER=y