drivers/ddr/fsl · 19060bd886381a58cfe335c2f13b6111ed936dd5 · Jack Humbert / reform-boundary-uboot

Forked from Reform / reform-boundary-uboot

26745 commits behind the upstream repository.

driver/ddr: Fix DDR register timing_cfg_8

York Sun authored 10 years ago

The field wrtord_bg should add 2 clocks if on the fly chop is enabled,
according to DDR controller manual for DDR4.

Signed-off-by: York Sun <yorksun@freescale.com>

3d75ec95

History

3d75ec95 10 years ago

History

Name	Last commit	Last update
..
Makefile
arm_ddr_gen3.c
ctrl_regs.c
ddr1_dimm_params.c
ddr2_dimm_params.c
ddr3_dimm_params.c
ddr4_dimm_params.c
fsl_ddr_gen4.c
interactive.c
lc_common_dimm_params.c
main.c
mpc85xx_ddr_gen1.c
mpc85xx_ddr_gen2.c
mpc85xx_ddr_gen3.c
mpc86xx_ddr.c
options.c
util.c