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Reform / reform-boundary-uboot
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David Wu
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The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 10-bits width. Signed-off-by:David Wu <david.wu@rock-chips.com> Acked-by:
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by:
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