diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 80bbc1805fbf0cfbd3b251216c15af8c95711db2..4ae4a6c83dc2c59e5d37dcbea9688ad48bcb5168 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -37,6 +37,10 @@
#ifdef CONFIG_FSL_CAAM
#include <fsl_sec.h>
#endif
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
+#include <asm/fsl_pamu.h>
+#include <fsl_secboot_err.h>
+#endif
#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
#include <nand.h>
#include <errno.h>
@@ -432,8 +436,7 @@ void fsl_erratum_a007212_workaround(void)
ulong cpu_init_f(void)
{
extern void m8560_cpm_reset (void);
-#if defined(CONFIG_SYS_DCSRBAR_PHYS) || \
- (defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET))
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
#if defined(CONFIG_SECURE_BOOT)
@@ -465,12 +468,6 @@ ulong cpu_init_f(void)
#if defined(CONFIG_SYS_CPC_REINIT_F)
disable_cpc_sram();
#endif
-
-#if defined(CONFIG_FSL_CORENET)
- /* Put PAMU in bypass mode */
- out_be32(&gur->pamubypenr, FSL_CORENET_PAMU_BYPASS);
-#endif
-
#endif
#ifdef CONFIG_CPM2
@@ -954,6 +951,11 @@ int cpu_init_r(void)
fman_enet_init();
#endif
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
+ if (pamu_init() < 0)
+ fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
+#endif
+
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile b/arch/powerpc/cpu/mpc8xxx/Makefile
index ac45e0e3dfffed036b6438f991b47d29503199e5..c5592cdbb324cff9fe411ca4ad770d64b09c54c9 100644
--- a/arch/powerpc/cpu/mpc8xxx/Makefile
+++ b/arch/powerpc/cpu/mpc8xxx/Makefile
@@ -24,5 +24,6 @@ obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_FSL_LBC) += fsl_lbc.o
obj-$(CONFIG_SYS_SRIO) += srio.o
obj-$(CONFIG_FSL_LAW) += law.o
+obj-$(CONFIG_FSL_CORENET) += fsl_pamu.o pamu_table.o
endif
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
new file mode 100644
index 0000000000000000000000000000000000000000..9421f1ebf6f312c081cb9f295e33fc5c4b1707ca
--- /dev/null
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c
@@ -0,0 +1,433 @@
+/*
+ * FSL PAMU driver
+ *
+ * Copyright 2012-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/log2.h>
+#include <malloc.h>
+#include <asm/fsl_pamu.h>
+
+struct paace *ppaact;
+struct paace *sec;
+unsigned long fspi;
+
+static inline int __ilog2_roundup_64(uint64_t val)
+{
+ if ((val & (val - 1)) == 0)
+ return __ilog2_u64(val);
+ else
+ return __ilog2_u64(val) + 1;
+}
+
+
+static inline int count_lsb_zeroes(unsigned long val)
+{
+ return ffs(val) - 1;
+}
+
+static unsigned int map_addrspace_size_to_wse(uint64_t addrspace_size)
+{
+ /* window size is 2^(WSE+1) bytes */
+ return count_lsb_zeroes(addrspace_size >> PAMU_PAGE_SHIFT) +
+ PAMU_PAGE_SHIFT - 1;
+}
+
+static unsigned int map_subwindow_cnt_to_wce(uint32_t subwindow_cnt)
+{
+ /* window count is 2^(WCE+1) bytes */
+ return count_lsb_zeroes(subwindow_cnt) - 1;
+}
+
+static void pamu_setup_default_xfer_to_host_ppaace(struct paace *ppaace)
+{
+ set_bf(ppaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_PRIMARY);
+ set_bf(ppaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
+ PAACE_M_COHERENCE_REQ);
+}
+
+static void pamu_setup_default_xfer_to_host_spaace(struct paace *spaace)
+{
+ set_bf(spaace->addr_bitfields, PAACE_AF_PT, PAACE_PT_SECONDARY);
+ set_bf(spaace->domain_attr.to_host.coherency_required, PAACE_DA_HOST_CR,
+ PAACE_M_COHERENCE_REQ);
+}
+
+/** Sets up PPAACE entry for specified liodn
+ *
+ * @param[in] liodn Logical IO device number
+ * @param[in] win_addr starting address of DSA window
+ * @param[in] win-size size of DSA window
+ * @param[in] omi Operation mapping index -- if ~omi == 0 then omi
+ not defined
+ * @param[in] stashid cache stash id for associated cpu -- if ~stashid == 0
+ then stashid not defined
+ * @param[in] snoopid snoop id for hardware coherency -- if ~snoopid == 0
+ then snoopid not defined
+ * @param[in] subwin_cnt number of sub-windows
+ *
+ * @return Returns 0 upon success else error code < 0 returned
+ */
+static int pamu_config_ppaace(uint32_t liodn, uint64_t win_addr,
+ uint64_t win_size, uint32_t omi,
+ uint32_t snoopid, uint32_t stashid,
+ uint32_t subwin_cnt)
+{
+ struct paace *ppaace;
+
+ if ((win_size & (win_size - 1)) || win_size < PAMU_PAGE_SIZE)
+ return -1;
+
+ if (win_addr & (win_size - 1))
+ return -2;
+
+ if (liodn > NUM_PPAACT_ENTRIES) {
+ printf("Entries in PPACT not sufficient\n");
+ return -3;
+ }
+
+ ppaace = &ppaact[liodn];
+
+ /* window size is 2^(WSE+1) bytes */
+ set_bf(ppaace->addr_bitfields, PPAACE_AF_WSE,
+ map_addrspace_size_to_wse(win_size));
+
+ pamu_setup_default_xfer_to_host_ppaace(ppaace);
+
+ if (sizeof(phys_addr_t) > 4)
+ ppaace->wbah = (u64)win_addr >> (PAMU_PAGE_SHIFT + 20);
+ else
+ ppaace->wbah = 0;
+
+ set_bf(ppaace->addr_bitfields, PPAACE_AF_WBAL,
+ (win_addr >> PAMU_PAGE_SHIFT));
+
+ /* set up operation mapping if it's configured */
+ if (omi < OME_NUMBER_ENTRIES) {
+ set_bf(ppaace->impl_attr, PAACE_IA_OTM, PAACE_OTM_INDEXED);
+ ppaace->op_encode.index_ot.omi = omi;
+ } else if (~omi != 0) {
+ return -3;
+ }
+
+ /* configure stash id */
+ if (~stashid != 0)
+ set_bf(ppaace->impl_attr, PAACE_IA_CID, stashid);
+
+ /* configure snoop id */
+ if (~snoopid != 0)
+ ppaace->domain_attr.to_host.snpid = snoopid;
+
+ if (subwin_cnt) {
+ /* window count is 2^(WCE+1) bytes */
+ set_bf(ppaace->impl_attr, PAACE_IA_WCE,
+ map_subwindow_cnt_to_wce(subwin_cnt));
+ set_bf(ppaace->addr_bitfields, PPAACE_AF_MW, 0x1);
+ ppaace->fspi = fspi;
+ fspi = fspi + DEFAULT_NUM_SUBWINDOWS - 1;
+ } else {
+ set_bf(ppaace->addr_bitfields, PAACE_AF_AP, PAACE_AP_PERMS_ALL);
+ }
+
+ asm volatile("sync" : : : "memory");
+ /* Mark the ppace entry valid */
+ ppaace->addr_bitfields |= PAACE_V_VALID;
+ asm volatile("sync" : : : "memory");
+
+ return 0;
+}
+
+static int pamu_config_spaace(uint32_t liodn,
+ uint64_t subwin_size, uint64_t subwin_addr, uint64_t size,
+ uint32_t omi, uint32_t snoopid, uint32_t stashid)
+{
+ struct paace *paace;
+ /* Align start addr of subwin to subwindoe size */
+ uint64_t sec_addr = subwin_addr & ~(subwin_size - 1);
+ uint64_t end_addr = subwin_addr + size;
+ int size_shift = __ilog2_u64(subwin_size);
+ uint64_t win_size = 0;
+ uint32_t index, swse;
+ unsigned long fspi_idx;
+
+ /* Recalculate the size */
+ size = end_addr - sec_addr;
+
+ if (!subwin_size)
+ return -1;
+
+ if (liodn > NUM_PPAACT_ENTRIES) {
+ printf("LIODN No programmed %d > no. of PPAACT entries %d\n",
+ liodn, NUM_PPAACT_ENTRIES);
+ return -1;
+ }
+
+ while (sec_addr < end_addr) {
+ debug("sec_addr < end_addr is %llx < %llx\n", sec_addr,
+ end_addr);
+ paace = &ppaact[liodn];
+ if (!paace)
+ return -1;
+ fspi_idx = paace->fspi;
+
+ /* Calculating the win_size here as if we map in index 0,
+ paace entry woudl need to be programmed for SWSE */
+ win_size = end_addr - sec_addr;
+ win_size = 1 << __ilog2_roundup_64(win_size);
+
+ if (win_size > subwin_size)
+ win_size = subwin_size;
+ else if (win_size < PAMU_PAGE_SIZE)
+ win_size = PAMU_PAGE_SIZE;
+
+ debug("win_size is %llx\n", win_size);
+
+ swse = map_addrspace_size_to_wse(win_size);
+ index = sec_addr >> size_shift;
+
+ if (index == 0) {
+ set_bf(paace->win_bitfields, PAACE_WIN_SWSE, swse);
+ set_bf(paace->addr_bitfields, PAACE_AF_AP,
+ PAACE_AP_PERMS_ALL);
+ sec_addr += subwin_size;
+ continue;
+ }
+
+ paace = sec + fspi_idx + index - 1;
+
+ debug("SPAACT:Writing at location %p, index %d\n", paace,
+ index);
+
+ pamu_setup_default_xfer_to_host_spaace(paace);
+ set_bf(paace->addr_bitfields, SPAACE_AF_LIODN, liodn);
+ set_bf(paace->addr_bitfields, PAACE_AF_AP, PAACE_AP_PERMS_ALL);
+
+ /* configure snoop id */
+ if (~snoopid != 0)
+ paace->domain_attr.to_host.snpid = snoopid;
+
+ if (paace->addr_bitfields & PAACE_V_VALID) {
+ debug("Reached overlap condition\n");
+ debug("%d < %d\n", get_bf(paace->win_bitfields,
+ PAACE_WIN_SWSE), swse);
+ if (get_bf(paace->win_bitfields, PAACE_WIN_SWSE) < swse)
+ set_bf(paace->win_bitfields, PAACE_WIN_SWSE,
+ swse);
+ } else {
+ set_bf(paace->win_bitfields, PAACE_WIN_SWSE, swse);
+ }
+
+ paace->addr_bitfields |= PAACE_V_VALID;
+ sec_addr += subwin_size;
+ }
+
+ return 0;
+}
+
+int pamu_init(void)
+{
+ u32 base_addr = CONFIG_SYS_PAMU_ADDR;
+ struct ccsr_pamu *regs;
+ u32 i = 0;
+ u64 ppaact_phys, ppaact_lim, ppaact_size;
+ u64 spaact_phys, spaact_lim, spaact_size;
+
+ ppaact_size = sizeof(struct paace) * NUM_PPAACT_ENTRIES;
+ spaact_size = sizeof(struct paace) * NUM_SPAACT_ENTRIES;
+
+ /* Allocate space for Primary PAACT Table */
+ ppaact = memalign(PAMU_TABLE_ALIGNMENT, ppaact_size);
+ if (!ppaact)
+ return -1;
+ memset(ppaact, 0, ppaact_size);
+
+ /* Allocate space for Secondary PAACT Table */
+ sec = memalign(PAMU_TABLE_ALIGNMENT, spaact_size);
+ if (!sec)
+ return -1;
+ memset(sec, 0, spaact_size);
+
+ ppaact_phys = virt_to_phys((void *)ppaact);
+ ppaact_lim = ppaact_phys + ppaact_size;
+
+ spaact_phys = (uint64_t)virt_to_phys((void *)sec);
+ spaact_lim = spaact_phys + spaact_size;
+
+ /* Configure all PAMU's */
+ for (i = 0; i < CONFIG_NUM_PAMU; i++) {
+ regs = (struct ccsr_pamu *)base_addr;
+
+ out_be32(®s->ppbah, ppaact_phys >> 32);
+ out_be32(®s->ppbal, (uint32_t)ppaact_phys);
+
+ out_be32(®s->pplah, (ppaact_lim) >> 32);
+ out_be32(®s->pplal, (uint32_t)ppaact_lim);
+
+ if (sec != NULL) {
+ out_be32(®s->spbah, spaact_phys >> 32);
+ out_be32(®s->spbal, (uint32_t)spaact_phys);
+ out_be32(®s->splah, spaact_lim >> 32);
+ out_be32(®s->splal, (uint32_t)spaact_lim);
+ }
+ asm volatile("sync" : : : "memory");
+
+ base_addr += PAMU_OFFSET;
+ }
+
+ return 0;
+}
+
+void pamu_enable(void)
+{
+ u32 i = 0;
+ u32 base_addr = CONFIG_SYS_PAMU_ADDR;
+ for (i = 0; i < CONFIG_NUM_PAMU; i++) {
+ setbits_be32((void *)base_addr + PAMU_PCR_OFFSET,
+ PAMU_PCR_PE);
+ asm volatile("sync" : : : "memory");
+ base_addr += PAMU_OFFSET;
+ }
+}
+
+void pamu_reset(void)
+{
+ u32 i = 0;
+ u32 base_addr = CONFIG_SYS_PAMU_ADDR;
+ struct ccsr_pamu *regs;
+
+ for (i = 0; i < CONFIG_NUM_PAMU; i++) {
+ regs = (struct ccsr_pamu *)base_addr;
+ /* Clear PPAACT Base register */
+ out_be32(®s->ppbah, 0);
+ out_be32(®s->ppbal, 0);
+ out_be32(®s->pplah, 0);
+ out_be32(®s->pplal, 0);
+ out_be32(®s->spbah, 0);
+ out_be32(®s->spbal, 0);
+ out_be32(®s->splah, 0);
+ out_be32(®s->splal, 0);
+
+ clrbits_be32((void *)regs + PAMU_PCR_OFFSET, PAMU_PCR_PE);
+ asm volatile("sync" : : : "memory");
+ base_addr += PAMU_OFFSET;
+ }
+}
+
+void pamu_disable(void)
+{
+ u32 i = 0;
+ u32 base_addr = CONFIG_SYS_PAMU_ADDR;
+
+
+ for (i = 0; i < CONFIG_NUM_PAMU; i++) {
+ clrbits_be32((void *)base_addr + PAMU_PCR_OFFSET, PAMU_PCR_PE);
+ asm volatile("sync" : : : "memory");
+ base_addr += PAMU_OFFSET;
+ }
+}
+
+
+static uint64_t find_max(uint64_t arr[], int num)
+{
+ int i = 0;
+ int max = 0;
+ for (i = 1 ; i < num; i++)
+ if (arr[max] < arr[i])
+ max = i;
+
+ return arr[max];
+}
+
+static uint64_t find_min(uint64_t arr[], int num)
+{
+ int i = 0;
+ int min = 0;
+ for (i = 1 ; i < num; i++)
+ if (arr[min] > arr[i])
+ min = i;
+
+ return arr[min];
+}
+
+static uint32_t get_win_cnt(uint64_t size)
+{
+ uint32_t win_cnt = DEFAULT_NUM_SUBWINDOWS;
+
+ while (win_cnt && (size/win_cnt) < PAMU_PAGE_SIZE)
+ win_cnt >>= 1;
+
+ return win_cnt;
+}
+
+int config_pamu(struct pamu_addr_tbl *tbl, int num_entries, uint32_t liodn)
+{
+ int i = 0;
+ int ret = 0;
+ uint32_t num_sec_windows = 0;
+ uint32_t num_windows = 0;
+ uint64_t min_addr, max_addr;
+ uint64_t size;
+ uint64_t subwin_size;
+ int sizebit;
+
+ min_addr = find_min(tbl->start_addr, num_entries);
+ max_addr = find_max(tbl->end_addr, num_entries);
+ size = max_addr - min_addr + 1;
+
+ if (!size)
+ return -1;
+
+ sizebit = __ilog2_roundup_64(size);
+ size = 1 << sizebit;
+ debug("min start_addr is %llx\n", min_addr);
+ debug("max end_addr is %llx\n", max_addr);
+ debug("size found is %llx\n", size);
+
+ if (size < PAMU_PAGE_SIZE)
+ size = PAMU_PAGE_SIZE;
+
+ while (1) {
+ min_addr = min_addr & ~(size - 1);
+ if (min_addr + size > max_addr)
+ break;
+ size <<= 1;
+ if (!size)
+ return -1;
+ }
+ debug("PAACT :Base addr is %llx\n", min_addr);
+ debug("PAACT : Size is %llx\n", size);
+ num_windows = get_win_cnt(size);
+ /* For a single window, no spaact entries are required
+ * sec_sub_window count = 0 */
+ if (num_windows > 1)
+ num_sec_windows = num_windows;
+ else
+ num_sec_windows = 0;
+
+ ret = pamu_config_ppaace(liodn, min_addr,
+ size , -1, -1, -1, num_sec_windows);
+
+ if (ret < 0)
+ return ret;
+
+ debug("configured ppace\n");
+
+ if (num_sec_windows) {
+ subwin_size = size >> count_lsb_zeroes(num_sec_windows);
+ debug("subwin_size is %llx\n", subwin_size);
+
+ for (i = 0; i < num_entries; i++) {
+ ret = pamu_config_spaace(liodn,
+ subwin_size, tbl->start_addr[i] - min_addr,
+ tbl->size[i], -1, -1, -1);
+
+ if (ret < 0)
+ return ret;
+ }
+ }
+
+ return ret;
+}
diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c b/arch/powerpc/cpu/mpc8xxx/pamu_table.c
new file mode 100644
index 0000000000000000000000000000000000000000..26c5ea4fd7a9fd13a73e54aa0f7dbd1d630092b0
--- /dev/null
+++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2012-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_pamu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, int *num_entries)
+{
+ int i = 0;
+ int j;
+
+ tbl->start_addr[i] =
+ (uint64_t)virt_to_phys((void *)CONFIG_SYS_SDRAM_BASE);
+ tbl->size[i] = (phys_size_t)(min(gd->ram_size, CONFIG_MAX_MEM_MAPPED));
+ tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1;
+
+ i++;
+#ifdef CONFIG_SYS_FLASH_BASE_PHYS
+ tbl->start_addr[i] =
+ (uint64_t)virt_to_phys((void *)CONFIG_SYS_FLASH_BASE_PHYS);
+ tbl->size[i] = 256 * 1024 * 1024; /* 256MB flash */
+ tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1;
+
+ i++;
+#endif
+ debug("PAMU address\t\t\tsize\n");
+ for (j = 0; j < i ; j++)
+ debug("%llx \t\t\t%llx\n", tbl->start_addr[j], tbl->size[j]);
+
+ *num_entries = i;
+}
+
+int sec_config_pamu_table(uint32_t liodn_ns, uint32_t liodn_s)
+{
+ struct pamu_addr_tbl tbl;
+ int num_entries = 0;
+ int ret = 0;
+
+ construct_pamu_addr_table(&tbl, &num_entries);
+
+ ret = config_pamu(&tbl, num_entries, liodn_ns);
+ if (ret)
+ return ret;
+
+ ret = config_pamu(&tbl, num_entries, liodn_s);
+ if (ret)
+ return ret;
+
+ return ret;
+}
diff --git a/arch/powerpc/include/asm/fsl_pamu.h b/arch/powerpc/include/asm/fsl_pamu.h
new file mode 100644
index 0000000000000000000000000000000000000000..93a7cae972a0b32d6e2b1fd046361e8e33132e41
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_pamu.h
@@ -0,0 +1,169 @@
+/*
+ * Copyright 2012-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __PAMU_H
+#define __PAMU_H
+
+#define CONFIG_NUM_PAMU 16
+#define NUM_PPAACT_ENTRIES 512
+#define NUM_SPAACT_ENTRIES 256
+
+/* PAMU_OFFSET to the next pamu space in ccsr */
+#define PAMU_OFFSET 0x1000
+
+#define PAMU_TABLE_ALIGNMENT 0x00001000
+
+#define PAMU_PAGE_SHIFT 12
+#define PAMU_PAGE_SIZE 4096U
+
+#define PAACE_M_COHERENCE_REQ 0x01
+
+#define PAACE_DA_HOST_CR 0x80
+#define PAACE_DA_HOST_CR_SHIFT 7
+
+#define PAACE_AF_PT 0x00000002
+#define PAACE_AF_PT_SHIFT 1
+
+#define PAACE_PT_PRIMARY 0x0
+#define PAACE_PT_SECONDARY 0x1
+
+#define PPAACE_AF_WBAL 0xfffff000
+#define PPAACE_AF_WBAL_SHIFT 12
+
+#define OME_NUMBER_ENTRIES 16 /* based on P4080 2.0 silicon plan */
+
+#define PAACE_IA_CID 0x00FF0000
+#define PAACE_IA_CID_SHIFT 16
+#define PAACE_IA_WCE 0x000000F0
+#define PAACE_IA_WCE_SHIFT 4
+#define PAACE_IA_ATM 0x0000000C
+#define PAACE_IA_ATM_SHIFT 2
+#define PAACE_IA_OTM 0x00000003
+#define PAACE_IA_OTM_SHIFT 0
+
+#define PAACE_OTM_NO_XLATE 0x00
+#define PAACE_OTM_IMMEDIATE 0x01
+#define PAACE_OTM_INDEXED 0x02
+#define PAACE_OTM_RESERVED 0x03
+#define PAACE_ATM_NO_XLATE 0x00
+#define PAACE_ATM_WINDOW_XLATE 0x01
+#define PAACE_ATM_PAGE_XLATE 0x02
+#define PAACE_ATM_WIN_PG_XLATE \
+ (PAACE_ATM_WINDOW_XLATE | PAACE_ATM_PAGE_XLATE)
+#define PAACE_WIN_TWBAL 0xfffff000
+#define PAACE_WIN_TWBAL_SHIFT 12
+#define PAACE_WIN_SWSE 0x00000fc0
+#define PAACE_WIN_SWSE_SHIFT 6
+
+#define PAACE_AF_AP 0x00000018
+#define PAACE_AF_AP_SHIFT 3
+#define PAACE_AF_DD 0x00000004
+#define PAACE_AF_DD_SHIFT 2
+#define PAACE_AF_PT 0x00000002
+#define PAACE_AF_PT_SHIFT 1
+#define PAACE_AF_V 0x00000001
+#define PAACE_AF_V_SHIFT 0
+#define PPAACE_AF_WSE 0x00000fc0
+#define PPAACE_AF_WSE_SHIFT 6
+#define PPAACE_AF_MW 0x00000020
+#define PPAACE_AF_MW_SHIFT 5
+
+#define PAACE_AP_PERMS_DENIED 0x0
+#define PAACE_AP_PERMS_QUERY 0x1
+#define PAACE_AP_PERMS_UPDATE 0x2
+#define PAACE_AP_PERMS_ALL 0x3
+
+#define SPAACE_AF_LIODN 0xffff0000
+#define SPAACE_AF_LIODN_SHIFT 16
+#define PAACE_V_VALID 0x1
+
+#define set_bf(v, m, x) (v = ((v) & ~(m)) | (((x) << \
+ (m##_SHIFT)) & (m)))
+#define get_bf(v, m) (((v) & (m)) >> (m##_SHIFT))
+
+#define DEFAULT_NUM_SUBWINDOWS 128
+#define PAMU_PCR_OFFSET 0xc10
+#define PAMU_PCR_PE 0x40000000
+
+struct pamu_addr_tbl {
+ phys_addr_t start_addr[10];
+ phys_addr_t end_addr[10];
+ phys_size_t size[10];
+};
+
+struct paace {
+ /* PAACE Offset 0x00 */
+ uint32_t wbah; /* only valid for Primary PAACE */
+ uint32_t addr_bitfields; /* See P/S PAACE_AF_* */
+
+ /* PAACE Offset 0x08 */
+ /* Interpretation of first 32 bits dependent on DD above */
+ union {
+ struct {
+ /* Destination ID, see PAACE_DID_* defines */
+ uint8_t did;
+ /* Partition ID */
+ uint8_t pid;
+ /* Snoop ID */
+ uint8_t snpid;
+ /* coherency_required : 1 reserved : 7 */
+ uint8_t coherency_required; /* See PAACE_DA_* */
+ } to_host;
+ struct {
+ /* Destination ID, see PAACE_DID_* defines */
+ uint8_t did;
+ uint8_t reserved1;
+ uint16_t reserved2;
+ } to_io;
+ } domain_attr;
+
+ /* Implementation attributes + window count + address & operation
+ * translation modes
+ */
+ uint32_t impl_attr; /* See PAACE_IA_* */
+
+ /* PAACE Offset 0x10 */
+ /* Translated window base address */
+ uint32_t twbah;
+ uint32_t win_bitfields; /* See PAACE_WIN_* */
+
+ /* PAACE Offset 0x18 */
+ /* first secondary paace entry */
+ uint32_t fspi; /* only valid for Primary PAACE */
+ union {
+ struct {
+ uint8_t ioea;
+ uint8_t moea;
+ uint8_t ioeb;
+ uint8_t moeb;
+ } immed_ot;
+ struct {
+ uint16_t reserved;
+ uint16_t omi;
+ } index_ot;
+ } op_encode;
+
+ /* PAACE Offset 0x20 */
+ uint32_t reserved1[2]; /* not currently implemented */
+
+ /* PAACE Offset 0x28 */
+ uint32_t reserved2[2]; /* not currently implemented */
+
+ /* PAACE Offset 0x30 */
+ uint32_t reserved3[2]; /* not currently implemented */
+
+ /* PAACE Offset 0x38 */
+ uint32_t reserved4[2]; /* not currently implemented */
+
+};
+
+int pamu_init(void);
+void pamu_enable(void);
+void pamu_disable(void);
+int config_pamu(struct pamu_addr_tbl *tbl, int num_entries, uint32_t liodn);
+int sec_config_pamu_table(uint32_t liodn_ns, uint32_t liodn_s);
+
+#endif
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index fd8aba42a55017df455604541e2a38023cd6c8b6..53ca6d94d644b93bc553bc6f02c811db232a15a0 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1935,7 +1935,6 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
u8 res24[64];
u32 pblsr; /* Preboot loader status */
u32 pamubypenr; /* PAMU bypass enable */
-#define FSL_CORENET_PAMU_BYPASS 0xffff0000
u32 dmacr1; /* DMA control */
u8 res25[4];
u32 gensr1; /* General status */
@@ -2774,6 +2773,21 @@ typedef struct ccsr_pme {
u8 res4[0x400];
} ccsr_pme_t;
+struct ccsr_pamu {
+ u32 ppbah;
+ u32 ppbal;
+ u32 pplah;
+ u32 pplal;
+ u32 spbah;
+ u32 spbal;
+ u32 splah;
+ u32 splal;
+ u32 obah;
+ u32 obal;
+ u32 olah;
+ u32 olal;
+};
+
#ifdef CONFIG_SYS_FSL_RAID_ENGINE
struct ccsr_raide {
u8 res0[0x543];
@@ -2854,6 +2868,7 @@ struct ccsr_pman {
#define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000
#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
#define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000
+#define CONFIG_SYS_FSL_PAMU_OFFSET 0x20000
#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
#define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
#define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000
@@ -3067,6 +3082,8 @@ struct ccsr_pman {
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
#define CONFIG_SYS_FSL_SRIO_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
+#define CONFIG_SYS_PAMU_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET)
#define CONFIG_SYS_PCI1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 4566ec3671b0c465020690c72f70ff9eb83a99b6..b766470ce224cf40fef613e97500af08f9baefd2 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -12,6 +12,9 @@
#include "jr.h"
#include "jobdesc.h"
#include "desc_constr.h"
+#ifdef CONFIG_FSL_CORENET
+#include <asm/fsl_pamu.h>
+#endif
#define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
#define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
@@ -534,18 +537,38 @@ int sec_init(void)
uint32_t mcr = sec_in32(&sec->mcfgr);
int ret = 0;
+#ifdef CONFIG_FSL_CORENET
+ uint32_t liodnr;
+ uint32_t liodn_ns;
+ uint32_t liodn_s;
+#endif
+
mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT);
#ifdef CONFIG_PHYS_64BIT
mcr |= (1 << MCFGR_PS_SHIFT);
#endif
sec_out32(&sec->mcfgr, mcr);
+#ifdef CONFIG_FSL_CORENET
+ liodnr = sec_in32(&sec->jrliodnr[0].ls);
+ liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT;
+ liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT;
+#endif
+
ret = jr_init();
if (ret < 0) {
printf("SEC initialization failed\n");
return -1;
}
+#ifdef CONFIG_FSL_CORENET
+ ret = sec_config_pamu_table(liodn_ns, liodn_s);
+ if (ret < 0)
+ return -1;
+
+ pamu_enable();
+#endif
+
if (get_rng_vid() >= 4) {
if (rng_init() < 0) {
printf("RNG instantiation failed\n");