diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index 414565cb65bb94e477ae1798851a1b154f8cb68d..03b6c86349cc795299dbeb174e9e97e53943ab4e 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -303,11 +303,11 @@ void cpu_init_f (volatile immap_t * im)
struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR;
/* Configure interface. */
- setbits_be32((void *)ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
+ setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
/* Wait for clock to stabilize */
do {
- temp = in_be32((void *)ehci->control);
+ temp = in_be32(&ehci->control);
udelay(1000);
} while (!(temp & PHY_CLK_VALID));
#endif
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index ec1d689b3558f3f54b2269da3158c8baa6d749b2..940d4a8b91c62ac418159468f6f701de06ad5886 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -37,6 +37,7 @@ COBJS-$(CONFIG_USB_SL811HS) += sl811-hcd.o
COBJS-$(CONFIG_USB_EHCI) += ehci-hcd.o
COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o
COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
+COBJS-$(CONFIG_USB_EHCI_KIRKWOOD) += ehci-kirkwood.o
COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index bf148c4e2429e588641739edd6a4518f46260ba6..c674929725230a9bb94b9bbe07a802ea56b7611b 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -41,15 +41,15 @@ int ehci_hcd_init(void)
struct usb_ehci *ehci;
ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR;
- hccr = (struct ehci_hccr *)((uint32_t)ehci->caplength);
+ hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
hcor = (struct ehci_hcor *)((uint32_t) hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
/* Set to Host mode */
- setbits_le32((void *)ehci->usbmode, CM_HOST);
+ setbits_le32(&ehci->usbmode, CM_HOST);
- out_be32((void *)ehci->snoop1, SNOOP_SIZE_2GB);
- out_be32((void *)ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
+ out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
+ out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
/* Init phy */
if (!strcmp(getenv("usb_phy_type"), "utmi"))
@@ -58,13 +58,13 @@ int ehci_hcd_init(void)
out_le32(&(hcor->or_portsc[0]), PORT_PTS_ULPI);
/* Enable interface. */
- setbits_be32((void *)ehci->control, USB_EN);
+ setbits_be32(&ehci->control, USB_EN);
- out_be32((void *)ehci->prictrl, 0x0000000c);
- out_be32((void *)ehci->age_cnt_limit, 0x00000040);
- out_be32((void *)ehci->sictrl, 0x00000001);
+ out_be32(&ehci->prictrl, 0x0000000c);
+ out_be32(&ehci->age_cnt_limit, 0x00000040);
+ out_be32(&ehci->sictrl, 0x00000001);
- in_le32((void *)ehci->usbmode);
+ in_le32(&ehci->usbmode);
return 0;
}
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index bbd547b3e357fb8011702d34d9a26c9b546e5a27..423ea5d814f72db68a097c2f377ca8bf234fb0c4 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -716,7 +716,7 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
goto unknown;
}
/* unblock posted writes */
- ehci_readl(&hcor->or_usbcmd);
+ (void) ehci_readl(&hcor->or_usbcmd);
break;
case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
reg = ehci_readl(status_reg);
@@ -745,7 +745,7 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer,
}
ehci_writel(status_reg, reg);
/* unblock posted write */
- ehci_readl(&hcor->or_usbcmd);
+ (void) ehci_readl(&hcor->or_usbcmd);
break;
default:
debug("Unknown request\n");
diff --git a/drivers/usb/host/ehci-kirkwood.c b/drivers/usb/host/ehci-kirkwood.c
new file mode 100644
index 0000000000000000000000000000000000000000..64997b85ce5984887112bce4890e69148c5b893a
--- /dev/null
+++ b/drivers/usb/host/ehci-kirkwood.c
@@ -0,0 +1,108 @@
+/*
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <usb.h>
+#include "ehci.h"
+#include "ehci-core.h"
+#include <asm/arch/kirkwood.h>
+
+#define rdl(off) readl(KW_USB20_BASE + (off))
+#define wrl(off, val) writel((val), KW_USB20_BASE + (off))
+
+#define USB_WINDOW_CTRL(i) (0x320 + ((i) << 4))
+#define USB_WINDOW_BASE(i) (0x324 + ((i) << 4))
+#define USB_TARGET_DRAM 0x0
+
+/*
+ * USB 2.0 Bridge Address Decoding registers setup
+ */
+static void usb_brg_adrdec_setup(void)
+{
+ int i;
+ u32 size, attrib;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+
+ /* Enable DRAM bank */
+ switch (i) {
+ case 0:
+ attrib = KWCPU_ATTR_DRAM_CS0;
+ break;
+ case 1:
+ attrib = KWCPU_ATTR_DRAM_CS1;
+ break;
+ case 2:
+ attrib = KWCPU_ATTR_DRAM_CS2;
+ break;
+ case 3:
+ attrib = KWCPU_ATTR_DRAM_CS3;
+ break;
+ default:
+ /* invalide bank, disable access */
+ attrib = 0;
+ break;
+ }
+
+ size = kw_sdram_bs(i);
+ if ((size) && (attrib))
+ wrl(USB_WINDOW_CTRL(i),
+ KWCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
+ attrib, KWCPU_WIN_ENABLE));
+ else
+ wrl(USB_WINDOW_CTRL(i), KWCPU_WIN_DISABLE);
+
+ wrl(USB_WINDOW_BASE(i), kw_sdram_bar(i));
+ }
+}
+
+/*
+ * Create the appropriate control structures to manage
+ * a new EHCI host controller.
+ */
+int ehci_hcd_init(void)
+{
+ usb_brg_adrdec_setup();
+
+ hccr = (struct ehci_hccr *)(KW_USB20_BASE + 0x100);
+ hcor = (struct ehci_hcor *)((uint32_t) hccr
+ + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+ debug("Kirkwood-ehci: init hccr %x and hcor %x hc_length %d\n",
+ (uint32_t)hccr, (uint32_t)hcor,
+ (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+ return 0;
+}
+
+/*
+ * Destroy the appropriate control structures corresponding
+ * the the EHCI host controller.
+ */
+int ehci_hcd_stop(void)
+{
+ return 0;
+}
+
diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
index b81c5365ec1d72bf5daa52b28c77f77c4df29969..f9da3f0b29b28766c37ee468ba917a52124d466b 100644
--- a/drivers/usb/musb/musb_core.h
+++ b/drivers/usb/musb/musb_core.h
@@ -307,10 +307,4 @@ extern void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt);
extern void write_fifo(u8 ep, u32 length, void *fifo_data);
extern void read_fifo(u8 ep, u32 length, void *fifo_data);
-/* extern functions */
-extern inline void musb_writew(u32 offset, u16 value);
-extern inline void musb_writeb(u32 offset, u8 value);
-extern inline u16 musb_readw(u32 offset);
-extern inline u8 musb_readb(u32 offset);
-
#endif /* __MUSB_HDRC_DEFS_H__ */
diff --git a/drivers/usb/musb/musb_hcd.c b/drivers/usb/musb/musb_hcd.c
index 352a0d4eb084851c8e7a6c65c76f5fc1a762b108..19d978b245a0f82367d9fa2fa2c53085e6a63be7 100644
--- a/drivers/usb/musb/musb_hcd.c
+++ b/drivers/usb/musb/musb_hcd.c
@@ -111,6 +111,7 @@ static int wait_until_ep0_ready(struct usb_device *dev, u32 bit_mask)
{
u16 csr;
int result = 1;
+ int timeout = CONFIG_MUSB_TIMEOUT;
while (result > 0) {
csr = readw(&musbr->txcsr);
@@ -152,7 +153,17 @@ static int wait_until_ep0_ready(struct usb_device *dev, u32 bit_mask)
}
break;
}
+
+ /* Check the timeout */
+ if (--timeout)
+ udelay(1);
+ else {
+ dev->status = USB_ST_CRC_ERR;
+ result = -1;
+ break;
+ }
}
+
return result;
}
@@ -162,6 +173,7 @@ static int wait_until_ep0_ready(struct usb_device *dev, u32 bit_mask)
static u8 wait_until_txep_ready(struct usb_device *dev, u8 ep)
{
u16 csr;
+ int timeout = CONFIG_MUSB_TIMEOUT;
do {
if (check_stall(ep, 1)) {
@@ -174,6 +186,15 @@ static u8 wait_until_txep_ready(struct usb_device *dev, u8 ep)
dev->status = USB_ST_CRC_ERR;
return 0;
}
+
+ /* Check the timeout */
+ if (--timeout)
+ udelay(1);
+ else {
+ dev->status = USB_ST_CRC_ERR;
+ return -1;
+ }
+
} while (csr & MUSB_TXCSR_TXPKTRDY);
return 1;
}
@@ -184,6 +205,7 @@ static u8 wait_until_txep_ready(struct usb_device *dev, u8 ep)
static u8 wait_until_rxep_ready(struct usb_device *dev, u8 ep)
{
u16 csr;
+ int timeout = CONFIG_MUSB_TIMEOUT;
do {
if (check_stall(ep, 0)) {
@@ -196,6 +218,15 @@ static u8 wait_until_rxep_ready(struct usb_device *dev, u8 ep)
dev->status = USB_ST_CRC_ERR;
return 0;
}
+
+ /* Check the timeout */
+ if (--timeout)
+ udelay(1);
+ else {
+ dev->status = USB_ST_CRC_ERR;
+ return -1;
+ }
+
} while (!(csr & MUSB_RXCSR_RXPKTRDY));
return 1;
}
diff --git a/drivers/usb/musb/musb_hcd.h b/drivers/usb/musb/musb_hcd.h
index bb83311b0142c4fdb9a7ade8591574626a5ca6e1..b7f571d03771753895b473c41af8b4cacfe03a60 100644
--- a/drivers/usb/musb/musb_hcd.h
+++ b/drivers/usb/musb/musb_hcd.h
@@ -30,6 +30,10 @@
extern unsigned char new[];
#endif
+#ifndef CONFIG_MUSB_TIMEOUT
+# define CONFIG_MUSB_TIMEOUT 100000
+#endif
+
/* This defines the endpoint number used for control transfers */
#define MUSB_CONTROL_EP 0
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index 114056177c2768eae173cee7f5bcd374f8950fd4..3b99456227303da3dab3925203b0e1c911dcd8e4 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -85,7 +85,7 @@
#define MPC83XX_SCCR_USB_DRCM_01 0x00100000
#define MPC83XX_SCCR_USB_DRCM_10 0x00200000
-#if defined(CONFIG_MPC83XX)
+#if defined(CONFIG_MPC83xx)
#define CONFIG_SYS_MPC8xxx_USB_ADDR CONFIG_SYS_MPC83xx_USB_ADDR
#elif defined(CONFIG_MPC85xx)
#define CONFIG_SYS_MPC8xxx_USB_ADDR CONFIG_SYS_MPC85xx_USB_ADDR