diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig
index 2a3db860bbcfeb7314a395dba61f37ee277d0c4e..cbc3ef71c81723b40839e455325055120bea45e2 100644
--- a/arch/arm/mach-imx/mx7/Kconfig
+++ b/arch/arm/mach-imx/mx7/Kconfig
@@ -55,11 +55,18 @@ config TARGET_COLIBRI_IMX7
select DM_SERIAL
select DM_THERMAL
+config TARGET_NITROGEN7
+ bool "nitrogen7"
+ select CPU_V7
+ select DM
+ select DM_THERMAL
+
endchoice
config SYS_SOC
default "mx7"
+source "board/boundary/nitrogen7/Kconfig"
source "board/compulab/cl-som-imx7/Kconfig"
source "board/freescale/mx7dsabresd/Kconfig"
source "board/technexion/pico-imx7d/Kconfig"
diff --git a/board/boundary/nitrogen7/Kconfig b/board/boundary/nitrogen7/Kconfig
new file mode 100644
index 0000000000000000000000000000000000000000..f0cd1432feb327bc53f86859dc6d0bbdc668e769
--- /dev/null
+++ b/board/boundary/nitrogen7/Kconfig
@@ -0,0 +1,21 @@
+if TARGET_NITROGEN7
+
+config SYS_BOARD
+ default "nitrogen7"
+
+config SYS_VENDOR
+ default "boundary"
+
+config SYS_SOC
+ default "mx7"
+
+config SYS_CONFIG_NAME
+ default "nitrogen7"
+
+config ENV_WLMAC
+ bool
+ default y
+
+source "board/boundary/common/Kconfig"
+
+endif
diff --git a/board/boundary/nitrogen7/MAINTAINERS b/board/boundary/nitrogen7/MAINTAINERS
new file mode 100644
index 0000000000000000000000000000000000000000..201e393d6c94cf57aad94e9ab765a7523bdf1023
--- /dev/null
+++ b/board/boundary/nitrogen7/MAINTAINERS
@@ -0,0 +1,6 @@
+NITROGEN7 BOARD
+M: Troy Kisky <troy.kisky@boundarydevices.com>
+S: Maintained
+F: board/boundary/nitrogen7
+F: include/configs/nitrogen7.h
+F: configs/nitrogen7_defconfig
diff --git a/board/boundary/nitrogen7/Makefile b/board/boundary/nitrogen7/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..72708afc06beb7c13b717e896e2342e4f8a5490c
--- /dev/null
+++ b/board/boundary/nitrogen7/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2015 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := nitrogen7.o
diff --git a/board/boundary/nitrogen7/nitrogen7.c b/board/boundary/nitrogen7/nitrogen7.c
new file mode 100644
index 0000000000000000000000000000000000000000..8a4448f5bc929f6e671dfbd50530a76c1272b654
--- /dev/null
+++ b/board/boundary/nitrogen7/nitrogen7.c
@@ -0,0 +1,484 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx7-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/fbpanel.h>
+#include <asm/io.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+#include "../../freescale/common/pfuze.h"
+#include <i2c.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/crm_regs.h>
+#include <usb.h>
+#include "../common/bd_common.h"
+#include "../common/padctrl.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
+ PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
+ PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
+
+#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
+ PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
+
+#define QSPI_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
+
+#define RGB_PAD_CTRL PAD_CTL_DSE_3P3V_49OHM
+
+#define SETUP_IOMUX_PADS(x) \
+ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
+
+static const iomux_v3_cfg_t init_pads[] = {
+ /* fec */
+#ifdef CONFIG_FEC_MXC
+ /* PHY - AR8035 */
+ IOMUX_PAD_CTRL(GPIO1_IO10__ENET1_MDIO, PAD_CTRL_ENET_MDIO),
+ IOMUX_PAD_CTRL(GPIO1_IO11__ENET1_MDC, PAD_CTRL_ENET_MDC),
+ IOMUX_PAD_CTRL(ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL, PAD_CTRL_ENET_TX),
+ IOMUX_PAD_CTRL(ENET1_RGMII_TD0__ENET1_RGMII_TD0, PAD_CTRL_ENET_TX),
+ IOMUX_PAD_CTRL(ENET1_RGMII_TD1__ENET1_RGMII_TD1, PAD_CTRL_ENET_TX),
+ IOMUX_PAD_CTRL(ENET1_RGMII_TD2__ENET1_RGMII_TD2, PAD_CTRL_ENET_TX),
+ IOMUX_PAD_CTRL(ENET1_RGMII_TD3__ENET1_RGMII_TD3, PAD_CTRL_ENET_TX),
+ IOMUX_PAD_CTRL(ENET1_RGMII_TXC__ENET1_RGMII_TXC, PAD_CTRL_ENET_TX),
+ IOMUX_PAD_CTRL(GPIO1_IO12__CCM_ENET_REF_CLK1, PAD_CTRL_ENET_TX),
+#endif
+#define GP_RGMII_PHY_RESET IMX_GPIO_NR(6, 10)
+ IOMUX_PAD_CTRL(SD3_STROBE__GPIO6_IO10, WEAK_PULLUP),
+#define GPIRQ_ENET_PHY IMX_GPIO_NR(1, 2)
+ IOMUX_PAD_CTRL(GPIO1_IO02__GPIO1_IO2, WEAK_PULLUP),
+
+ /* flexcan2 */
+ IOMUX_PAD_CTRL(GPIO1_IO14__FLEXCAN2_RX, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(GPIO1_IO15__FLEXCAN2_TX, WEAK_PULLUP),
+#define GP_CAN_STANDBY IMX_GPIO_NR(2, 14)
+ IOMUX_PAD_CTRL(EPDC_DATA14__GPIO2_IO14, WEAK_PULLUP),
+
+ /* GPIOs - J2 */
+ IOMUX_PAD_CTRL(SAI1_TX_DATA__GPIO6_IO15, WEAK_PULLUP), /* pin 1 */
+ IOMUX_PAD_CTRL(SAI1_RX_DATA__GPIO6_IO12, WEAK_PULLUP), /* pin 3 */
+ IOMUX_PAD_CTRL(SD1_WP__GPIO5_IO1, WEAK_PULLUP), /* pin 5 */
+ IOMUX_PAD_CTRL(SD1_RESET_B__GPIO5_IO2, WEAK_PULLUP), /* pin 7 */
+ IOMUX_PAD_CTRL(EPDC_DATA07__GPIO2_IO7, WEAK_PULLUP), /* pin 15 */
+ IOMUX_PAD_CTRL(EPDC_DATA08__GPIO2_IO8, WEAK_PULLUP), /* pin 17 */
+ IOMUX_PAD_CTRL(EPDC_DATA09__GPIO2_IO9, WEAK_PULLUP), /* pin 19 */
+ IOMUX_PAD_CTRL(EPDC_DATA10__GPIO2_IO10, WEAK_PULLUP), /* pin 21 */
+ IOMUX_PAD_CTRL(EPDC_DATA11__GPIO2_IO11, WEAK_PULLUP), /* pin 23 */
+ IOMUX_PAD_CTRL(EPDC_DATA12__GPIO2_IO12, WEAK_PULLUP), /* pin 25 */
+ IOMUX_PAD_CTRL(EPDC_DATA13__GPIO2_IO13, WEAK_PULLUP), /* pin 27 */
+ IOMUX_PAD_CTRL(EPDC_GDCLK__GPIO2_IO24, WEAK_PULLUP), /* pin 33 */
+ IOMUX_PAD_CTRL(EPDC_GDOE__GPIO2_IO25, WEAK_PULLUP), /* pin 35 */
+ IOMUX_PAD_CTRL(EPDC_GDRL__GPIO2_IO26, WEAK_PULLUP), /* pin 37 */
+ IOMUX_PAD_CTRL(EPDC_SDCE0__GPIO2_IO20, WEAK_PULLUP), /* pin 39 */
+ IOMUX_PAD_CTRL(EPDC_SDCE1__GPIO2_IO21, WEAK_PULLUP), /* pin 41 */
+ IOMUX_PAD_CTRL(EPDC_SDCE2__GPIO2_IO22, WEAK_PULLUP), /* pin 43 */
+ IOMUX_PAD_CTRL(EPDC_SDCE3__GPIO2_IO23, WEAK_PULLUP), /* pin 45 */
+ IOMUX_PAD_CTRL(EPDC_GDSP__GPIO2_IO27, WEAK_PULLUP), /* pin 47 */
+ IOMUX_PAD_CTRL(EPDC_SDCLK__GPIO2_IO16, WEAK_PULLUP), /* pin 51 */
+ IOMUX_PAD_CTRL(EPDC_SDLE__GPIO2_IO17, WEAK_PULLUP), /* pin 53 */
+ IOMUX_PAD_CTRL(EPDC_SDOE__GPIO2_IO18, WEAK_PULLUP), /* pin 55 */
+ IOMUX_PAD_CTRL(EPDC_PWR_COM__GPIO2_IO30, WEAK_PULLUP), /* pin 57 */
+ IOMUX_PAD_CTRL(EPDC_PWR_STAT__GPIO2_IO31, WEAK_PULLUP), /* pin 59 */
+
+ IOMUX_PAD_CTRL(EPDC_BDR0__GPIO2_IO28, WEAK_PULLUP), /* pin 2 */
+ IOMUX_PAD_CTRL(EPDC_BDR1__GPIO2_IO29, WEAK_PULLUP), /* pin 4 */
+ IOMUX_PAD_CTRL(EPDC_SDSHR__GPIO2_IO19, WEAK_PULLUP), /* pin 6 */
+ IOMUX_PAD_CTRL(SD2_RESET_B__GPIO5_IO11, WEAK_PULLUP), /* pin 10 */
+ IOMUX_PAD_CTRL(SAI1_TX_SYNC__GPIO6_IO14, WEAK_PULLUP), /* pin 26 */
+ IOMUX_PAD_CTRL(SAI1_TX_BCLK__GPIO6_IO13, WEAK_PULLUP), /* pin 28 */
+ IOMUX_PAD_CTRL(SD2_CD_B__GPIO5_IO9, WEAK_PULLUP), /* pin 30 */
+ IOMUX_PAD_CTRL(SAI2_RX_DATA__GPIO6_IO21, WEAK_PULLUP), /* pin 34 */
+ IOMUX_PAD_CTRL(SAI2_TX_DATA__GPIO6_IO22, WEAK_PULLUP), /* pin 38 */
+ IOMUX_PAD_CTRL(SAI2_TX_BCLK__GPIO6_IO20, WEAK_PULLUP), /* pin 40 */
+ IOMUX_PAD_CTRL(SAI2_TX_SYNC__GPIO6_IO19, WEAK_PULLUP), /* pin 42 */
+
+ /* i2c1 - pmic */
+#define GP_PMIC_INT_B IMX_GPIO_NR(4, 22)
+ IOMUX_PAD_CTRL(ECSPI2_MISO__GPIO4_IO22, WEAK_PULLUP),
+
+ /* i2c2 - rv4162 */
+#define GP_RTC IMX_GPIO_NR(2, 15)
+ IOMUX_PAD_CTRL(EPDC_DATA15__GPIO2_IO15, WEAK_PULLUP),
+
+ /* i2c2a */
+#define GP_I2C2A_EN IMX_GPIO_NR(1, 7)
+ IOMUX_PAD_CTRL(GPIO1_IO07__GPIO1_IO7, WEAK_PULLUP),
+#define GP_MIPI IMX_GPIO_NR(1, 6)
+ IOMUX_PAD_CTRL(GPIO1_IO06__GPIO1_IO6, WEAK_PULLUP),
+#define GP_MIPI_BACKLIGHT IMX_GPIO_NR(1, 13)
+ IOMUX_PAD_CTRL(GPIO1_IO13__GPIO1_IO13, WEAK_PULLUP),
+
+ /* i2c3 - J9, J2(gpio connector), J20(rgb connector) */
+#define GP_I2C_TOUCH IMX_GPIO_NR(5, 10)
+// IOMUX_PAD_CTRL(SD2_WP__GPIO5_IO10, WEAK_PULLUP),
+ /* i2c4 - PCIe, WM8960*/
+
+ /* PCIe */
+#define GP_PCIE_DISABLE IMX_GPIO_NR(6, 17)
+ IOMUX_PAD_CTRL(SAI1_RX_BCLK__GPIO6_IO17, WEAK_PULLUP),
+#define GP_PCIE_RESET IMX_GPIO_NR(6, 16)
+ IOMUX_PAD_CTRL(SAI1_RX_SYNC__GPIO6_IO16, WEAK_PULLUP),
+
+ /* PWM1 - rgb */
+#define GP_BACKLIGHT_RGB IMX_GPIO_NR(1, 1)
+ IOMUX_PAD_CTRL(GPIO1_IO01__GPIO1_IO1, WEAK_PULLDN_OUTPUT),
+// IOMUX_PAD_CTRL(GPIO1_IO01__PWM1_OUT, WEAK_PULLDN_OUTPUT),
+
+ /* PWM2 */
+ IOMUX_PAD_CTRL(GPIO1_IO09__PWM2_OUT, WEAK_PULLUP),
+
+ /* QSPIA */
+ IOMUX_PAD_CTRL(EPDC_DATA00__QSPI_A_DATA0, QSPI_PAD_CTRL),
+ IOMUX_PAD_CTRL(EPDC_DATA01__QSPI_A_DATA1, QSPI_PAD_CTRL),
+#if 1
+ IOMUX_PAD_CTRL(EPDC_DATA02__QSPI_A_DATA2, QSPI_PAD_CTRL),
+ IOMUX_PAD_CTRL(EPDC_DATA03__QSPI_A_DATA3, QSPI_PAD_CTRL),
+#else
+#define GP_SPI_nWP IMX_GPIO_NR(2, 2)
+ IOMUX_PAD_CTRL(EPDC_DATA02__GPIO2_IO2, WEAK_PULLUP),
+#define GP_SPI_nHOLD IMX_GPIO_NR(2, 3)
+ IOMUX_PAD_CTRL(EPDC_DATA03__GPIO2_IO3, WEAK_PULLUP),
+#endif
+ IOMUX_PAD_CTRL(EPDC_DATA05__QSPI_A_SCLK, QSPI_PAD_CTRL),
+ IOMUX_PAD_CTRL(EPDC_DATA06__QSPI_A_SS0_B, QSPI_PAD_CTRL),
+
+ /* SAI1 - wm8960 on i2c4 */
+ IOMUX_PAD_CTRL(ENET1_CRS__SAI1_TX_SYNC, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(ENET1_RX_CLK__SAI1_TX_BCLK, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(ENET1_TX_CLK__SAI1_RX_DATA0, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(ENET1_COL__SAI1_TX_DATA0, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(SAI1_MCLK__SAI1_MCLK, WEAK_PULLUP),
+
+ /* uart1 */
+ IOMUX_PAD_CTRL(UART1_TX_DATA__UART1_DCE_TX, UART_PAD_CTRL),
+ IOMUX_PAD_CTRL(UART1_RX_DATA__UART1_DCE_RX, UART_PAD_CTRL),
+
+ /* uart2 */
+ IOMUX_PAD_CTRL(UART2_TX_DATA__UART2_DCE_TX, UART_PAD_CTRL),
+ IOMUX_PAD_CTRL(UART2_RX_DATA__UART2_DCE_RX, UART_PAD_CTRL),
+
+ /* uart3 */
+ IOMUX_PAD_CTRL(UART3_TX_DATA__UART3_DCE_TX, UART_PAD_CTRL),
+ IOMUX_PAD_CTRL(UART3_RX_DATA__UART3_DCE_RX, UART_PAD_CTRL),
+#define GP_UART3_RS485_TX IMX_GPIO_NR(2, 4)
+ IOMUX_PAD_CTRL(EPDC_DATA04__GPIO2_IO4, WEAK_PULLUP),
+
+ /* uart6 - bluetooth */
+ IOMUX_PAD_CTRL(ECSPI1_MOSI__UART6_DCE_TX, UART_PAD_CTRL),
+ IOMUX_PAD_CTRL(ECSPI1_SCLK__UART6_DCE_RX, UART_PAD_CTRL),
+ IOMUX_PAD_CTRL(ECSPI1_MISO__UART6_DCE_RTS, UART_PAD_CTRL),
+ IOMUX_PAD_CTRL(ECSPI1_SS0__UART6_DCE_CTS, UART_PAD_CTRL),
+
+#ifdef CONFIG_USB_EHCI_MX7
+ /* usbotg1 */
+ IOMUX_PAD_CTRL(GPIO1_IO04__USB_OTG1_OC, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(GPIO1_IO05__USB_OTG1_PWR, WEAK_PULLUP),
+// IOMUX_PAD_CTRL(SD2_WP__USB_OTG1_ID, WEAK_PULLUP),
+#define GP_OTG1_ID IMX_GPIO_NR(5, 10)
+ IOMUX_PAD_CTRL(SD2_WP__GPIO5_IO10, WEAK_PULLUP),
+
+ /* usbotg2 */
+ IOMUX_PAD_CTRL(UART3_RTS_B__USB_OTG2_OC, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(UART3_CTS_B__USB_OTG2_PWR, WEAK_PULLUP),
+#endif
+
+ /* usdhc1 */
+ IOMUX_PAD_CTRL(SD1_CLK__SD1_CLK, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD1_CMD__SD1_CMD, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD1_DATA0__SD1_DATA0, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD1_DATA1__SD1_DATA1, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD1_DATA2__SD1_DATA2, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD1_DATA3__SD1_DATA3, USDHC_PAD_CTRL),
+#define GP_USDHC1_CD IMX_GPIO_NR(5, 0)
+ IOMUX_PAD_CTRL(SD1_CD_B__GPIO5_IO0, USDHC_PAD_CTRL),
+#define GP_PMIC_SD1_VSEL IMX_GPIO_NR(1, 8)
+ IOMUX_PAD_CTRL(GPIO1_IO08__SD1_VSELECT, WEAK_PULLUP),
+
+ /* usdhc2 - murata wifi */
+ IOMUX_PAD_CTRL(SD2_CLK__SD2_CLK, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD2_CMD__SD2_CMD, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD2_DATA0__SD2_DATA0, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD2_DATA1__SD2_DATA1, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD2_DATA2__SD2_DATA2, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD2_DATA3__SD2_DATA3, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(GPIO1_IO03__CCM_CLKO2, WEAK_PULLUP), /* Slow clock */
+#define GP_BT_REG_ON IMX_GPIO_NR(4, 23)
+ IOMUX_PAD_CTRL(ECSPI2_SS0__GPIO4_IO23, WEAK_PULLUP),
+#define GP_WL_HOST_WAKE IMX_GPIO_NR(4, 20)
+ IOMUX_PAD_CTRL(ECSPI2_SCLK__GPIO4_IO20, WEAK_PULLUP),
+#define GP_WL_REG_ON IMX_GPIO_NR(4, 21)
+ IOMUX_PAD_CTRL(ECSPI2_MOSI__GPIO4_IO21, WEAK_PULLUP),
+
+ /* usdhc3 - emmc */
+ IOMUX_PAD_CTRL(SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DATA0__SD3_DATA0, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DATA1__SD3_DATA1, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DATA2__SD3_DATA2, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DATA3__SD3_DATA3, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DATA4__SD3_DATA4, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DATA5__SD3_DATA5, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DATA6__SD3_DATA6, USDHC_PAD_CTRL),
+ IOMUX_PAD_CTRL(SD3_DATA7__SD3_DATA7, USDHC_PAD_CTRL),
+#define GP_EMMC_RESET IMX_GPIO_NR(6, 11)
+ IOMUX_PAD_CTRL(SD3_RESET_B__GPIO6_IO11, USDHC_PAD_CTRL),
+
+ /* watchdog */
+ IOMUX_PAD_CTRL(GPIO1_IO00__WDOG1_WDOG_B, WEAK_PULLUP_OUTPUT),
+};
+
+static const iomux_v3_cfg_t rgb_pads[] = {
+ IOMUX_PAD_CTRL(LCD_CLK__LCD_CLK, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(LCD_ENABLE__LCD_ENABLE, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(LCD_HSYNC__LCD_HSYNC, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(LCD_VSYNC__LCD_VSYNC, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(LCD_RESET__LCD_RESET, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(LCD_DATA00__LCD_DATA0, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(LCD_DATA01__LCD_DATA1, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(LCD_DATA02__LCD_DATA2, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(LCD_DATA03__LCD_DATA3, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(LCD_DATA04__LCD_DATA4, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(LCD_DATA05__LCD_DATA5, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(LCD_DATA06__LCD_DATA6, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(LCD_DATA07__LCD_DATA7, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(LCD_DATA08__LCD_DATA8, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(LCD_DATA09__LCD_DATA9, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(LCD_DATA10__LCD_DATA10, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(LCD_DATA11__LCD_DATA11, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(LCD_DATA12__LCD_DATA12, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(LCD_DATA13__LCD_DATA13, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(LCD_DATA14__LCD_DATA14, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(LCD_DATA15__LCD_DATA15, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(LCD_DATA16__LCD_DATA16, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(LCD_DATA17__LCD_DATA17, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(LCD_DATA18__LCD_DATA18, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(LCD_DATA19__LCD_DATA19, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(LCD_DATA20__LCD_DATA20, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(LCD_DATA21__LCD_DATA21, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(LCD_DATA22__LCD_DATA22, RGB_PAD_CTRL),
+ IOMUX_PAD_CTRL(LCD_DATA23__LCD_DATA23, RGB_PAD_CTRL),
+};
+
+static const iomux_v3_cfg_t rgb_gpio_pads[] = {
+ IOMUX_PAD_CTRL(LCD_CLK__GPIO3_IO0, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(LCD_ENABLE__GPIO3_IO1, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(LCD_HSYNC__GPIO3_IO2, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(LCD_VSYNC__GPIO3_IO3, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(LCD_RESET__GPIO3_IO4, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(LCD_DATA00__GPIO3_IO5, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(LCD_DATA01__GPIO3_IO6, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(LCD_DATA02__GPIO3_IO7, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(LCD_DATA03__GPIO3_IO8, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(LCD_DATA04__GPIO3_IO9, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(LCD_DATA05__GPIO3_IO10, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(LCD_DATA06__GPIO3_IO11, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(LCD_DATA07__GPIO3_IO12, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(LCD_DATA08__GPIO3_IO13, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(LCD_DATA09__GPIO3_IO14, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(LCD_DATA10__GPIO3_IO15, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(LCD_DATA11__GPIO3_IO16, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(LCD_DATA12__GPIO3_IO17, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(LCD_DATA13__GPIO3_IO18, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(LCD_DATA14__GPIO3_IO19, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(LCD_DATA15__GPIO3_IO20, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(LCD_DATA16__GPIO3_IO21, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(LCD_DATA17__GPIO3_IO22, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(LCD_DATA18__GPIO3_IO23, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(LCD_DATA19__GPIO3_IO24, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(LCD_DATA20__GPIO3_IO25, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(LCD_DATA21__GPIO3_IO26, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(LCD_DATA22__GPIO3_IO27, WEAK_PULLUP),
+ IOMUX_PAD_CTRL(LCD_DATA23__GPIO3_IO28, WEAK_PULLUP),
+};
+
+#ifdef CONFIG_SYS_I2C_MXC
+/* I2C1 for PMIC */
+static const struct i2c_pads_info i2c_pads[] = {
+ I2C_PADS_INFO_ENTRY(I2C1, I2C1_SCL, 4, 8, I2C1_SDA, 4, 9, I2C_PAD_CTRL),
+ I2C_PADS_INFO_ENTRY(I2C2, I2C2_SCL, 4, 10, I2C2_SDA, 4, 11, I2C_PAD_CTRL),
+ I2C_PADS_INFO_ENTRY(I2C3, I2C3_SCL, 4, 12, I2C3_SDA, 4, 13, I2C_PAD_CTRL),
+ I2C_PADS_INFO_ENTRY(I2C4, I2C4_SCL, 4, 14, I2C4_SDA, 4, 15, I2C_PAD_CTRL),
+};
+#define I2C_BUS_CNT 4
+#else
+#define i2c_pads NULL
+#define I2C_BUS_CNT 0
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg board_usdhc_cfg[] = {
+ {.esdhc_base = USDHC1_BASE_ADDR, .bus_width = 4,
+ .gp_cd = GP_USDHC1_CD},
+ {.esdhc_base = USDHC3_BASE_ADDR, .bus_width = 8,
+ .gp_reset = GP_EMMC_RESET},
+};
+#endif
+
+#ifdef CONFIG_CMD_FBPANEL
+void board_enable_lcd(const struct display_info_t *di, int enable)
+{
+ if (enable)
+ SETUP_IOMUX_PADS(rgb_pads);
+ else
+ SETUP_IOMUX_PADS(rgb_gpio_pads);
+ gpio_direction_output(GP_BACKLIGHT_RGB, enable);
+}
+
+static const struct display_info_t displays[] = {
+ /* fusion7 specific touchscreen */
+ VD_FUSION7(LCD, fbp_detect_i2c, 2, 0x10),
+
+ /* tsc2004 */
+ VD_CLAA_WVGA(LCD, fbp_detect_i2c, 2, 0x48),
+ VD_SHARP_WVGA(LCD, NULL, 2, 0x48),
+ VD_DC050WX(LCD, NULL, 2, 0x48),
+ VD_QVGA(LCD, NULL, 2, 0x48),
+ VD_AT035GT_07ET3(LCD, NULL, 2, 0x48),
+
+ VD_LSA40AT9001(LCD, NULL, 0, 0x00),
+};
+#define display_cnt ARRAY_SIZE(displays)
+#else
+#define displays NULL
+#define display_cnt 0
+#endif
+
+static const unsigned short gpios_out_low[] = {
+ GP_RGMII_PHY_RESET,
+ GP_I2C2A_EN,
+ GP_MIPI_BACKLIGHT,
+ GP_PCIE_DISABLE,
+ GP_PCIE_RESET,
+ GP_BACKLIGHT_RGB,
+ GP_UART3_RS485_TX,
+ GP_PMIC_SD1_VSEL,
+ GP_BT_REG_ON,
+ GP_WL_REG_ON,
+ GP_EMMC_RESET,
+};
+
+static const unsigned short gpios_out_high[] = {
+ GP_CAN_STANDBY,
+#ifdef GP_SPI_nWP
+ GP_SPI_nWP,
+#endif
+#ifdef GP_SPI_nHOLD
+ GP_SPI_nHOLD,
+#endif
+};
+
+static const unsigned short gpios_in[] = {
+ GPIRQ_ENET_PHY,
+ GP_PMIC_INT_B,
+ GP_RTC,
+ GP_MIPI,
+ GP_I2C_TOUCH,
+ GP_USDHC1_CD,
+ GP_WL_HOST_WAKE,
+ GP_OTG1_ID,
+};
+
+int board_early_init_f(void)
+{
+ set_gpios_in(gpios_in, ARRAY_SIZE(gpios_in));
+ set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
+ set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
+ SETUP_IOMUX_PADS(init_pads);
+ SETUP_IOMUX_PADS(rgb_gpio_pads);
+ return 0;
+}
+
+int board_init(void)
+{
+ common_board_init(i2c_pads, I2C_BUS_CNT, 0,
+ displays, display_cnt, 0);
+ return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
+ {"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)},
+ {NULL, 0},
+};
+#endif
+
+#ifdef CONFIG_POWER
+#define I2C_PMIC 0
+int power_init_board(void)
+{
+ struct pmic *p;
+ int ret;
+ unsigned int reg, rev_id;
+
+ ret = power_pfuze3000_init(I2C_PMIC);
+ if (ret)
+ return ret;
+
+ p = pmic_get("PFUZE3000");
+ ret = pmic_probe(p);
+ if (ret)
+ return ret;
+
+ pmic_reg_read(p, PFUZE3000_DEVICEID, ®);
+ pmic_reg_read(p, PFUZE3000_REVID, &rev_id);
+ printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id);
+
+ /* disable Low Power Mode during standby mode */
+ pmic_reg_read(p, PFUZE3000_LDOGCTL, ®);
+ reg |= 0x1;
+ pmic_reg_write(p, PFUZE3000_LDOGCTL, reg);
+
+ return 0;
+}
+#endif
+
+u32 get_board_rev(void)
+{
+ return get_cpu_rev();
+}
+
+const struct button_key board_buttons[] = {
+ {NULL, 0, 0, 0},
+};
+
+#ifdef CONFIG_USB_EHCI_MX7
+int board_usb_phy_mode(int port)
+{
+ if (port)
+ return USB_INIT_HOST;
+ return gpio_get_value(GP_OTG1_ID) ? USB_INIT_DEVICE : USB_INIT_HOST;
+}
+
+int board_ehci_hcd_init(int port)
+{
+ switch (port) {
+ case 0:
+ break;
+ case 1:
+ break;
+ default:
+ printf("MXC USB port %d not yet supported\n", port);
+ return -EINVAL;
+ }
+ return 0;
+}
+#endif
diff --git a/board/boundary/nitrogen7/nitrogen7.cfg b/board/boundary/nitrogen7/nitrogen7.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..0abb4a8ee11e402dda9e0d5b76f9113177d0c19f
--- /dev/null
+++ b/board/boundary/nitrogen7/nitrogen7.cfg
@@ -0,0 +1,106 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* H5TC4G63CFR-PBA */
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : sd
+ */
+#ifdef CONFIG_LINK_QSPI
+BOOT_FROM qspi
+#else
+BOOT_FROM sd
+#endif
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+DATA 4 0x30340004 0x4F400005 /* IOMUXC_GPR_GPR1 - enable ocram EPDC function */
+
+DATA 4 0x30391000 0x00000002 /* SRC_DDRC_RCR - assert ddr phy reset */
+DATA 4 0x307a0000 0x01040001 /* DDRC_MSTR - DDR3, burst 8, rank 1 */
+DATA 4 0x307a01a0 0x80400003 /* DDRC_DFIUPD0 - disable auto req */
+DATA 4 0x307a01a4 0x00100020 /* DDRC_DFIUPD1 - min/max delay line recalibration */
+DATA 4 0x307a01a8 0x80100004 /* DDRC_DFIUPD2 - req controls */
+DATA 4 0x307a0064 0x00400046 /* DDRC_RFSHTMG - */
+DATA 4 0x307a0490 0x00000001 /* DDRC_MP_PCTRL_0 - port enable */
+DATA 4 0x307a00d0 0x00020083 /* DDRC_INIT0 - wait 2 clocks after cke high */
+DATA 4 0x307a00d4 0x00690000 /* DDRC_INIT1 - reset width */
+DATA 4 0x307a00dc 0x09300004 /* DDRC_INIT3 - MR0/MR1 reg values */
+DATA 4 0x307a00e0 0x04080000 /* DDRC_INIT4 - MR2/MR3 reg values */
+DATA 4 0x307a00e4 0x00100004 /* DDRC_INIT5 - ZQ cal clks(512)*/
+DATA 4 0x307a00f4 0x0000033f /* DDRC_RANKCTL - */
+DATA 4 0x307a0100 0x09081109 /* DDRC_DRAMTMG0 - RAS */
+DATA 4 0x307a0104 0x0007020d /* DDRC_DRAMTMG1 - tRC */
+DATA 4 0x307a0108 0x03040407 /* DDRC_DRAMTMG2 - WL/RL */
+DATA 4 0x307a010c 0x00002006 /* DDRC_DRAMTMG3 - tMRD */
+DATA 4 0x307a0110 0x04020205 /* DDRC_DRAMTMG4 - tRCD, tRRD, tRP */
+DATA 4 0x307a0114 0x03030202 /* DDRC_DRAMTMG5 - tCKE */
+DATA 4 0x307a0120 0x00000803 /* DDRC_DRAMTMG8 - tXS */
+DATA 4 0x307a0180 0x00800020 /* DDRC_ZQCTL0 - 32 NOP clks after short calibration */
+DATA 4 0x307a0184 0x02000100 /* DDRC_ZQCTL1 - short calibration interval */
+DATA 4 0x307a0190 0x02098204 /* DDRC_DFITMG0 - */
+DATA 4 0x307a0194 0x00030303 /* DDRC_DFITMG1 - */
+DATA 4 0x307a0200 0x00000016 /* DDRC_ADDRMAP0 - bit(A28=22+6) used for rank */
+DATA 4 0x307a0204 0x00171717 /* DDRC_ADDRMAP1 - bit(A25,A26,A27) for bank*/
+DATA 4 0x307a0214 0x04040404 /* DDRC_ADDRMAP5 - bit(A10) for row bit 0, bit(A21) for row bit 11 */
+DATA 4 0x307a0218 0x0f040404 /* DDRC_ADDRMAP6 - bit(A22) for row bit 12, A24 for row bit 14 */
+DATA 4 0x307a0240 0x06000604 /* DDRC_ODTCFG - odt clocks */
+DATA 4 0x307a0244 0x00000001 /* DDRC_ODTMAP - enable rank 0 */
+DATA 4 0x30391000 0x00000000 /* SRC_DDRC_RCR - release ddr phy reset */
+
+DATA 4 0x30790000 0x17420f40 /* DDR_PHY_PHY_CON0 */
+DATA 4 0x30790004 0x10210100 /* DDR_PHY_PHY_CON1 */
+DATA 4 0x30790010 0x00060807 /* DDR_PHY_PHY_CON4 - BL8, tRL */
+DATA 4 0x307900b0 0x1010007e /* DDR_PHY_MDLL_CON0 */
+DATA 4 0x3079009c 0x00000d6e /* DDR_PHY_DRVDS_CON0 - drive strength, CA/RAS/CAS/WEN/ODT/RESET/BANK */
+
+DATA 4 0x30790020 0x08080808 /* DDR_PHY_OFFSET_RD_CON0, read DQS calibration */
+DATA 4 0x30790030 0x08080808 /* DDR_PHY_OFFSET_WR_CON0, write DQS calibration */
+DATA 4 0x30790050 0x01000010 /* DDR_PHY_CMD_SDLL_CON0, resync */
+DATA 4 0x30790050 0x00000010 /* DDR_PHY_CMD_SDLL_CON0 */
+
+DATA 4 0x307900c0 0x0e407304 /* DDR_PHY_ZQ_CON0, */
+DATA 4 0x307900c0 0x0e447304 /* DDR_PHY_ZQ_CON0, zq_clk_div_en */
+DATA 4 0x307900c0 0x0e447306 /* DDR_PHY_ZQ_CON0, start calibration */
+
+CHECK_BITS_SET 4 0x307900c4 0x1 /* DDR_PHY_ZQ_CON1, zq calibration done */
+
+DATA 4 0x307900c0 0x0e447304 /* DDR_PHY_ZQ_CON0, zq_clk_div_en*/
+DATA 4 0x307900c0 0x0e407304 /* DDR_PHY_ZQ_CON0 */
+
+DATA 4 0x30384130 0x00000000 /* CCM_CCGR19 - turn off clocks */
+DATA 4 0x30340020 0x00000178 /* IOMUXC_GPR_GPR8 - start DDR PHY */
+DATA 4 0x30384130 0x00000002 /* CCM_CCGR19 - turn on clock */
+DATA 4 0x30790018 0x0000000f /* DDR_PHY_RODT_CON0 */
+
+CHECK_BITS_SET 4 0x307a0004 0x1 /* DDRC_STAT - wait for normal mode */
+
+DATA 4 0x88780000 0x12345678
+CHECK_BITS_SET 4 0x88780000 0x8
diff --git a/board/boundary/nitrogen7/qspi-mx25l6405d b/board/boundary/nitrogen7/qspi-mx25l6405d
new file mode 100644
index 0000000000000000000000000000000000000000..94e773e6b9a0d7bbe2e926a745db3aa194eaab18
--- /dev/null
+++ b/board/boundary/nitrogen7/qspi-mx25l6405d
@@ -0,0 +1,128 @@
+0 /* 0 dqs_loopback=0 or 1*/ /* The binary file can be built using "./qspi_param.awk qspi-MX25L6405D | xxd -r >qspi-MX25L6405D.nitrogen7" */
+0 /* 4 hold_delay=0 to 3*/
+0 /* 8 reserved */
+0 /* c reserved */
+0 /*10 device_quad_mode_en=1 to enable sending command to SPI device*/
+0 /*14 device_cmd=command to device for enabling Quad I/O mode*/
+03000001 /*18 write_cmd_ipcr=hex value to be written to IPCR register for write cmd of device*/
+02000000 /*1c write_enable_ipcr=hex value to be written to IPCR register for write enable of device*/
+3 /*20 cs_hold_time=0 to 0xF*/
+3 /*24 cs_setup_time=0 to 0xF*/
+8000000 /*28 sflash_A1_size=size in byte(hex)*/
+0 /*2c sflash_A2_size=size in byte(hex)*/
+0 /*30 sflash_B1_size=size in byte(hex)*/
+0 /*34 sflash_B2_size=size in byte(hex)*/
+5 /*38 sclk_freq=0 to 6, 0:18Mhz, 1:49Mhz, 2:55Mhz, 3:60Mhz, 4:66Mhz, 5:76MHz, 6:99Mhz, max 80 MHz*/
+0 /*3c busy_bit_offset=bit position of device BUSY in device status register*/
+1 /*40 sflash_type=1 (Single), 2 (Dual), 4 (Quad mode of operation)*/
+0 /*44 sflash_port=0 or 1 (Port B used)*/
+0 /*48 ddr_mode_enable=0 or 1*/
+0 /*4c dqs_enable=0 or 1*/
+0 /*50 parallel_mode_enable=0 or 1*/
+0 /*54 portA_cs1=0 or 1*/
+0 /*58 portB_cs1=0 or 1*/
+0 /*5c fsphs=0 (Full Speed Phase sampling at non-inverted clock) or 1 (sampling at inverted clock)*/
+0 /*60 fsdly=0 (Full Speed Delay One clk delay) or 1 (two clk cycle delay)*/
+0 /*64 ddrsmp=0 to 7 (sampling point for incoming data in DDR mode)*/
+0818040b /*68 lut[0] QSPI_CMD_FAST_READ */
+1c040c08 /*6c lut[1] */
+2400 /*70 lut[2] */
+0 /*74 lut[3] */
+1c010405 /*78 lut[4] QSPI_CMD_RDSR(Read status register 1) */
+2400 /*7c lut[5] */
+0 /*80 lut[6] */
+0 /*84 lut[7] */
+24000406 /*88 lut[8] QSPI_CMD_WREN(write enable) */
+0 /*8c lut[9] */
+0 /*90 lut[10] */
+0 /*94 lut[11] */
+20010401 /*98 lut[12] QSPI_CMD_WRITE_STATUS(Write status register 1) */
+2400 /*9c lut[13] */
+0 /*a0 lut[14] */
+0 /*a4 lut[15] */
+0 /*a8 lut[16] */
+0 /*ac lut[17] */
+0 /*b0 lut[18] */
+0 /*b4 lut[19] */
+0 /*b8 lut[20] */
+0 /*bc lut[21] */
+0 /*c0 lut[22] */
+0 /*c4 lut[23] */
+0 /*c8 lut[24] */
+0 /*cc lut[25] */
+0 /*d0 lut[26] */
+0 /*d4 lut[27] */
+0 /*d8 lut[28] */
+0 /*dc lut[29] */
+0 /*e0 lut[30] */
+0 /*e4 lut[31] */
+0 /*e8 lut[32] */
+0 /*ec lut[33] */
+0 /*f0 lut[34] */
+0 /*f4 lut[35] */
+0 /*f8 lut[36] */
+0 /*fc lut[37] */
+0 /*100 lut[38] */
+0 /*104 lut[39] */
+0 /*108 lut[40] */
+0 /*10c lut[41] */
+0 /*110 lut[42] */
+0 /*114 lut[43] */
+0 /*118 lut[44] */
+0 /*11c lut[45] */
+0 /*120 lut[46] */
+0 /*124 lut[47] */
+0 /*128 lut[48] */
+0 /*12c lut[49] */
+0 /*130 lut[50] */
+0 /*134 lut[51] */
+0 /*138 lut[52] */
+0 /*13c lut[53] */
+0 /*140 lut[54] */
+0 /*144 lut[55] */
+0 /*148 lut[56] */
+0 /*14c lut[57] */
+0 /*150 lut[58] */
+0 /*154 lut[59] */
+0 /*158 lut[60] */
+0 /*15c lut[61] */
+0 /*160 lut[62] */
+0 /*164 lut[63] */
+1000001 /*168 read_status_ipcr=hex value to be written to IPCR register for reading status reg of device */
+0 /*16c enable_dqs_phase=0 or 1 */
+0 /*170 Not used */
+0 /*174 */
+0 /*178 */
+0 /*17c */
+0 /*180 */
+0 /*184 */
+0 /*188 */
+0 /*18c */
+0 /*190 */
+0 /*194 DQS pin pad setting override */
+0 /*198 SCLK pin pad setting override */
+0 /*19c DATA pins pad setting override */
+0 /*1a0 CS pins pad setting override */
+0 /*1a4 0: dqs loopback from pad/1: dqs loopback internally */
+0 /*1a8 dqs phase selection */
+0 /*1ac dqs fa delay chain selection */
+0 /*1b0 dqs fb delay chain selection */
+0 /*1b4 sclk fa delay chain selection */
+0 /*1b8 sclk fb delay chain selection */
+0 /*1bc */
+0 /*1c0 reserve[0] */
+0 /*1c4 reserve[1] */
+0 /*1c8 reserve[2] */
+0 /*1cc reserve[3] */
+0 /*1d0 reserve[4] */
+0 /*1d4 reserve[5] */
+0 /*1d8 reserve[6] */
+0 /*1dc reserve[7] */
+0 /*1e0 reserve[8] */
+0 /*1e4 reserve[9] */
+0 /*1e8 reserve[10] */
+0 /*1ec reserve[11] */
+0 /*1f0 reserve[12] */
+0 /*1f4 reserve[13] */
+0 /*1f8 reserve[14] */
+c0ffee01 /*1fc tag, QSPI configuration tag, should be 0xc0ffee01 */
diff --git a/board/boundary/nitrogen7/qspi-sst25vf016b b/board/boundary/nitrogen7/qspi-sst25vf016b
new file mode 100644
index 0000000000000000000000000000000000000000..eacc1fb8577a1cd5edc2775b8d4441a751ef6fc1
--- /dev/null
+++ b/board/boundary/nitrogen7/qspi-sst25vf016b
@@ -0,0 +1,128 @@
+0 /* 0 dqs_loopback=0 or 1*/ /* The binary file can be built using "./qspi_param.awk qspi-SST25VF016B | xxd -r >qspi-SST25VF016B.nitrogen7" */
+0 /* 4 hold_delay=0 to 3*/
+0 /* 8 reserved */
+0 /* c reserved */
+0 /*10 device_quad_mode_en=1 to enable sending command to SPI device*/
+0 /*14 device_cmd=command to device for enabling Quad I/O mode*/
+03000002 /*18 write_cmd_ipcr=hex value to be written to IPCR register for write cmd of device*/
+02000000 /*1c write_enable_ipcr=hex value to be written to IPCR register for write enable of device*/
+3 /*20 cs_hold_time=0 to 0xF*/
+3 /*24 cs_setup_time=0 to 0xF*/
+1000000 /*28 sflash_A1_size=size in byte(hex)*/
+0 /*2c sflash_A2_size=size in byte(hex)*/
+0 /*30 sflash_B1_size=size in byte(hex)*/
+0 /*34 sflash_B2_size=size in byte(hex)*/
+5 /*38 sclk_freq=0 to 6, 0:18Mhz, 1:49Mhz, 2:55Mhz, 3:60Mhz, 4:66Mhz, 5:76MHz, 6:99Mhz, max 80 MHz*/
+0 /*3c busy_bit_offset=bit position of device BUSY in device status register*/
+1 /*40 sflash_type=1 (Single), 2 (Dual), 4 (Quad mode of operation)*/
+0 /*44 sflash_port=0 or 1 (Port B used)*/
+0 /*48 ddr_mode_enable=0 or 1*/
+0 /*4c dqs_enable=0 or 1*/
+0 /*50 parallel_mode_enable=0 or 1*/
+0 /*54 portA_cs1=0 or 1*/
+0 /*58 portB_cs1=0 or 1*/
+0 /*5c fsphs=0 (Full Speed Phase sampling at non-inverted clock) or 1 (sampling at inverted clock)*/
+0 /*60 fsdly=0 (Full Speed Delay One clk delay) or 1 (two clk cycle delay)*/
+0 /*64 ddrsmp=0 to 7 (sampling point for incoming data in DDR mode)*/
+0818040b /*68 lut[0] QSPI_CMD_FAST_READ */
+1c040c08 /*6c lut[1] */
+2400 /*70 lut[2] */
+0 /*74 lut[3] */
+1c010405 /*78 lut[4] QSPI_CMD_RDSR(Read status register 1) */
+2400 /*7c lut[5] */
+0 /*80 lut[6] */
+0 /*84 lut[7] */
+24000406 /*88 lut[8] QSPI_CMD_WREN(write enable) */
+0 /*8c lut[9] */
+0 /*90 lut[10] */
+0 /*94 lut[11] */
+20010401 /*98 lut[12] QSPI_CMD_WRITE_STATUS(Write status register 1) */
+2400 /*9c lut[13] */
+0 /*a0 lut[14] */
+0 /*a4 lut[15] */
+0 /*a8 lut[16] */
+0 /*ac lut[17] */
+0 /*b0 lut[18] */
+0 /*b4 lut[19] */
+0 /*b8 lut[20] */
+0 /*bc lut[21] */
+0 /*c0 lut[22] */
+0 /*c4 lut[23] */
+0 /*c8 lut[24] */
+0 /*cc lut[25] */
+0 /*d0 lut[26] */
+0 /*d4 lut[27] */
+0 /*d8 lut[28] */
+0 /*dc lut[29] */
+0 /*e0 lut[30] */
+0 /*e4 lut[31] */
+0 /*e8 lut[32] */
+0 /*ec lut[33] */
+0 /*f0 lut[34] */
+0 /*f4 lut[35] */
+0 /*f8 lut[36] */
+0 /*fc lut[37] */
+0 /*100 lut[38] */
+0 /*104 lut[39] */
+0 /*108 lut[40] */
+0 /*10c lut[41] */
+0 /*110 lut[42] */
+0 /*114 lut[43] */
+0 /*118 lut[44] */
+0 /*11c lut[45] */
+0 /*120 lut[46] */
+0 /*124 lut[47] */
+0 /*128 lut[48] */
+0 /*12c lut[49] */
+0 /*130 lut[50] */
+0 /*134 lut[51] */
+0 /*138 lut[52] */
+0 /*13c lut[53] */
+0 /*140 lut[54] */
+0 /*144 lut[55] */
+0 /*148 lut[56] */
+0 /*14c lut[57] */
+0 /*150 lut[58] */
+0 /*154 lut[59] */
+0 /*158 lut[60] */
+0 /*15c lut[61] */
+0 /*160 lut[62] */
+0 /*164 lut[63] */
+1000001 /*168 read_status_ipcr=hex value to be written to IPCR register for reading status reg of device */
+0 /*16c enable_dqs_phase=0 or 1 */
+0 /*170 Not used */
+0 /*174 */
+0 /*178 */
+0 /*17c */
+0 /*180 */
+0 /*184 */
+0 /*188 */
+0 /*18c */
+0 /*190 */
+0 /*194 DQS pin pad setting override */
+0 /*198 SCLK pin pad setting override */
+0 /*19c DATA pins pad setting override */
+0 /*1a0 CS pins pad setting override */
+0 /*1a4 0: dqs loopback from pad/1: dqs loopback internally */
+0 /*1a8 dqs phase selection */
+0 /*1ac dqs fa delay chain selection */
+0 /*1b0 dqs fb delay chain selection */
+0 /*1b4 sclk fa delay chain selection */
+0 /*1b8 sclk fb delay chain selection */
+0 /*1bc */
+0 /*1c0 reserve[0] */
+0 /*1c4 reserve[1] */
+0 /*1c8 reserve[2] */
+0 /*1cc reserve[3] */
+0 /*1d0 reserve[4] */
+0 /*1d4 reserve[5] */
+0 /*1d8 reserve[6] */
+0 /*1dc reserve[7] */
+0 /*1e0 reserve[8] */
+0 /*1e4 reserve[9] */
+0 /*1e8 reserve[10] */
+0 /*1ec reserve[11] */
+0 /*1f0 reserve[12] */
+0 /*1f4 reserve[13] */
+0 /*1f8 reserve[14] */
+c0ffee01 /*1fc tag, QSPI configuration tag, should be 0xc0ffee01 */
diff --git a/board/boundary/nitrogen7/qspi-w25q128bv b/board/boundary/nitrogen7/qspi-w25q128bv
new file mode 100644
index 0000000000000000000000000000000000000000..4e77b028e968c3c40d450f37f847d460fb73e52e
--- /dev/null
+++ b/board/boundary/nitrogen7/qspi-w25q128bv
@@ -0,0 +1,128 @@
+0 /* 0 dqs_loopback=0 or 1*/ /* The binary file can be built using "./qspi_param.awk qspi-W25Q128BV | xxd -r >qspi-W25Q128BV.nitrogen7" */
+0 /* 4 hold_delay=0 to 3*/
+0 /* 8 reserved */
+0 /* c reserved */
+1 /*10 device_quad_mode_en=1 to enable sending command to SPI device*/
+0200 /*14 device_cmd=command to device for enabling Quad I/O mode(status reg1 & 2 write) */
+03000002 /*18 write_cmd_ipcr=hex value to be written to IPCR register for write cmd of device*/
+02000000 /*1c write_enable_ipcr=hex value to be written to IPCR register for write enable of device*/
+3 /*20 cs_hold_time=0 to 0xF*/
+3 /*24 cs_setup_time=0 to 0xF*/
+1000000 /*28 sflash_A1_size=size in byte(hex)*/
+0 /*2c sflash_A2_size=size in byte(hex)*/
+0 /*30 sflash_B1_size=size in byte(hex)*/
+0 /*34 sflash_B2_size=size in byte(hex)*/
+6 /*38 sclk_freq=0 to 6*/
+0 /*3c busy_bit_offset=bit position of device BUSY in device status register*/
+4 /*40 sflash_type=1 (Single), 2 (Dual), 4 (Quad mode of operation)*/
+0 /*44 sflash_port=0 or 1 (Port B used)*/
+0 /*48 ddr_mode_enable=0 or 1*/
+0 /*4c dqs_enable=0 or 1*/
+0 /*50 parallel_mode_enable=0 or 1*/
+0 /*54 portA_cs1=0 or 1*/
+0 /*58 portB_cs1=0 or 1*/
+0 /*5c fsphs=0 (Full Speed Phase sampling at non-inverted clock) or 1 (sampling at inverted clock)*/
+0 /*60 fsdly=0 (Full Speed Delay One clk delay) or 1 (two clk cycle delay)*/
+0 /*64 ddrsmp=0 to 7 (sampling point for incoming data in DDR mode)*/
+0a1804eb /*68 lut[0] Fast Read Quad I/O, needs status reg write to enable cmd */
+0e041200 /*6c lut[1] */
+24001e04 /*70 lut[2] */
+0 /*74 lut[3] */
+1c010405 /*78 lut[4] QSPI_CMD_RDSR(Read status register 1) */
+2400 /*7c lut[5] */
+0 /*80 lut[6] */
+0 /*84 lut[7] */
+24000406 /*88 lut[8] QSPI_CMD_WREN(write enable) */
+0 /*8c lut[9] */
+0 /*90 lut[10] */
+0 /*94 lut[11] */
+20010401 /*98 lut[12] QSPI_CMD_WRITE_STATUS(Write status register 1) */
+2400 /*9c lut[13] */
+0 /*a0 lut[14] */
+0 /*a4 lut[15] */
+1c010435 /*a8 lut[16] QSPI_CMD_RDSR2(Read status register 2) */
+2400 /*ac lut[17] */
+0 /*b0 lut[18] */
+0 /*b4 lut[19] */
+0 /*b8 lut[20] */
+0 /*bc lut[21] */
+0 /*c0 lut[22] */
+0 /*c4 lut[23] */
+0 /*c8 lut[24] */
+0 /*cc lut[25] */
+0 /*d0 lut[26] */
+0 /*d4 lut[27] */
+0 /*d8 lut[28] */
+0 /*dc lut[29] */
+0 /*e0 lut[30] */
+0 /*e4 lut[31] */
+0 /*e8 lut[32] */
+0 /*ec lut[33] */
+0 /*f0 lut[34] */
+0 /*f4 lut[35] */
+0 /*f8 lut[36] */
+0 /*fc lut[37] */
+0 /*100 lut[38] */
+0 /*104 lut[39] */
+0 /*108 lut[40] */
+0 /*10c lut[41] */
+0 /*110 lut[42] */
+0 /*114 lut[43] */
+0 /*118 lut[44] */
+0 /*11c lut[45] */
+0 /*120 lut[46] */
+0 /*124 lut[47] */
+0 /*128 lut[48] */
+0 /*12c lut[49] */
+0 /*130 lut[50] */
+0 /*134 lut[51] */
+0 /*138 lut[52] */
+0 /*13c lut[53] */
+0 /*140 lut[54] */
+0 /*144 lut[55] */
+0 /*148 lut[56] */
+0 /*14c lut[57] */
+0 /*150 lut[58] */
+0 /*154 lut[59] */
+0 /*158 lut[60] */
+0 /*15c lut[61] */
+0 /*160 lut[62] */
+0 /*164 lut[63] */
+1000001 /*168 read_status_ipcr=hex value to be written to IPCR register for reading status reg of device */
+0 /*16c enable_dqs_phase=0 or 1 */
+0 /*170 Not used */
+0 /*174 */
+0 /*178 */
+0 /*17c */
+0 /*180 */
+0 /*184 */
+0 /*188 */
+0 /*18c */
+0 /*190 */
+0 /*194 DQS pin pad setting override */
+0 /*198 SCLK pin pad setting override */
+0 /*19c DATA pins pad setting override */
+0 /*1a0 CS pins pad setting override */
+0 /*1a4 0: dqs loopback from pad/1: dqs loopback internally */
+0 /*1a8 dqs phase selection */
+0 /*1ac dqs fa delay chain selection */
+0 /*1b0 dqs fb delay chain selection */
+0 /*1b4 sclk fa delay chain selection */
+0 /*1b8 sclk fb delay chain selection */
+0 /*1bc */
+0 /*1c0 reserve[0] */
+0 /*1c4 reserve[1] */
+0 /*1c8 reserve[2] */
+0 /*1cc reserve[3] */
+0 /*1d0 reserve[4] */
+0 /*1d4 reserve[5] */
+0 /*1d8 reserve[6] */
+0 /*1dc reserve[7] */
+0 /*1e0 reserve[8] */
+0 /*1e4 reserve[9] */
+0 /*1e8 reserve[10] */
+0 /*1ec reserve[11] */
+0 /*1f0 reserve[12] */
+0 /*1f4 reserve[13] */
+0 /*1f8 reserve[14] */
+c0ffee01 /*1fc tag, QSPI configuration tag, should be 0xc0ffee01 */
diff --git a/board/boundary/nitrogen7/qspi_param.awk b/board/boundary/nitrogen7/qspi_param.awk
new file mode 100644
index 0000000000000000000000000000000000000000..351fabbfa8cebbda32918402ab66ec6d1d66ec10
--- /dev/null
+++ b/board/boundary/nitrogen7/qspi_param.awk
@@ -0,0 +1,12 @@
+#!/usr/bin/awk -f
+{
+ s="00000000"$1;
+ l=length(s);
+ if(!((NR-1)%4))
+ printf "%03x ",(NR-1)*4;
+ for(i=l-1;i>l-8;i-=2)
+ printf " %s",substr(s,i,2);
+ if(!(NR%4))
+ printf "\n";
+}
+
diff --git a/configs/nitrogen7_defconfig b/configs/nitrogen7_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..d0e1de0ed6fce807dbe786f0dacb48fdee2f78ff
--- /dev/null
+++ b/configs/nitrogen7_defconfig
@@ -0,0 +1,76 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX7=y
+CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_TARGET_NITROGEN7=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+CONFIG_IMX_RDC=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen7/nitrogen7.cfg,MX7D,DDR_MB=1024,DEFCONFIG=\"nitrogen7\""
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12000000
+CONFIG_FASTBOOT_BUF_SIZE=0x26000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_FSL_ESDHC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
+CONFIG_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Boundary"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_VIDEO=y
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/nitrogen7.h b/include/configs/nitrogen7.h
new file mode 100644
index 0000000000000000000000000000000000000000..81f0ad0db6ce34440c1984f8352382967ce61977
--- /dev/null
+++ b/include/configs/nitrogen7.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX7D SABRESD board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __NITROGEN7_CONFIG_H
+#define __NITROGEN7_CONFIG_H
+
+#include "mx7_common.h"
+
+#define CONFIG_DBG_MONITOR
+#define PHYS_SDRAM_SIZE SZ_1G
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_DFU_MMC
+
+/* ENET1 */
+#define IMX_FEC_BASE ENET_IPS_BASE_ADDR
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE3000
+#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
+
+#ifdef CONFIG_SPI_FLASH
+/* #define CONFIG_SYS_FSL_QSPI_AHB */
+#define FSL_QSPI_FLASH_NUM 1
+#define FSL_QSPI_FLASH_SIZE SZ_16M
+#endif
+
+#undef CONFIG_BOOTM_NETBSD
+#undef CONFIG_BOOTM_PLAN9
+#undef CONFIG_BOOTM_RTEMS
+
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+
+#define CONFIG_FEC_MXC_PHYADDR 4
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
+#define BD_CONSOLE "ttymxc0"
+#define BD_I2C_MASK 0xf
+
+/* M4 specific */
+#define SYS_AUXCORE_BOOTDATA_DDR 0x9ff00000
+#define SYS_AUXCORE_BOOTDATA_OCRAM 0x00910000
+#define SYS_AUXCORE_BOOTDATA_QSPI 0x601e0000
+#define SYS_AUXCORE_BOOTDATA_TCM 0x007F8000
+#define EXTRA_ENV_M4 \
+ "loadm4image=load ${devtype} ${devnum}:1 ${loadaddr} ${m4image}\0" \
+ "m4boot=run m4boot_nor\0" \
+ "m4boot_ext=load ${devtype} ${devnum}:1 ${m4loadaddr} ${m4image}; " \
+ "dcache flush; bootaux ${m4loadaddr}\0" \
+ "m4boot_nor=sf probe; sf read ${m4loadaddr} ${m4offset} ${m4size}; " \
+ "dcache flush; bootaux ${m4loadaddr}\0" \
+ "m4boot_qspi=bootaux "__stringify(SYS_AUXCORE_BOOTDATA_QSPI)"\0" \
+ "m4image=m4_fw.bin\0" \
+ "m4loadaddr="__stringify(SYS_AUXCORE_BOOTDATA_TCM)"\0" \
+ "m4loaddevs=mmc\0" \
+ "m4offset=0x1e0000\0" \
+ "m4size=0x8000\0" \
+ "m4update=for devtype in ${m4loaddevs}; do " \
+ "for devnum in 0 1 ; do ${devtype} dev ${devnum} ;" \
+ "if run loadm4image; then " \
+ "sf probe; " \
+ "sf erase ${m4offset} ${m4size}; " \
+ "sf write ${loadaddr} ${m4offset} ${filesize}; " \
+ "exit; " \
+ "fi; " \
+ "done; " \
+ "done\0"
+
+#include "boundary.h"
+#define CONFIG_EXTRA_ENV_SETTINGS BD_BOUNDARY_ENV_SETTINGS \
+ "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
+ "rdinit=/linuxrc " \
+ "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
+ "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
+ "g_mass_storage.iSerialNumber=\"\" "\
+ "clk_ignore_unused "\
+ "\0" \
+ "initrd_addr=0x83800000\0" \
+ "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
+ EXTRA_ENV_M4
+
+#endif /* __CONFIG_H */