diff --git a/board/boundary/nitrogen8mm_som/spl.c b/board/boundary/nitrogen8mm_som/spl.c
index 6e4d32596ac8e25845e47ddbe421103a14231987..cbcaff4e01b779bb9ff37048168831f6b13531f2 100644
--- a/board/boundary/nitrogen8mm_som/spl.c
+++ b/board/boundary/nitrogen8mm_som/spl.c
@@ -225,18 +225,6 @@ int power_init_boundary(void)
 
 void spl_board_init(void)
 {
-	int i;
-	enable_tzc380();
-
-	for (i = 0; i < ARRAY_SIZE(i2c_pad_info1); i++)
-		setup_i2c(i, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1[i]);
-
-	malloc(sizeof(int));
-
-	power_init_boundary();
-	/* DDR initialization */
-	spl_dram_init();
-
 #ifndef CONFIG_SPL_USB_SDP_SUPPORT
 	/* Serial download mode */
 	if (is_usb_boot()) {
@@ -259,6 +247,9 @@ int board_fit_config_name_match(const char *name)
 
 void board_init_f(ulong dummy)
 {
+	int ret;
+	int i;
+
 	/* Clear global data */
 	memset((void *)gd, 0, sizeof(gd_t));
 
@@ -273,5 +264,20 @@ void board_init_f(ulong dummy)
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
 
+	ret = spl_init();
+	if (ret) {
+		printf("spl_init() failed: %d\n", ret);
+		hang();
+	}
+
+	enable_tzc380();
+
+	for (i = 0; i < ARRAY_SIZE(i2c_pad_info1); i++)
+		setup_i2c(i, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1[i]);
+
+	power_init_boundary();
+	/* DDR initialization */
+	spl_dram_init();
+
 	board_init_r(NULL, 0);
 }
diff --git a/include/configs/nitrogen8mm_som.h b/include/configs/nitrogen8mm_som.h
index f9fb8ad08de2014330f25e7bce6e906fa0863af4..b79cf4cfba78980fd8cb1edd4f6933ae29b5edcd 100644
--- a/include/configs/nitrogen8mm_som.h
+++ b/include/configs/nitrogen8mm_som.h
@@ -23,11 +23,12 @@
 #ifdef CONFIG_SPL_BUILD
 /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
 #define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
-#define CONFIG_SPL_STACK		0x91fff0
-#define CONFIG_SPL_BSS_START_ADDR      0x00910000
-#define CONFIG_SPL_BSS_MAX_SIZE        0x1000	/* 4 KB */
-#define CONFIG_SYS_SPL_MALLOC_START    0x00911000
-#define CONFIG_SYS_SPL_MALLOC_SIZE     0x3000	/* 12 KB */
+#define CONFIG_SPL_STACK		0x0091fff0
+#define CONFIG_SPL_BSS_START_ADDR	0x00910000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x00001000	/* 4 KB */
+#define CONFIG_SYS_SPL_MALLOC_START	0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00080000	/* 512 KB */
+#define CONFIG_MALLOC_F_ADDR		0x00911000	/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
 #define CONFIG_SYS_ICACHE_OFF
 #define CONFIG_SYS_DCACHE_OFF