diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index 3337d8cc3304c567829311c41f0b7181d603f5b0..e643037d2745690afcff59de3636c2683b71d51c 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -73,11 +73,6 @@ void cpu_init_f (volatile immap_t * im)
 			  (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
 #endif
 
-#ifdef CFG_SPCR_TSECEP
-	/* eTSEC Emergency priority */
-	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) | (CFG_SPCR_TSECEP << SPCR_TSECEP_SHIFT);
-#endif
-
 #ifdef CFG_ACR_RPTCNT
 	/* Arbiter repeat count */
 	im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
@@ -85,7 +80,7 @@ void cpu_init_f (volatile immap_t * im)
 #endif
 
 #ifdef CFG_SPCR_TSECEP
-	/* all TSEC's Emergency priority */
+	/* all eTSEC's Emergency priority */
 	im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) |
 			   (CFG_SPCR_TSECEP << SPCR_TSECEP_SHIFT);
 #endif
diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
index 61c937981c3bd270e1f3fc333c335d651e4c8dde..f598699b2c6271564850c8ae5e549072fd39cd1b 100644
--- a/cpu/mpc83xx/speed.c
+++ b/cpu/mpc83xx/speed.c
@@ -367,17 +367,17 @@ int get_clocks(void)
 #endif
 
 #if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
-	switch ((sccr & SCCR_SATACM) >> SCCR_SATACM_SHIFT) {
-	case SCCR_SATACM_0:
+	switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
+	case 0:
 		sata_clk = 0;
 		break;
-	case SCCR_SATACM_1:
+	case 1:
 		sata_clk = csb_clk;
 		break;
-	case SCCR_SATACM_2:
+	case 2:
 		sata_clk = csb_clk / 2;
 		break;
-	case SCCR_SATACM_3:
+	case 3:
 		sata_clk = csb_clk / 3;
 		break;
 	default:
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 39cecf21c2b52729d2b5a665fbf5e8a6ebfa9b37..df052e3d4c73fe2dcb62f13b5e5c7762e33a9e9d 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -725,6 +725,7 @@
 #define SCCR_USBCM_3			0x00F00000
 
 #elif defined(CONFIG_MPC8313)
+/* TSEC1 bits are for TSEC2 as well */
 #define SCCR_TSEC1CM			0xc0000000
 #define SCCR_TSEC1CM_SHIFT		30
 #define SCCR_TSEC1CM_0			0x00000000
@@ -732,13 +733,6 @@
 #define SCCR_TSEC1CM_2			0x80000000
 #define SCCR_TSEC1CM_3			0xC0000000
 
-#define SCCR_TSEC2CM			0x30000000
-#define SCCR_TSEC2CM_SHIFT		28
-#define SCCR_TSEC2CM_0			0x00000000
-#define SCCR_TSEC2CM_1			0x10000000
-#define SCCR_TSEC2CM_2			0x20000000
-#define SCCR_TSEC2CM_3			0x30000000
-
 #define SCCR_TSEC1ON			0x20000000
 #define SCCR_TSEC1ON_SHIFT		29
 #define SCCR_TSEC2ON			0x10000000
@@ -838,6 +832,8 @@
 #define SCCR_PCIEXP2CM_3		0x000c0000
 
 /* All of the four SATA controllers must have the same clock ratio */
+#define SCCR_SATA1CM			0x000000c0
+#define SCCR_SATA1CM_SHIFT		6
 #define SCCR_SATACM			0x000000ff
 #define SCCR_SATACM_SHIFT		0
 #define SCCR_SATACM_0			0x00000000