diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 0452cb3c4f5eb89203eb5eda5a16b5278ffe047f..aecdb47b8ac510cdf91223f715019b11fbb77446 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -452,6 +452,9 @@ config TARGET_NIT6XLITE
 config TARGET_NITROGEN6_MAX
 	bool "nitrogen6_max"
 
+config TARGET_NITROGEN6_SCM
+	bool "nitrogen6_scm"
+
 config TARGET_NITROGEN6X
 	bool "nitrogen6x"
 	imply USB_HOST_ETHER
@@ -625,6 +628,7 @@ source "board/boundary/mx6_r/Kconfig"
 source "board/boundary/neol/Kconfig"
 source "board/boundary/nit6xlite/Kconfig"
 source "board/boundary/nitrogen6_max/Kconfig"
+source "board/boundary/nitrogen6_scm/Kconfig"
 source "board/boundary/nitrogen6x/Kconfig"
 source "board/boundary/ys/Kconfig"
 source "board/bticino/mamoj/Kconfig"
diff --git a/board/boundary/nitrogen6_scm/Kconfig b/board/boundary/nitrogen6_scm/Kconfig
new file mode 100644
index 0000000000000000000000000000000000000000..4231ab93dc2fe1f56394aae33f0a32b188f7b0ac
--- /dev/null
+++ b/board/boundary/nitrogen6_scm/Kconfig
@@ -0,0 +1,20 @@
+if TARGET_NITROGEN6_SCM
+
+config SYS_CPU
+	default "armv7"
+
+config SYS_BOARD
+	default "nitrogen6_scm"
+
+config SYS_VENDOR
+	default "boundary"
+
+config SYS_SOC
+	default "mx6"
+
+config SYS_CONFIG_NAME
+	default "nitrogen6_scm"
+
+source "board/boundary/common/Kconfig"
+
+endif
diff --git a/board/boundary/nitrogen6_scm/MAINTAINERS b/board/boundary/nitrogen6_scm/MAINTAINERS
new file mode 100644
index 0000000000000000000000000000000000000000..9ed28f947cfc3e5d0a2a28f60b0a84b5ded2330c
--- /dev/null
+++ b/board/boundary/nitrogen6_scm/MAINTAINERS
@@ -0,0 +1,6 @@
+NITROGEN6_SCM BOARD
+M:	Troy Kisky <troy.kisky@boundarydevices.com>
+S:	Maintained
+F:	board/boundary/nitrogen6_scm/
+F:	include/configs/nitrogen6_scm.h
+F:	configs/nitrogen6_scm_defconfig
diff --git a/board/boundary/nitrogen6_scm/Makefile b/board/boundary/nitrogen6_scm/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..0fff1805f5999a7cc2a8fdd46f968de9801ffad5
--- /dev/null
+++ b/board/boundary/nitrogen6_scm/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := nitrogen6_scm.o
diff --git a/board/boundary/nitrogen6_scm/nitrogen6_scm.c b/board/boundary/nitrogen6_scm/nitrogen6_scm.c
new file mode 100644
index 0000000000000000000000000000000000000000..6b78de859f0f16bee123dbabed683ac68de8eede
--- /dev/null
+++ b/board/boundary/nitrogen6_scm/nitrogen6_scm.c
@@ -0,0 +1,443 @@
+/*
+ * Copyright (C) 2015 Boundary Devices, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/fbpanel.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <linux/sizes.h>
+#include <malloc.h>
+#include <mmc.h>
+#include <usb.h>
+#include <usb/ehci-ci.h>
+#include "../common/bd_common.h"
+#include "../common/padctrl.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CSI_PAD_CTL	PAD_CTL_DSE_120ohm
+
+#define ESAI_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS | PAD_CTL_ODE)
+
+#define LCDIF_PAD_CTL	PAD_CTL_DSE_120ohm
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+#define USDHC1_PAD_CTRL (PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW | \
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+#define USDHC1_CLK_PAD_CTRL (PAD_CTL_SPEED_LOW | \
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+#define USDHC2_PAD_CTRL (PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW | \
+	PAD_CTL_DSE_80ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+#define USDHC2_CLK_PAD_CTRL (PAD_CTL_SPEED_LOW | \
+	PAD_CTL_DSE_80ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+static const iomux_v3_cfg_t init_pads[] = {
+	/* bt_rfkill */
+#define GP_BT_RFKILL_RESET	IMX_GPIO_NR(2, 18)
+	IOMUX_PAD_CTRL(KEY_ROW3__GPIO2_IO_18, WEAK_PULLDN),
+
+	/* CSI */
+	IOMUX_PAD_CTRL(CSI_MCLK__CSI1_MCLK, CSI_PAD_CTL),
+	IOMUX_PAD_CTRL(CSI_PIXCLK__CSI1_PIXCLK, CSI_PAD_CTL),
+	IOMUX_PAD_CTRL(CSI_VSYNC__CSI1_VSYNC, CSI_PAD_CTL),
+	IOMUX_PAD_CTRL(CSI_HSYNC__CSI1_HSYNC, CSI_PAD_CTL),
+	IOMUX_PAD_CTRL(CSI_DATA00__CSI1_DATA_2, CSI_PAD_CTL),
+	IOMUX_PAD_CTRL(CSI_DATA01__CSI1_DATA_3, CSI_PAD_CTL),
+	IOMUX_PAD_CTRL(CSI_DATA02__CSI1_DATA_4, CSI_PAD_CTL),
+	IOMUX_PAD_CTRL(CSI_DATA03__CSI1_DATA_5, CSI_PAD_CTL),
+	IOMUX_PAD_CTRL(CSI_DATA04__CSI1_DATA_6, CSI_PAD_CTL),
+	IOMUX_PAD_CTRL(CSI_DATA05__CSI1_DATA_7, CSI_PAD_CTL),
+	IOMUX_PAD_CTRL(CSI_DATA06__CSI1_DATA_8, CSI_PAD_CTL),
+	IOMUX_PAD_CTRL(CSI_DATA07__CSI1_DATA_9, CSI_PAD_CTL),
+
+#define GP_OV5642_RESET		IMX_GPIO_NR(7, 4)
+	IOMUX_PAD_CTRL(SD3_DATA2__GPIO7_IO_4, WEAK_PULLDN),
+#define GP_OV5642_PWRDN		IMX_GPIO_NR(7, 5)
+	IOMUX_PAD_CTRL(SD3_DATA3__GPIO7_IO_5, WEAK_PULLUP),
+
+	/* ECSPI1 (serial nor eeprom) */
+	IOMUX_PAD_CTRL(KEY_COL1__ECSPI1_MISO, SPI_PAD_CTRL),
+	IOMUX_PAD_CTRL(KEY_ROW0__ECSPI1_MOSI, SPI_PAD_CTRL),
+	IOMUX_PAD_CTRL(KEY_COL0__ECSPI1_SCLK, SPI_PAD_CTRL),
+#define GP_ECSPI1_NOR_CS	IMX_GPIO_NR(2, 16)
+	IOMUX_PAD_CTRL(KEY_ROW1__GPIO2_IO_16, WEAK_PULLUP),
+
+	/* ESAI */
+	IOMUX_PAD_CTRL(NAND_WE_B__ESAI_TX5_RX0, ESAI_PAD_CTRL),
+	IOMUX_PAD_CTRL(NAND_CE0_B__ESAI_TX_CLK, ESAI_PAD_CTRL),
+	IOMUX_PAD_CTRL(NAND_READY_B__ESAI_TX1, ESAI_PAD_CTRL),
+	IOMUX_PAD_CTRL(NAND_RE_B__ESAI_TX_FS, ESAI_PAD_CTRL),
+
+	/* gpio - keys */
+#define GP_GPIOKEY_POWER	IMX_GPIO_NR(4, 27)
+	IOMUX_PAD_CTRL(QSPI1B_DATA3__GPIO4_IO_27, WEAK_PULLUP),
+
+	/* gpio - output */
+#define GP_POWER_OFF		IMX_GPIO_NR(4, 26)
+	IOMUX_PAD_CTRL(QSPI1B_DATA2__GPIO4_IO_26, WEAK_PULLDN),
+
+	/* hogs - Test points */
+#define GP_TP16		IMX_GPIO_NR(7, 6)
+	IOMUX_PAD_CTRL(SD3_DATA4__GPIO7_IO_6, WEAK_PULLUP),
+#define GP_TP17		IMX_GPIO_NR(7, 7)
+	IOMUX_PAD_CTRL(SD3_DATA5__GPIO7_IO_7, WEAK_PULLUP),
+#define GP_TP18		IMX_GPIO_NR(6, 14)
+	IOMUX_PAD_CTRL(SD4_DATA0__GPIO6_IO_14, WEAK_PULLUP),
+#define GP_TP19		IMX_GPIO_NR(6, 15)
+	IOMUX_PAD_CTRL(SD4_DATA1__GPIO6_IO_15, WEAK_PULLUP),
+
+#define GP_I2C3_J4_RESET	IMX_GPIO_NR(1, 8)
+	IOMUX_PAD_CTRL(GPIO1_IO08__GPIO1_IO_8, WEAK_PULLUP),
+#define GPIRQ_I2C3_J4	IMX_GPIO_NR(1, 9)
+	IOMUX_PAD_CTRL(GPIO1_IO09__GPIO1_IO_9, WEAK_PULLUP),
+
+	/* i2c4a - max77818 */
+#define GPIRQ_MAX77818_INTB		IMX_GPIO_NR(7, 0)
+	IOMUX_PAD_CTRL(SD3_CLK__GPIO7_IO_0, WEAK_PULLUP),
+#define GPIRQ_MAX77818_WCINOKB		IMX_GPIO_NR(7, 8)
+	IOMUX_PAD_CTRL(SD3_DATA6__GPIO7_IO_8, WEAK_PULLUP),
+#define GPIRQ_MAX77818_INOKB	IMX_GPIO_NR(7, 9)
+	IOMUX_PAD_CTRL(SD3_DATA7__GPIO7_IO_9, WEAK_PULLUP),
+
+	/* PWM1 for rgb panel */
+#define GP_BACKLIGHT_RGB 	IMX_GPIO_NR(1, 10)
+	IOMUX_PAD_CTRL(GPIO1_IO10__GPIO1_IO_10, WEAK_PULLDN_OUTPUT),
+
+	/* reg_5v_en */
+#define GP_5V_BST_EN	IMX_GPIO_NR(6, 12)
+	IOMUX_PAD_CTRL(SD4_CLK__GPIO6_IO_12, WEAK_PULLDN),
+
+	/* reg_wlan_en */
+#define GP_REG_WLAN_EN	IMX_GPIO_NR(2, 13)
+	IOMUX_PAD_CTRL(KEY_COL3__GPIO2_IO_13, WEAK_PULLDN),
+	/* 32K clock, off for now */
+#define GP_WLAN_LF_CLK		IMX_GPIO_NR(1, 11)
+	IOMUX_PAD_CTRL(GPIO1_IO11__GPIO1_IO_11, WEAK_PULLDN_OUTPUT),
+
+	/* uart1 */
+	IOMUX_PAD_CTRL(GPIO1_IO04__UART1_TX, UART_PAD_CTRL),
+	IOMUX_PAD_CTRL(GPIO1_IO05__UART1_RX, UART_PAD_CTRL),
+
+	/* uart2 */
+	IOMUX_PAD_CTRL(GPIO1_IO06__UART2_TX, UART_PAD_CTRL),
+	IOMUX_PAD_CTRL(GPIO1_IO07__UART2_RX, UART_PAD_CTRL),
+
+	/* uart3 - wifi */
+	IOMUX_PAD_CTRL(NAND_DATA07__UART3_TX, UART_PAD_CTRL),
+	IOMUX_PAD_CTRL(NAND_DATA06__UART3_RX, UART_PAD_CTRL),
+	IOMUX_PAD_CTRL(NAND_DATA05__UART3_CTS_B, UART_PAD_CTRL),
+	IOMUX_PAD_CTRL(NAND_DATA04__UART3_RTS_B, UART_PAD_CTRL),
+
+	/* uart5 */
+	IOMUX_PAD_CTRL(SD4_DATA5__UART5_TX, UART_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD4_DATA4__UART5_RX, UART_PAD_CTRL),
+
+	/* USB OTG */
+#define GP_USB_OTG1_OC		IMX_GPIO_NR(4, 29)
+	IOMUX_PAD_CTRL(QSPI1B_SCLK__GPIO4_IO_29, WEAK_PULLUP),
+#define GP_USB_OTG1_ID		IMX_GPIO_NR(4, 28)
+	IOMUX_PAD_CTRL(QSPI1B_DQS__GPIO4_IO_28, WEAK_PULLUP),
+#define GP_USB_OTG1_PWR		IMX_GPIO_NR(4, 24)
+	IOMUX_PAD_CTRL(QSPI1B_DATA0__GPIO4_IO_24, WEAK_PULLDN_OUTPUT),
+
+	/* USB OTG2 */
+#define GP_USB_OTG2_OC		IMX_GPIO_NR(4, 31)
+	IOMUX_PAD_CTRL(QSPI1B_SS1_B__GPIO4_IO_31, WEAK_PULLDN_OUTPUT),
+#define GP_USB_OTG2_PWR		IMX_GPIO_NR(4, 25)
+	IOMUX_PAD_CTRL(QSPI1B_DATA1__GPIO4_IO_25, WEAK_PULLDN_OUTPUT),
+
+	/* usdhc1 - microSD */
+	IOMUX_PAD_CTRL(SD1_CLK__USDHC1_CLK, USDHC1_CLK_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD1_CMD__USDHC1_CMD, USDHC1_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD1_DATA0__USDHC1_DATA0, USDHC1_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD1_DATA1__USDHC1_DATA1, USDHC1_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD1_DATA2__USDHC1_DATA2, USDHC1_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD1_DATA3__USDHC1_DATA3, USDHC1_PAD_CTRL),
+#define GP_USDHC1_CD	IMX_GPIO_NR(4, 30)
+	IOMUX_PAD_CTRL(QSPI1B_SS0_B__GPIO4_IO_30, WEAK_PULLUP),
+
+	/* usdhc2 - wifi */
+	IOMUX_PAD_CTRL(SD2_CLK__USDHC2_CLK, USDHC2_CLK_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_CMD__USDHC2_CMD, USDHC2_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_DATA0__USDHC2_DATA0, USDHC2_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_DATA1__USDHC2_DATA1, USDHC2_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_DATA2__USDHC2_DATA2, USDHC2_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_DATA3__USDHC2_DATA3, USDHC2_PAD_CTRL),
+
+	/* WLAN wifi silex */
+#define GPIRQ_WLAN		IMX_GPIO_NR(2, 14)
+	IOMUX_PAD_CTRL(KEY_COL4__GPIO2_IO_14, WEAK_PULLDN),
+#define GP_WLAN_CLK_REQ		IMX_GPIO_NR(2, 12)
+	IOMUX_PAD_CTRL(KEY_COL2__GPIO2_IO_12, WEAK_PULLDN),
+#define GP_WLAN_QOW		IMX_GPIO_NR(2, 17)
+	IOMUX_PAD_CTRL(KEY_ROW2__GPIO2_IO_17, WEAK_PULLDN),
+#define GP_BT_HOST_WAKE 	IMX_GPIO_NR(1, 13)
+	IOMUX_PAD_CTRL(GPIO1_IO13__GPIO1_IO_13, WEAK_PULLDN),
+};
+
+
+#ifdef CONFIG_CMD_FBPANEL
+static const iomux_v3_cfg_t rgb_pads[] = {
+	/* LCDIF1 */
+	IOMUX_PAD_CTRL(LCD1_CLK__LCDIF1_CLK, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_ENABLE__LCDIF1_ENABLE, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_HSYNC__LCDIF1_HSYNC, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_VSYNC__LCDIF1_VSYNC, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_RESET__LCDIF1_RESET, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA00__LCDIF1_DATA_0, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA01__LCDIF1_DATA_1, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA02__LCDIF1_DATA_2, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA03__LCDIF1_DATA_3, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA04__LCDIF1_DATA_4, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA05__LCDIF1_DATA_5, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA06__LCDIF1_DATA_6, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA07__LCDIF1_DATA_7, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA08__LCDIF1_DATA_8, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA09__LCDIF1_DATA_9, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA10__LCDIF1_DATA_10, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA11__LCDIF1_DATA_11, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA12__LCDIF1_DATA_12, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA13__LCDIF1_DATA_13, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA14__LCDIF1_DATA_14, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA15__LCDIF1_DATA_15, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA16__LCDIF1_DATA_16, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA17__LCDIF1_DATA_17, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA18__LCDIF1_DATA_18, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA19__LCDIF1_DATA_19, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA20__LCDIF1_DATA_20, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA21__LCDIF1_DATA_21, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA22__LCDIF1_DATA_22, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA23__LCDIF1_DATA_23, LCDIF_PAD_CTL),
+};
+#endif
+
+static const iomux_v3_cfg_t rgb_gpio_pads[] = {
+	/* LCDIF1 */
+	IOMUX_PAD_CTRL(LCD1_CLK__GPIO3_IO_0, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_ENABLE__GPIO3_IO_25, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_HSYNC__GPIO3_IO_26, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_VSYNC__GPIO3_IO_28, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_RESET__GPIO3_IO_27, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA00__GPIO3_IO_1, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA01__GPIO3_IO_2, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA02__GPIO3_IO_3, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA03__GPIO3_IO_4, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA04__GPIO3_IO_5, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA05__GPIO3_IO_6, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA06__GPIO3_IO_7, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA07__GPIO3_IO_8, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA08__GPIO3_IO_9, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA09__GPIO3_IO_10, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA10__GPIO3_IO_11, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA11__GPIO3_IO_12, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA12__GPIO3_IO_13, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA13__GPIO3_IO_14, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA14__GPIO3_IO_15, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA15__GPIO3_IO_16, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA16__GPIO3_IO_17, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA17__GPIO3_IO_18, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA18__GPIO3_IO_19, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA19__GPIO3_IO_20, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA20__GPIO3_IO_21, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA21__GPIO3_IO_22, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA22__GPIO3_IO_23, LCDIF_PAD_CTL),
+	IOMUX_PAD_CTRL(LCD1_DATA23__GPIO3_IO_24, LCDIF_PAD_CTL),
+};
+
+static const struct i2c_pads_info i2c_pads[] = {
+	I2C_PADS_INFO_ENTRY(I2C2, GPIO1_IO02, 1, 2, GPIO1_IO03, 1, 3, I2C_PAD_CTRL),	/* PMIC */
+	I2C_PADS_INFO_ENTRY(I2C3, ENET2_RX_CLK, 2, 8, ENET2_TX_CLK, 2, 9, I2C_PAD_CTRL), /* J4 touch */
+	I2C_PADS_INFO_ENTRY(I2C4, SD3_DATA0, 7, 2, SD3_DATA1, 7, 3, I2C_PAD_CTRL),	/* PCA9540B switch, charger/ov5642 */
+};
+#define I2C_BUS_CNT	3
+
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? GP_ECSPI1_NOR_CS : (cs >> 8) ? (cs >> 8) : -1;
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET	0x800
+#define UCTRL_PWR_POL		(1 << 9)
+
+int board_usb_phy_mode(int port)
+{
+	if (port == 1)
+		return USB_INIT_HOST;
+	else
+		return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+	u32 *usbnc_usb_ctrl;
+
+	if (port > 1)
+		return -EINVAL;
+	usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+			port * 4);
+	setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+	return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+	gpio_set_value(port ? GP_USB_OTG2_PWR: GP_USB_OTG1_PWR, on);
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg board_usdhc_cfg[] = {
+	{.esdhc_base = USDHC1_BASE_ADDR, .bus_width = 4,
+			.gp_cd = GP_USDHC1_CD},
+};
+#endif
+
+#ifdef CONFIG_CMD_FBPANEL
+void board_enable_lcd(const struct display_info_t *di, int enable)
+{
+	if (enable)
+		SETUP_IOMUX_PADS(rgb_pads);
+	else
+		SETUP_IOMUX_PADS(rgb_gpio_pads);
+	gpio_direction_output(GP_BACKLIGHT_RGB, enable);
+}
+
+static const struct display_info_t displays[] = {
+	/* tsc2004 */
+	VDF_DC050WX(LCD, "DC050WX", RGB24, 0, NULL, 2, 0x48),
+	VDF_CLAA_WVGA(LCD, "CLAA-WVGA", RGB666, 0, fbp_detect_i2c, 2, 0x48),
+	VDF_SHARP_WVGA(LCD, "sharp-wvga", RGB24, 0, NULL, 2, 0x48),
+	VDF_QVGA(LCD, "qvga", RGB24, 0, NULL, 2, 0x48),
+	VDF_AT035GT_07ET3(LCD, "AT035GT-07ET3", RGB24, 0, NULL, 2, 0x48),
+
+	VDF_1280_720M_60(LCD, "1280x720M@60", RGB24, 0, fbp_detect_i2c, 2, 0x50),
+	VDF_1920_1080M_60(LCD, "1920x1080M@60", RGB24, 0, NULL, 2, 0x50),
+	VDF_1024_768M_60(LCD, "1024x768M@60", RGB24, 0, NULL, 2, 0x50),
+
+	/* fusion7 specific touchscreen */
+	VDF_FUSION7(LCD, "fusion7", RGB666, 0, fbp_detect_i2c, 2, 0x10),
+
+	VDF_LSA40AT9001(LCD, "LSA40AT9001", RGB24, 0, NULL, 0, 0x00),
+};
+#define display_cnt	ARRAY_SIZE(displays)
+#else
+#define displays	NULL
+#define display_cnt	0
+#endif
+
+static const unsigned short gpios_out_low[] = {
+	GP_POWER_OFF,		/* 0 - on */
+	GP_5V_BST_EN,		/* 0 - off */
+	GP_USB_OTG1_PWR,	/* 0 - off */
+	GP_USB_OTG2_PWR,	/* 0 - off */
+	GP_OV5642_RESET,
+	GP_I2C3_J4_RESET,
+	GP_BACKLIGHT_RGB,
+	GP_REG_WLAN_EN,
+	GP_BT_RFKILL_RESET,
+	GP_WLAN_LF_CLK,
+};
+
+static const unsigned short gpios_out_high[] = {
+	GP_OV5642_PWRDN,
+	GP_ECSPI1_NOR_CS,
+};
+
+static const unsigned short gpios_in[] = {
+	GP_TP16,
+	GP_TP17,
+	GP_TP18,
+	GP_TP19,
+	GP_GPIOKEY_POWER,
+	GPIRQ_MAX77818_INTB,
+	GPIRQ_MAX77818_WCINOKB,
+	GPIRQ_MAX77818_INOKB,
+	GPIRQ_I2C3_J4,
+	GP_USB_OTG1_OC,
+	GP_USB_OTG1_ID,
+	GP_USB_OTG2_OC,
+	GP_USDHC1_CD,
+	GPIRQ_WLAN,
+	GP_WLAN_CLK_REQ,
+	GP_WLAN_QOW,
+	GP_BT_HOST_WAKE,
+};
+
+int board_early_init_f(void)
+{
+	set_gpios_in(gpios_in, ARRAY_SIZE(gpios_in));
+	set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
+	set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
+	SETUP_IOMUX_PADS(init_pads);
+	SETUP_IOMUX_PADS(rgb_gpio_pads);
+	return 0;
+}
+
+void board_poweroff(void)
+{
+	gpio_set_value(GP_POWER_OFF, 1);
+	mdelay(500);
+}
+
+int board_init(void)
+{
+	common_board_init(i2c_pads, I2C_BUS_CNT, 0, displays, display_cnt, 0);
+	return 0;
+}
+
+#ifdef CONFIG_CMD_BMODE
+const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"mmc0",        MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
+	{"mmc1",        MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
+	{NULL,          0},
+};
+#endif
+
+const struct button_key board_buttons[] = {
+	{"Power",	GP_GPIOKEY_POWER,	'P', 1},
+	{NULL, 0, 0, 0},
+};
+
+static int _do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	board_poweroff();
+	return 0;
+}
+
+U_BOOT_CMD(
+	poweroff, 70, 0, _do_poweroff,
+	"power down board",
+	""
+);
+
diff --git a/board/boundary/nitrogen6_scm/nitrogen6_scm.cfg b/board/boundary/nitrogen6_scm/nitrogen6_scm.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..ed0608825a839c5b6e074113ff53b5dcce75d708
--- /dev/null
+++ b/board/boundary/nitrogen6_scm/nitrogen6_scm.cfg
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* enable cko1 as 32k for slow clock */
+/* DATA 4 0x020c4060 0x0000008e */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+/* IOMUX - DDR IO Type */
+DATA 4 0x020e0618 0x00080000
+DATA 4 0x020e05fc 0x00000000
+
+/* Clock */
+DATA 4 0x020e032c 0x00000030
+
+/* Address */
+DATA 4 0x020e0300 0x00000028
+DATA 4 0x020e02fc 0x00000028
+DATA 4 0x020e05f4 0x00000028
+
+/* Control */
+DATA 4 0x020e0340 0x00000028
+
+DATA 4 0x020e0320 0x00000000
+DATA 4 0x020e0310 0x00000000
+DATA 4 0x020e0314 0x00000000
+DATA 4 0x020e0614 0x00000028
+
+/* Data Strobe */
+DATA 4 0x020e05f8 0x00020000
+DATA 4 0x020e0330 0x00003028
+DATA 4 0x020e0334 0x00003028
+DATA 4 0x020e0338 0x00003028
+DATA 4 0x020e033c 0x00003028
+
+/* Data */
+DATA 4 0x020e0608 0x00020000
+DATA 4 0x020e060c 0x00000028
+DATA 4 0x020e0610 0x00000028
+DATA 4 0x020e061c 0x00000028
+DATA 4 0x020e0620 0x00000028
+DATA 4 0x020e02ec 0x00000028
+DATA 4 0x020e02f0 0x00000028
+DATA 4 0x020e02f4 0x00000028
+DATA 4 0x020e02f8 0x00000028
+
+/* */
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b085c 0x1b4700c7
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b0890 0x00380000
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b082c 0x51111111
+DATA 4 0x021b0830 0x51111111
+DATA 4 0x021b0834 0x51111111
+DATA 4 0x021b0838 0x51111111
+
+/* Read/Write Delay */
+DATA 4 0x021b0848 0x4244464a	/* MPRDDLCTL */
+DATA 4 0x021b0850 0x36343a34	/* MPWRDLCTL */
+DATA 4 0x021b08c0 0x2492244A
+DATA 4 0x021b083c 0x20000000
+DATA 4 0x021b0840 0x00000000
+DATA 4 0x021b08b8 0x00000800
+
+DATA 4 0x021b000c 0x33374133
+DATA 4 0x021b0004 0x00020024
+DATA 4 0x021b0010 0x00100A42
+DATA 4 0x021b0014 0x00000093
+DATA 4 0x021b0018 0x00001748
+DATA 4 0x021b002c 0x0f9f26d2
+DATA 4 0x021b0030 0x0000020e
+DATA 4 0x021b0038 0x00190778
+DATA 4 0x021b0008 0x00000000
+DATA 4 0x021b0040 0x0000004f
+DATA 4 0x021b0000 0x83110000
+
+DATA 4 0x021b001c 0x003f8030
+DATA 4 0x021b001c 0xff0a8030
+DATA 4 0x021b001c 0x82018030
+DATA 4 0x021b001c 0x04028030
+DATA 4 0x021b001c 0x01038030
+
+DATA 4 0x021b001c 0x003f8038
+DATA 4 0x021b001c 0xff0a8038
+DATA 4 0x021b001c 0x82018038
+DATA 4 0x021b001c 0x04028038
+DATA 4 0x021b001c 0x01038038
+
+DATA 4 0x021b0020 0x00001800
+DATA 4 0x021b0818 0x00000000
+DATA 4 0x021b0800 0xa1310003
+DATA 4 0x021b0004 0x00025576
+DATA 4 0x021b0404 0x00011006 
+DATA 4 0x021b001c 0x00000000
diff --git a/configs/nitrogen6_scm_defconfig b/configs/nitrogen6_scm_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..fa1d71993d7b52ba5c4573a621036533915eed33
--- /dev/null
+++ b/configs/nitrogen6_scm_defconfig
@@ -0,0 +1,70 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x87800000
+CONFIG_TARGET_NITROGEN6_SCM=y
+CONFIG_FEC_MAC_FUSE=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6_scm/nitrogen6_scm.cfg,MX6SX,DDR_MB=512,DEFCONFIG=\"nitrogen6_scm\""
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82000000
+CONFIG_FASTBOOT_BUF_SIZE=0x26000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FSL_ESDHC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_NETDEVICES=y
+CONFIG_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Boundary"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_VIDEO=y
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/nitrogen6_scm.h b/include/configs/nitrogen6_scm.h
new file mode 100644
index 0000000000000000000000000000000000000000..32067667d1dc13448a24e2c21d62988a82073be9
--- /dev/null
+++ b/include/configs/nitrogen6_scm.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Boundary Devices Nitrogen6SX
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+#define CONFIG_MACH_TYPE	3769
+#define CONFIG_ETHPRIME			"usb_ether"
+
+/* M4 specific */
+#define SYS_AUXCORE_BOOTDATA_DDR	0x9ff00000
+#define SYS_AUXCORE_BOOTDATA_OCRAM	0x00910000
+#define SYS_AUXCORE_BOOTDATA_TCM	0x007F8000
+#define EXTRA_ENV_M4 \
+	"m4image=m4_fw.bin\0" \
+	"m4offset=0x1e0000\0" \
+	"m4size=0x8000\0" \
+	"loadm4image=load ${dtype} ${disk}:1 ${loadaddr} ${m4image}\0" \
+	"m4update=for dtype in ${bootdevs}; do " \
+		"for disk in 0 1 ; do ${dtype} dev ${disk} ;" \
+			"if run loadm4image; then " \
+				"sf probe; " \
+				"sf erase ${m4offset} ${m4size}; " \
+				"sf write ${loadaddr} ${m4offset} ${filesize}; " \
+				"exit; " \
+			"fi; " \
+		"done; " \
+		"done\0" \
+	"m4loadaddr="__stringify(CONFIG_SYS_AUXCORE_BOOTDATA_TCM)"\0" \
+	"m4boot=run m4boot_nor\0" \
+	"m4boot_ext=load ${dtype} ${disk}:1 ${m4loadaddr} ${m4image}; " \
+		"dcache flush; bootaux ${m4loadaddr}\0" \
+	"m4boot_nor=sf probe; sf read ${m4loadaddr} ${m4offset} ${m4size}; " \
+		"dcache flush; bootaux ${m4loadaddr}\0"
+
+#define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(4, 10)
+#define CONFIG_SYS_AUXCORE_BOOTDATA	0x900000	/* M4 specific */
+#define CONFIG_SYS_FSL_ESDHC_GPIO_WP
+#define CONFIG_SYS_SPD_BUS_NUM	1
+
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+#define CONFIG_SYS_FSL_USDHC_NUM	1
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define BD_CONSOLE	"ttymxc0"
+#define BD_I2C_MASK	0xf
+
+#include "boundary.h"
+#define CONFIG_EXTRA_ENV_SETTINGS BD_BOUNDARY_ENV_SETTINGS \
+	EXTRA_ENV_M4
+
+#endif	       /* __CONFIG_H */