diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index e1578f3444a7d88c0b25bcca3fed886dc5256b81..3ebfc147c945ba8fbe81efbddc8d5ddd6c065ed8 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -419,6 +419,9 @@ config TARGET_INSP
 config TARGET_IOC
 	bool "ioc"
 
+config TARGET_JLM
+	bool "jlm"
+
 config TARGET_NITROGEN6X
 	bool "nitrogen6x"
 	imply USB_HOST_ETHER
@@ -581,6 +584,7 @@ source "board/boundary/hl/Kconfig"
 source "board/boundary/hp/Kconfig"
 source "board/boundary/insp/Kconfig"
 source "board/boundary/ioc/Kconfig"
+source "board/boundary/jlm/Kconfig"
 source "board/boundary/nitrogen6x/Kconfig"
 source "board/boundary/ys/Kconfig"
 source "board/bticino/mamoj/Kconfig"
diff --git a/board/boundary/jlm/Kconfig b/board/boundary/jlm/Kconfig
new file mode 100644
index 0000000000000000000000000000000000000000..8898a28714f5be7fe7662541723e01e80dfb186d
--- /dev/null
+++ b/board/boundary/jlm/Kconfig
@@ -0,0 +1,21 @@
+if TARGET_JLM
+
+config SYS_BOARD
+	default "jlm"
+
+config SYS_VENDOR
+	default "boundary"
+
+config SYS_SOC
+	default "mx6"
+
+config SYS_CONFIG_NAME
+	default "jlm"
+
+config ENV_WLMAC
+	bool
+	default	y
+
+source "board/boundary/common/Kconfig"
+
+endif
diff --git a/board/boundary/jlm/MAINTAINERS b/board/boundary/jlm/MAINTAINERS
new file mode 100644
index 0000000000000000000000000000000000000000..ace0b13e03b86cb0bc023e2959ee07d696070dc5
--- /dev/null
+++ b/board/boundary/jlm/MAINTAINERS
@@ -0,0 +1,6 @@
+NITROGEN6X BOARD
+M:	Troy Kisky <troy.kisky@boundarydevices.com>
+S:	Maintained
+F:	board/boundary/jlm/
+F:	include/configs/jlm.h
+F:	configs/jlm_defconfig
diff --git a/board/boundary/jlm/Makefile b/board/boundary/jlm/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..ef108366fd18036f205dae67d01934c728c90efa
--- /dev/null
+++ b/board/boundary/jlm/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2012-2013, Guennadi Liakhovetski <lg@denx.de>
+# (C) Copyright 2012-2013 Freescale Semiconductor, Inc.
+# Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := jlm.o
+obj-$(CONFIG_MXC_SPI_DISPLAY) += spi_display.o
\ No newline at end of file
diff --git a/board/boundary/jlm/jlm.c b/board/boundary/jlm/jlm.c
new file mode 100644
index 0000000000000000000000000000000000000000..b4363dcd477ad4b481df335d06a80ac99062649d
--- /dev/null
+++ b/board/boundary/jlm/jlm.c
@@ -0,0 +1,461 @@
+/*
+ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * This board has a SOM1 cpu card
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+#include <malloc.h>
+#include <asm/arch/mx6-pins.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/fbpanel.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/sata.h>
+#include <asm/mach-imx/spi.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <i2c.h>
+#include <input.h>
+#include <splash.h>
+#include <usb/ehci-ci.h>
+#include "spi_display.h"
+#include "../common/bd_common.h"
+#include "../common/padctrl.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define BUTTON_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define RGB_PAD_CTRL	PAD_CTL_DSE_120ohm
+
+#define SPI_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_SPEED_MED |	\
+	PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define UART_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+#define USDHC2_PAD_CTRL	(PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+#define USDHC3_PAD_CTRL	(PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+#define USDHC4_PAD_CTRL	(PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+/*
+ *
+ */
+static const iomux_v3_cfg_t init_pads[] = {
+	/* bt_rfkill */
+#define GP_BT_RFKILL_RESET	IMX_GPIO_NR(6, 16)
+	IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, WEAK_PULLDN),
+
+	/* ECSPI1 */
+	IOMUX_PAD_CTRL(EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
+	IOMUX_PAD_CTRL(EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
+	IOMUX_PAD_CTRL(EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
+#define GP_ECSPI1_NOR_CS	IMX_GPIO_NR(3, 19)
+	IOMUX_PAD_CTRL(EIM_D19__GPIO3_IO19, WEAK_PULLUP),
+
+	/* ECSPI2 */
+	IOMUX_PAD_CTRL(CSI0_DAT10__ECSPI2_MISO, SPI_PAD_CTRL),
+	IOMUX_PAD_CTRL(CSI0_DAT9__ECSPI2_MOSI, SPI_PAD_CTRL),
+	IOMUX_PAD_CTRL(CSI0_DAT8__ECSPI2_SCLK, SPI_PAD_CTRL),
+#define GP_ECSPI2_CS		IMX_GPIO_NR(5, 29)
+	IOMUX_PAD_CTRL(CSI0_DAT11__GPIO5_IO29, WEAK_PULLUP),	/* for spi displays */
+#define GP_SPI_DISPLAY_RESET	IMX_GPIO_NR(4, 20)
+	IOMUX_PAD_CTRL(DI0_PIN4__GPIO4_IO20, WEAK_PULLUP),
+
+	/* gpio_Keys - Button assignments for J14 */
+#define GP_GPIOKEY_BACK		IMX_GPIO_NR(2, 2)
+	IOMUX_PAD_CTRL(NANDF_D2__GPIO2_IO02, BUTTON_PAD_CTRL),
+#define GP_GPIOKEY_HOME		IMX_GPIO_NR(2, 4)
+	IOMUX_PAD_CTRL(NANDF_D4__GPIO2_IO04, BUTTON_PAD_CTRL),
+#define GP_GPIOKEY_MENU		IMX_GPIO_NR(2, 1)
+	IOMUX_PAD_CTRL(NANDF_D1__GPIO2_IO01, BUTTON_PAD_CTRL),
+	/* Labeled Search (mapped to Power under Android) */
+#define GP_GPIOKEY_POWER	IMX_GPIO_NR(2, 3)
+	IOMUX_PAD_CTRL(NANDF_D3__GPIO2_IO03, BUTTON_PAD_CTRL),
+#define GP_GPIOKEY_VOL_DOWN	IMX_GPIO_NR(4, 5)
+	IOMUX_PAD_CTRL(GPIO_19__GPIO4_IO05, BUTTON_PAD_CTRL),
+#define GP_GPIOKEY_VOL_UP	IMX_GPIO_NR(7, 13)
+	IOMUX_PAD_CTRL(GPIO_18__GPIO7_IO13, BUTTON_PAD_CTRL),
+
+	/* i2c1_isl1208 */
+#define GPIRQ_RTC_ISL1208	IMX_GPIO_NR(6, 7)
+	IOMUX_PAD_CTRL(NANDF_CLE__GPIO6_IO07, WEAK_PULLUP),
+
+	/* i2c1_isl29023 */
+#define GPIRQ_ISL29023		IMX_GPIO_NR(3, 29)
+	IOMUX_PAD_CTRL(EIM_D29__GPIO3_IO29, WEAK_PULLUP),
+
+	/* i2c1_SGTL5000 sys_mclk */
+	IOMUX_PAD_CTRL(GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
+
+	/* i2c2 ov5640 mipi Camera controls */
+#define GP_OV5640_MIPI_POWER_DOWN	IMX_GPIO_NR(6, 9)
+	IOMUX_PAD_CTRL(NANDF_WP_B__GPIO6_IO09, WEAK_PULLUP),
+#define GP_OV5640_MIPI_RESET		IMX_GPIO_NR(2, 5)
+	IOMUX_PAD_CTRL(NANDF_D5__GPIO2_IO05, WEAK_PULLDN),
+
+	/* i2c2 ov5642 Camera controls, J5 */
+	IOMUX_PAD_CTRL(GPIO_3__CCM_CLKO2, OUTPUT_40OHM),	/* mclk */
+#define GP_OV5642_POWER_DOWN	IMX_GPIO_NR(1, 6)
+	IOMUX_PAD_CTRL(GPIO_6__GPIO1_IO06, WEAK_PULLUP),
+#define GP_OV5642_RESET		IMX_GPIO_NR(1, 8)
+	IOMUX_PAD_CTRL(GPIO_8__GPIO1_IO08, WEAK_PULLDN),
+
+	/* PWM1 - Backlight on RGB connector: J15 */
+#define GP_BACKLIGHT_RGB	IMX_GPIO_NR(1, 21)
+	IOMUX_PAD_CTRL(SD1_DAT3__GPIO1_IO21, WEAK_PULLDN),
+
+	/* PWM4 - Backlight on LVDS connector: J6 */
+#define GP_BACKLIGHT_LVDS	IMX_GPIO_NR(1, 18)
+	IOMUX_PAD_CTRL(SD1_CMD__GPIO1_IO18, WEAK_PULLDN),
+
+	/* reg_usbotg_vbus */
+#define GP_REG_USBOTG		IMX_GPIO_NR(3, 22)
+	IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, WEAK_PULLDN),
+
+	/* reg_wlan_en */
+#define GP_REG_WLAN_EN		IMX_GPIO_NR(6, 15)
+	IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, WEAK_PULLDN),
+
+	/* UART2 */
+#ifndef CONFIG_SILENT_UART
+	IOMUX_PAD_CTRL(EIM_D26__UART2_TX_DATA, UART_PAD_CTRL),
+	IOMUX_PAD_CTRL(EIM_D27__UART2_RX_DATA, UART_PAD_CTRL),
+#else
+	IOMUX_PAD_CTRL(EIM_D26__GPIO3_IO26, UART_PAD_CTRL),
+	IOMUX_PAD_CTRL(EIM_D27__GPIO3_IO27, UART_PAD_CTRL),
+#endif
+
+	/* USBH1 */
+	IOMUX_PAD_CTRL(EIM_D30__USB_H1_OC, WEAK_PULLUP),
+#define GP_USB_HUB_RESET	IMX_GPIO_NR(7, 12)
+	IOMUX_PAD_CTRL(GPIO_17__GPIO7_IO12, WEAK_PULLDN),
+
+	/* USBOTG */
+	IOMUX_PAD_CTRL(GPIO_1__USB_OTG_ID, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(KEY_COL4__USB_OTG_OC, WEAK_PULLUP),
+
+	/* USDHC2 - TiWi wl1271 */
+	IOMUX_PAD_CTRL(SD2_CLK__SD2_CLK, USDHC2_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_CMD__SD2_CMD, USDHC2_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_DAT0__SD2_DATA0, USDHC2_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_DAT1__SD2_DATA1, USDHC2_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_DAT2__SD2_DATA2, USDHC2_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_DAT3__SD2_DATA3, USDHC2_PAD_CTRL),
+
+	/* USDHC3 - eMMC */
+	IOMUX_PAD_CTRL(SD3_CLK__SD3_CLK, USDHC3_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_CMD__SD3_CMD, USDHC3_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DAT0__SD3_DATA0, USDHC3_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DAT1__SD3_DATA1, USDHC3_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DAT2__SD3_DATA2, USDHC3_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DAT3__SD3_DATA3, USDHC3_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DAT4__SD3_DATA4, USDHC3_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DAT5__SD3_DATA5, USDHC3_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DAT6__SD3_DATA6, USDHC3_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DAT7__SD3_DATA7, USDHC3_PAD_CTRL),
+#define GP_EMMC_RESET	IMX_GPIO_NR(2, 23)
+	IOMUX_PAD_CTRL(EIM_CS0__GPIO2_IO23, WEAK_PULLUP),
+
+	/* USDHC4 - sdcard */
+	IOMUX_PAD_CTRL(SD4_CLK__SD4_CLK, USDHC4_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD4_CMD__SD4_CMD, USDHC4_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD4_DAT0__SD4_DATA0, USDHC4_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD4_DAT1__SD4_DATA1, USDHC4_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD4_DAT2__SD4_DATA2, USDHC4_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD4_DAT3__SD4_DATA3, USDHC4_PAD_CTRL),
+#define GP_USDHC4_CD		IMX_GPIO_NR(2, 6)
+	IOMUX_PAD_CTRL(NANDF_D6__GPIO2_IO06, WEAK_PULLUP),
+
+	/* wl1271 */
+#define GPIRQ_WL1271_WL		IMX_GPIO_NR(6, 14)
+	IOMUX_PAD_CTRL(NANDF_CS1__GPIO6_IO14, WEAK_PULLDN),
+};
+
+#ifdef CONFIG_CMD_FBPANEL
+static const iomux_v3_cfg_t rgb_pads[] = {
+	IOMUX_PAD_CTRL(DI0_DISP_CLK__IPU1_DI0_DISP_CLK, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DI0_PIN15__IPU1_DI0_PIN15, RGB_PAD_CTRL),	/* DRDY */
+	IOMUX_PAD_CTRL(DI0_PIN2__IPU1_DI0_PIN02, RGB_PAD_CTRL),		/* HSYNC */
+	IOMUX_PAD_CTRL(DI0_PIN3__IPU1_DI0_PIN03, RGB_PAD_CTRL),		/* VSYNC */
+	IOMUX_PAD_CTRL(DISP0_DAT0__IPU1_DISP0_DATA00, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT1__IPU1_DISP0_DATA01, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT2__IPU1_DISP0_DATA02, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT3__IPU1_DISP0_DATA03, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT4__IPU1_DISP0_DATA04, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT5__IPU1_DISP0_DATA05, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT6__IPU1_DISP0_DATA06, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT7__IPU1_DISP0_DATA07, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT8__IPU1_DISP0_DATA08, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT9__IPU1_DISP0_DATA09, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT10__IPU1_DISP0_DATA10, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT11__IPU1_DISP0_DATA11, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT12__IPU1_DISP0_DATA12, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT13__IPU1_DISP0_DATA13, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT14__IPU1_DISP0_DATA14, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT15__IPU1_DISP0_DATA15, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT16__IPU1_DISP0_DATA16, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT17__IPU1_DISP0_DATA17, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT18__IPU1_DISP0_DATA18, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT19__IPU1_DISP0_DATA19, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT20__IPU1_DISP0_DATA20, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT21__IPU1_DISP0_DATA21, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT22__IPU1_DISP0_DATA22, RGB_PAD_CTRL),
+	IOMUX_PAD_CTRL(DISP0_DAT23__IPU1_DISP0_DATA23, RGB_PAD_CTRL),
+};
+#endif
+
+static const iomux_v3_cfg_t rgb_gpio_pads[] = {
+	IOMUX_PAD_CTRL(DI0_DISP_CLK__GPIO4_IO16, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DI0_PIN15__GPIO4_IO17, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DI0_PIN2__GPIO4_IO18, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DI0_PIN3__GPIO4_IO19, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT0__GPIO4_IO21, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT1__GPIO4_IO22, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT2__GPIO4_IO23, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT3__GPIO4_IO24, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT4__GPIO4_IO25, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT5__GPIO4_IO26, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT6__GPIO4_IO27, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT7__GPIO4_IO28, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT8__GPIO4_IO29, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT9__GPIO4_IO30, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT10__GPIO4_IO31, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT11__GPIO5_IO05, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT12__GPIO5_IO06, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT13__GPIO5_IO07, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT14__GPIO5_IO08, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT15__GPIO5_IO09, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT16__GPIO5_IO10, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT17__GPIO5_IO11, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT18__GPIO5_IO12, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT19__GPIO5_IO13, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT20__GPIO5_IO14, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT21__GPIO5_IO15, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT22__GPIO5_IO16, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(DISP0_DAT23__GPIO5_IO17, WEAK_PULLUP),
+};
+
+static const struct i2c_pads_info i2c_pads[] = {
+	/* I2C1, SGTL5000 */
+	I2C_PADS_INFO_ENTRY(I2C1, EIM_D21, 3, 21, EIM_D28, 3, 28, I2C_PAD_CTRL),
+	/* I2C2 Camera, MIPI */
+	I2C_PADS_INFO_ENTRY(I2C2, KEY_COL3, 4, 12, KEY_ROW3, 4, 13, I2C_PAD_CTRL),
+	/* I2C3, J15 - RGB connector */
+	I2C_PADS_INFO_ENTRY(I2C3, GPIO_5, 1, 05, GPIO_16, 7, 11, I2C_PAD_CTRL),
+};
+#define I2C_BUS_CNT	3
+
+#ifdef CONFIG_USB_EHCI_MX6
+int board_ehci_hcd_init(int port)
+{
+	if (port) {
+		/* Reset USB hub */
+		gpio_set_value(GP_USB_HUB_RESET, 0);
+		mdelay(2);
+		gpio_set_value(GP_USB_HUB_RESET, 1);
+	}
+	return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+	if (port)
+		return 0;
+	gpio_set_value(GP_REG_USBOTG, on);
+	return 0;
+}
+
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg board_usdhc_cfg[] = {
+	{.esdhc_base = USDHC4_BASE_ADDR, .bus_width = 4,
+			.gp_cd = GP_USDHC4_CD},
+	{.esdhc_base = USDHC3_BASE_ADDR, .bus_width = 8,
+			.gp_reset = GP_EMMC_RESET},
+};
+#endif
+
+#ifdef CONFIG_MXC_SPI
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	if (bus == 0 && cs == 0)
+		return GP_ECSPI1_NOR_CS;
+	if (bus == 1 && cs == 0)
+		return GP_ECSPI2_CS;
+	if (cs >> 8)
+		return (cs >> 8);
+	return -1;
+}
+#endif
+
+#ifdef CONFIG_CMD_FBPANEL
+void board_enable_lvds(const struct display_info_t *di, int enable)
+{
+	gpio_direction_output(GP_BACKLIGHT_LVDS, enable);
+}
+
+void board_enable_lcd(const struct display_info_t *di, int enable)
+{
+	if (enable) {
+		SETUP_IOMUX_PADS(rgb_pads);
+#ifdef CONFIG_MXC_SPI_DISPLAY
+		if (di->fbflags & FBF_SPI)
+			enable_spi_rgb(di);
+#endif
+		mdelay(100); /* let panel sync up before enabling backlight */
+		gpio_direction_output(GP_BACKLIGHT_RGB, enable);
+	} else {
+		gpio_direction_output(GP_BACKLIGHT_RGB, enable);
+		SETUP_IOMUX_PADS(rgb_gpio_pads);
+	}
+}
+
+static const struct display_info_t displays[] = {
+	/* hdmi */
+	VD_1280_720M_60(HDMI, fbp_detect_i2c, 1, 0x50),
+	VD_1920_1080M_60(HDMI, NULL, 1, 0x50),
+	VD_1024_768M_60(HDMI, NULL, 1, 0x50),
+	VD_640_480M_60(HDMI, NULL, 1, 0x50),
+	VD_720_480M_60(HDMI, NULL, 1, 0x50),
+
+	/* ft5x06 */
+	VD_HANNSTAR7(LVDS, fbp_detect_i2c, 2, 0x38),
+	VD_AUO_B101EW05(LVDS, NULL, 2, 0x38),
+	VD_LG1280_800(LVDS, NULL, 2, 0x38),
+	VD_DT070BTFT(LVDS, NULL, 2, 0x38),
+	VD_WSVGA(LVDS, NULL, 2, 0x38),
+	VD_TM070JDHG30(LVDS, NULL, 2, 0x38),
+
+	/* ili210x */
+	VD_AMP1024_600(LVDS, fbp_detect_i2c, 2, 0x41),
+
+	/* egalax_ts */
+	VD_HANNSTAR(LVDS, fbp_detect_i2c, 2, 0x04),
+	VD_LG9_7(LVDS, NULL, 2, 0x04),
+
+	/* fusion7 specific touchscreen */
+	VD_FUSION7(LCD, fbp_detect_i2c, 2, 0x10),
+
+	VD_SHARP_LQ101K1LY04(LVDS, NULL, 0, 0x00),
+	VD_WXGA_J(LVDS, NULL, 0, 0x00),
+	VD_WXGA(LVDS, NULL, 0, 0x00),
+	VD_WVGA(LVDS, NULL, 0, 0x00),
+	VD_AA065VE11(LVDS, NULL, 0, 0x00),
+	VD_VGA(LVDS, NULL, 0, 0x00),
+
+	/* tsc2004 */
+	VD_CLAA_WVGA(LCD, fbp_detect_i2c, 2, 0x48),
+	VD_SHARP_WVGA(LCD, NULL, 2, 0x48),
+	VD_DC050WX(LCD, NULL, 2, 0x48),
+	VD_QVGA(LCD, NULL, 2, 0x48),
+	VD_AT035GT_07ET3(LCD, NULL, 2, 0x48),
+
+	VD_LSA40AT9001(LCD, NULL, 0, 0x00),
+#ifdef CONFIG_MXC_SPI_DISPLAY
+	VD_AUO_G050(LCD, NULL, 1, 0),
+	VD_A030JN01_UPS051(LCD, NULL, 1, 2),
+	VD_A030JN01_YUV720(LCD, NULL, 1, 1),
+#endif
+};
+#define display_cnt	ARRAY_SIZE(displays)
+#else
+#define displays	NULL
+#define display_cnt	0
+#endif
+
+static const unsigned short gpios_out_low[] = {
+	GP_BACKLIGHT_LVDS,
+	GP_BACKLIGHT_RGB,
+	/* Disable wl1271 */
+	GP_REG_WLAN_EN,
+	GP_BT_RFKILL_RESET,
+	GP_REG_USBOTG,
+	GP_OV5640_MIPI_RESET,
+	GP_OV5642_RESET,
+	GP_USB_HUB_RESET,
+	GP_EMMC_RESET,
+};
+
+static const unsigned short gpios_out_high[] = {
+	GP_ECSPI1_NOR_CS,
+	GP_OV5642_POWER_DOWN,
+	GP_OV5640_MIPI_POWER_DOWN,
+};
+
+static const unsigned short gpios_in[] = {
+	GP_GPIOKEY_BACK,
+	GP_GPIOKEY_HOME,
+	GP_GPIOKEY_MENU,
+	GP_GPIOKEY_POWER,
+	GP_GPIOKEY_VOL_DOWN,
+	GP_GPIOKEY_VOL_UP,
+	GPIRQ_RTC_ISL1208,
+	GPIRQ_ISL29023,
+	GPIRQ_WL1271_WL,
+	GP_USDHC4_CD,
+};
+
+int board_early_init_f(void)
+{
+	set_gpios_in(gpios_in, ARRAY_SIZE(gpios_in));
+	set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
+	set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
+	SETUP_IOMUX_PADS(init_pads);
+	SETUP_IOMUX_PADS(rgb_gpio_pads);
+	return 0;
+}
+
+int board_init(void)
+{
+	common_board_init(i2c_pads, I2C_BUS_CNT, IOMUXC_GPR1_OTG_ID_GPIO1,
+			displays, display_cnt, 0);
+	return 0;
+}
+
+const struct button_key board_buttons[] = {
+	{"back",	GP_GPIOKEY_BACK,	'B', 1},
+	{"home",	GP_GPIOKEY_HOME,	'H', 1},
+	{"menu",	GP_GPIOKEY_MENU,	'M', 1},
+	{"search",	GP_GPIOKEY_POWER,	'S', 1},
+	{"volup",	GP_GPIOKEY_VOL_UP,	'V', 1},
+	{"voldown",	GP_GPIOKEY_VOL_DOWN,	'v', 1},
+	{NULL, 0, 0, 0},
+};
+
+#ifdef CONFIG_CMD_BMODE
+const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"mmc0",	MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+	{"mmc1",	MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+	{NULL,		0},
+};
+#endif
diff --git a/board/boundary/jlm/jlm_1g.cfg b/board/boundary/jlm/jlm_1g.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..a82693797a83ff456d6e6472fdeff62476bbbeb6
--- /dev/null
+++ b/board/boundary/jlm/jlm_1g.cfg
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      spi
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* ? board sample */
+#define MX6_MMDC_P0_MPDGCTRL0_VAL	0x42720306
+#define MX6_MMDC_P0_MPDGCTRL1_VAL	0x026F0266
+#define MX6_MMDC_P1_MPDGCTRL0_VAL	0x4273030A
+#define MX6_MMDC_P1_MPDGCTRL1_VAL	0x02740240
+#define MX6_MMDC_P0_MPRDDLCTL_VAL	0x45393B3E
+#define MX6_MMDC_P1_MPRDDLCTL_VAL	0x403A3747
+#define MX6_MMDC_P0_MPWRDLCTL_VAL	0x40434541
+#define MX6_MMDC_P1_MPWRDLCTL_VAL	0x473E4A3B
+#define MX6_MMDC_P0_MPWLDECTRL0_VAL	0x0011000E
+#define MX6_MMDC_P0_MPWLDECTRL1_VAL	0x000E001B
+#define MX6_MMDC_P1_MPWLDECTRL0_VAL	0x00190015
+#define MX6_MMDC_P1_MPWLDECTRL1_VAL	0x00070018
+#define WALAT	0
+
+#include "../common/mx6/ddr-setup.cfg"
+#define RANK 0
+#define BUS_WIDTH 64
+/* H5TC2G63FFR-PBA */
+/* MT41K128M16JT-125 IT:K */
+#include "../common/mx6/1066mhz_128mx16.cfg"
+#include "../common/mx6/clocks.cfg"
diff --git a/board/boundary/jlm/jlm_2g.cfg b/board/boundary/jlm/jlm_2g.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..d5724de2f543793f68fe09f5c4bb9fa915058f90
--- /dev/null
+++ b/board/boundary/jlm/jlm_2g.cfg
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      spi
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* NC YET */
+#define MX6_MMDC_P0_MPDGCTRL0_VAL	0x42740304
+#define MX6_MMDC_P0_MPDGCTRL1_VAL	0x026e0265
+#define MX6_MMDC_P1_MPDGCTRL0_VAL	0x02750306
+#define MX6_MMDC_P1_MPDGCTRL1_VAL	0x02720244
+#define MX6_MMDC_P0_MPRDDLCTL_VAL	0x463d4041
+#define MX6_MMDC_P1_MPRDDLCTL_VAL	0x42413c47
+#define MX6_MMDC_P0_MPWRDLCTL_VAL	0x37414441
+#define MX6_MMDC_P1_MPWRDLCTL_VAL	0x4633473b
+#define MX6_MMDC_P0_MPWLDECTRL0_VAL	0x0025001f
+#define MX6_MMDC_P0_MPWLDECTRL1_VAL	0x00290027
+#define MX6_MMDC_P1_MPWLDECTRL0_VAL	0x001f002b
+#define MX6_MMDC_P1_MPWLDECTRL1_VAL	0x000f0029
+#define WALAT	1
+
+#include "../common/mx6/ddr-setup.cfg"
+#define RANK 0
+#define BUS_WIDTH 64
+/* D2516EC4BXGGB-U */
+/* D2516EC4BXGGBI-U */
+#include "../common/mx6/1066mhz_256mx16.cfg"
+#include "../common/mx6/clocks.cfg"
diff --git a/board/boundary/jlm/spi_display.c b/board/boundary/jlm/spi_display.c
new file mode 100644
index 0000000000000000000000000000000000000000..bd1be507acba5d0b0fd8e57230ebe21e62238653
--- /dev/null
+++ b/board/boundary/jlm/spi_display.c
@@ -0,0 +1,462 @@
+/*
+ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/spi.h>
+#include <asm/mach-imx/video.h>
+#include <spi.h>
+#include "spi_display.h"
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
+
+#define SPI_MOSI_R_PAD_CTRL	SPI_PAD_CTRL | PAD_CTL_ODE | PAD_CTL_PUS_22K_UP
+
+#define GP_SPI_DISPLAY_RESET	IMX_GPIO_NR(4, 20)
+
+static iomux_v3_cfg_t const spi_mosi_r_pads[] = {
+	IOMUX_PAD_CTRL(CSI0_DAT9__ECSPI2_MOSI, SPI_MOSI_R_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const spi_mosi_w_pads[] = {
+	IOMUX_PAD_CTRL(CSI0_DAT9__ECSPI2_MOSI, SPI_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const spi_ss0_pad[] = {
+	IOMUX_PAD_CTRL(CSI0_DAT11__ECSPI2_SS0, SPI_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const spi_ss0_gpio_pad[] = {
+#define GP_ECSPI2_CS		IMX_GPIO_NR(5, 29)
+	IOMUX_PAD_CTRL(CSI0_DAT11__GPIO5_IO29, SPI_PAD_CTRL),
+};
+
+static int AUO_G050_spi_write_rtn(struct spi_slave *spi, u8 *cmds)
+{
+	u8 buf[4];
+	int ret = 0;
+
+	debug("%s\n", __func__);
+	while (1) {
+		uint reg = (cmds[0] << 8) | cmds[1];
+		uint len = cmds[2];
+
+		if (!len && !reg)
+			break;
+		cmds += 3;
+		do {
+			buf[0] = 0x20;
+			buf[1] = reg >> 8;
+			ret = spi_xfer(spi, 2 * 8, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
+			if (ret) {
+				debug("%s: Failed to select reg1 0x%x, %d\n", __func__, reg, ret);
+				return ret;
+			}
+			udelay(2);
+			buf[0] = 0;
+			buf[1] = reg;
+			ret = spi_xfer(spi, 2 * 8, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
+			if (ret) {
+				debug("%s: Failed to select reg2 0x%x, %d\n", __func__, reg, ret);
+				return ret;
+			}
+			udelay(2);
+			if (!len) {
+				debug("spi: reg:%04x\n", reg);
+				break;
+			}
+			buf[0] = 0x40;
+			buf[1] = *cmds++;
+			ret = spi_xfer(spi, 2 * 8, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
+			if (ret) {
+				debug("%s: Failed to select reg3 0x%x, %d\n", __func__, reg, ret);
+				return ret;
+			}
+			debug("spi: reg:%04x %02x\n", reg, buf[1]);
+			udelay(2);
+			reg++;
+		} while (--len);
+	}
+	return ret;
+}
+
+static int AUO_G050_spi_read_rtn(struct spi_slave *spi, int reg)
+{
+	u8 buf[4];
+	u8 rbuf[4];
+	int ret = 0;
+
+	buf[0] = 0x20;
+	buf[1] = reg >> 8;
+	ret = spi_xfer(spi, 2 * 8, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
+	if (ret) {
+		debug("%s: Failed to select reg1 0x%x, %d\n", __func__, reg, ret);
+		return ret;
+	}
+	udelay(2);
+	buf[0] = 0;
+	buf[1] = reg;
+	ret = spi_xfer(spi, 2 * 8, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
+	if (ret) {
+		debug("%s: Failed to select reg2 0x%x, %d\n", __func__, reg, ret);
+		return ret;
+	}
+	udelay(2);
+	buf[0] = 0xC0;
+	buf[1] = 0xff;
+	ret = spi_xfer(spi, 2 * 8, buf, rbuf, SPI_XFER_BEGIN | SPI_XFER_END);
+	if (ret) {
+		debug("%s: Failed to select reg3 0x%x, %d\n", __func__, reg, ret);
+		return ret;
+	}
+	debug("spi: reg:0x%04x: %02x %02x\n", reg, rbuf[0], rbuf[1]);
+	udelay(2);
+	return rbuf[1];
+}
+
+#define A(reg, cnt) (reg >> 8), (reg & 0xff), cnt
+
+static u8 AUO_G050_display_init_cmds[] = {
+/* Display Mode Setting */
+	A(0xf000, 5), 0x55, 0xaa, 0x52, 0x08, 0x00,
+	A(0xb100, 2), 0x0c, 0x00,
+	A(0xbc00, 3), 0x05, 0x05, 0x05,
+	A(0xb700, 2), 0x22, 0x22,
+	A(0xb800, 4), 0x01, 0x03, 0x03, 0x03,
+	A(0xc803, 1), 0x96,
+	A(0xc805, 1), 0x96,
+	A(0xc807, 1), 0x96,
+	A(0xc809, 1), 0x96,
+	A(0xc80b, 1), 0x2a,
+	A(0xc80c, 1), 0x2a,
+	A(0xc80f, 1), 0x2a,
+	A(0xc810, 1), 0x2a,
+	A(0xf000, 5), 0x55, 0xaa, 0x52, 0x08, 0x01,
+	A(0xb900, 3), 0x34, 0x34, 0x34,
+	A(0xba00, 3), 0x14, 0x14, 0x14,
+	A(0xbe00, 2), 0x00, 0x8c,
+	A(0xb000, 3), 0x00, 0x00, 0x00,
+	A(0xb800, 3), 0x24, 0x24, 0x24,
+	A(0xbc00, 3), 0x00, 0x88, 0x01,
+	A(0xbd00, 3), 0x00, 0x88, 0x01,
+	A(0xd100, 52),  0x00, 0x00, 0x00, 0x10, 0x00, 0x31, 0x00, 0x5a, 0x00, 0x78, 0x00, 0x9b, 0x00, 0xbe, 0x00, 0xe6, 0x01, 0x04,
+			0x01, 0x36, 0x01, 0x59, 0x01, 0x90, 0x01, 0xbd, 0x01, 0xbe, 0x01, 0xe5, 0x02, 0x0d, 0x02, 0x29, 0x02, 0x44,
+			0x02, 0x5d, 0x02, 0xbc, 0x02, 0xe9, 0x03, 0x16, 0x03, 0x48, 0x03, 0xac, 0x03, 0xe8, 0x03, 0xff,
+	A(0xd200, 52),  0x00, 0x00, 0x00, 0x10, 0x00, 0x31, 0x00, 0x5a, 0x00, 0x78, 0x00, 0x9b, 0x00, 0xbe, 0x00, 0xe6, 0x01, 0x04,
+			0x01, 0x36, 0x01, 0x59, 0x01, 0x90, 0x01, 0xbd, 0x01, 0xbe, 0x01, 0xe5, 0x02, 0x0d, 0x02, 0x29, 0x02, 0x44,
+			0x02, 0x5d, 0x02, 0xbc, 0x02, 0xe9, 0x03, 0x16, 0x03, 0x48, 0x03, 0xac, 0x03, 0xe8, 0x03, 0xff,
+	A(0xd300, 52),  0x00, 0x00, 0x00, 0x10, 0x00, 0x31, 0x00, 0x5a, 0x00, 0x78, 0x00, 0x9b, 0x00, 0xbe, 0x00, 0xe6, 0x01, 0x04,
+			0x01, 0x36, 0x01, 0x59, 0x01, 0x90, 0x01, 0xbd, 0x01, 0xbe, 0x01, 0xe5, 0x02, 0x0d, 0x02, 0x29, 0x02, 0x44,
+			0x02, 0x5d, 0x02, 0xbc, 0x02, 0xe9, 0x03, 0x16, 0x03, 0x48, 0x03, 0xac, 0x03, 0xe8, 0x03, 0xff,
+	A(0xd400, 52),  0x00, 0x00, 0x00, 0x10, 0x00, 0x31, 0x00, 0x5a, 0x00, 0x78, 0x00, 0x9b, 0x00, 0xbe, 0x00, 0xe6, 0x01, 0x04,
+			0x01, 0x36, 0x01, 0x59, 0x01, 0x90, 0x01, 0xbd, 0x01, 0xbe, 0x01, 0xe5, 0x02, 0x0d, 0x02, 0x29, 0x02, 0x44,
+			0x02, 0x5d, 0x02, 0xbc, 0x02, 0xe9, 0x03, 0x16, 0x03, 0x48, 0x03, 0xac, 0x03, 0xe8, 0x03, 0xff,
+	A(0xd500, 52),  0x00, 0x00, 0x00, 0x10, 0x00, 0x31, 0x00, 0x5a, 0x00, 0x78, 0x00, 0x9b, 0x00, 0xbe, 0x00, 0xe6, 0x01, 0x04,
+			0x01, 0x36, 0x01, 0x59, 0x01, 0x90, 0x01, 0xbd, 0x01, 0xbe, 0x01, 0xe5, 0x02, 0x0d, 0x02, 0x29, 0x02, 0x44,
+			0x02, 0x5d, 0x02, 0xbc, 0x02, 0xe9, 0x03, 0x16, 0x03, 0x48, 0x03, 0xac, 0x03, 0xe8, 0x03, 0xff,
+	A(0xd600, 52),  0x00, 0x00, 0x00, 0x10, 0x00, 0x31, 0x00, 0x5a, 0x00, 0x78, 0x00, 0x9b, 0x00, 0xbe, 0x00, 0xe6, 0x01, 0x04,
+			0x01, 0x36, 0x01, 0x59, 0x01, 0x90, 0x01, 0xbd, 0x01, 0xbe, 0x01, 0xe5, 0x02, 0x0d, 0x02, 0x29, 0x02, 0x44,
+			0x02, 0x5d, 0x02, 0xbc, 0x02, 0xe9, 0x03, 0x16, 0x03, 0x48, 0x03, 0xac, 0x03, 0xe8, 0x03, 0xff,
+	A(0x1100, 0),	/* exit sleep mode, wait 120 ms */
+	A(0, 0)
+};
+
+static u8 AUO_G050_display_on_cmds[] = {
+	A(0x2900, 0),
+	A(0, 0)
+};
+
+/* *************************************************** */
+
+static int A030JN01_spi_write_rtn(struct spi_slave *spi, u8 *cmds)
+{
+	u8 buf[4];
+	int ret = 0;
+
+	while (1) {
+		uint reg = (cmds[0] << 8) | cmds[1];
+		uint len = cmds[2];
+
+		if (!len && !reg)
+			break;
+		cmds += 3;
+		do {
+			buf[0] = reg + (reg & 0x40);
+			buf[1] = *cmds++;
+			ret = spi_xfer(spi, 2 * 8, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END);
+			if (ret) {
+				debug("%s: Failed 0x%x, %d\n", __func__, reg, ret);
+				return ret;
+			}
+			debug("spi: reg:%02x %02x\n", reg, buf[1]);
+			udelay(2);
+			reg++;
+		} while (--len);
+	}
+	return ret;
+}
+
+static int A030JN01_spi_read_rtn(struct spi_slave *spi, int reg)
+{
+	u8 buf[4];
+	u8 rbuf[4];
+	int ret = 0;
+
+	buf[0] = (reg + (reg & 0x40)) | 0x40;
+	buf[1] = 0xff;
+	ret = spi_xfer(spi, 2 * 8, buf, rbuf, SPI_XFER_BEGIN | SPI_XFER_END);
+	if (ret) {
+		debug("%s: Failed 0x%x, %d\n", __func__, reg, ret);
+		return ret;
+	}
+	debug("spi: reg:0x%02x: %02x %02x\n", reg, rbuf[0], rbuf[1]);
+	return rbuf[1];
+}
+
+static u8 A030JN01_display_YUV720_init_cmds[] = {
+/* Display Mode Setting */
+	A(4, 2), 0x6b, 0x5f,
+	A(0, 0)
+};
+
+static u8 A030JN01_display_UPS051_init_cmds[] = {
+	A(5, 1), 0x5f,
+	A(0, 0)
+};
+
+static u8 A030JN01_display_on_cmds[] = {
+	A(0, 0)
+};
+
+struct spi_display_info {
+	int mode;
+	int speed_r;
+	int speed_w;
+	int reset_active_low;
+	u8 *init_cmds;
+	u8 *on_cmds;
+	int (*spi_write_rtn)(struct spi_slave *spi, u8 *cmds);
+	int (*spi_read_rtn)(struct spi_slave *spi, int reg);
+};
+
+struct spi_display_info spi_di[] = {
+	{ .mode = SPI_MODE_0, .speed_r = 10000, .speed_w = 1000000, .reset_active_low = 1,
+			.init_cmds = AUO_G050_display_init_cmds, .on_cmds = AUO_G050_display_on_cmds,
+			.spi_write_rtn = AUO_G050_spi_write_rtn, .spi_read_rtn = AUO_G050_spi_read_rtn},
+	{ .mode = SPI_MODE_3, .speed_r = 10000, .speed_w = 10000, .reset_active_low = 1,
+			.init_cmds = A030JN01_display_YUV720_init_cmds, .on_cmds = A030JN01_display_on_cmds,
+			.spi_write_rtn = A030JN01_spi_write_rtn, .spi_read_rtn = A030JN01_spi_read_rtn},
+	{ .mode = SPI_MODE_3, .speed_r = 10000, .speed_w = 10000, .reset_active_low = 1,
+			.init_cmds = A030JN01_display_UPS051_init_cmds, .on_cmds = A030JN01_display_on_cmds,
+			.spi_write_rtn = A030JN01_spi_write_rtn, .spi_read_rtn = A030JN01_spi_read_rtn},
+};
+
+const struct display_info_t *g_dev;
+
+/*
+ * Return 1 for successful detection of display
+ */
+int detect_spi(struct display_info_t const *dev)
+{
+	return 1;
+}
+
+static void init_spi(struct display_info_t const *dev)
+{
+	unsigned cs_gpio = GP_ECSPI2_CS;
+	unsigned reset_gpio = GP_SPI_DISPLAY_RESET;
+	struct spi_display_info *di = &spi_di[dev->addr];
+	int reset_val = di->reset_active_low ? 0 : 1;
+
+	debug("%s\n", __func__);
+	gpio_direction_output(cs_gpio, 1);
+	gpio_direction_output(reset_gpio, reset_val ^ 1);
+	gpio_direction_output(reset_gpio, reset_val);
+	udelay(200);
+	gpio_direction_output(reset_gpio, reset_val ^ 1);
+	mdelay(200);
+}
+
+void enable_spi_rgb(struct display_info_t const *dev)
+{
+	unsigned cs_gpio = GP_ECSPI2_CS;
+	struct spi_slave *spi;
+	int ret;
+	struct spi_display_info *di = &spi_di[dev->addr];
+
+	g_dev = dev;
+	init_spi(dev);
+	gpio_direction_output(cs_gpio, 1);
+	SETUP_IOMUX_PADS(spi_mosi_w_pads);
+
+	enable_spi_clk(1, dev->bus);
+
+	/* Setup spi_slave */
+	spi = spi_setup_slave(dev->bus, 0, di->speed_w, di->mode);
+	if (!spi) {
+		printf("%s: Failed to set up slave\n", __func__);
+		return;
+	}
+
+	/* Claim spi bus */
+	ret = spi_claim_bus(spi);
+	if (ret) {
+		debug("%s: Failed to claim SPI bus: %d\n", __func__, ret);
+		goto free_bus;
+	}
+
+	/*
+	 * Initialization sequence
+	 * 1. Display Mode Settings
+	 * 2. Power Settings
+	 * 3. Gamma Settings
+	 * 4. Sleep Out
+	 * 5. Wait >= 7 frame
+	 * 6. Display on
+	 */
+	SETUP_IOMUX_PADS(spi_ss0_pad);
+	ret = di->spi_write_rtn(spi, di->init_cmds);
+	if (ret) {
+		printf("%s: Failed to display_init_cmds %d\n", __func__, ret);
+		goto release_bus;
+	}
+	mdelay(200);
+	ret = di->spi_write_rtn(spi, di->on_cmds);
+	if (ret) {
+		printf("%s: Failed to display_on_cmds %d\n", __func__, ret);
+		goto release_bus;
+	}
+	ret = 1;
+	SETUP_IOMUX_PADS(spi_ss0_gpio_pad);
+
+	/* Release spi bus */
+release_bus:
+	spi_release_bus(spi);
+free_bus:
+	spi_free_slave(spi);
+	enable_spi_clk(0, dev->bus);
+	return;
+}
+
+static int do_spid(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned cs_gpio = GP_ECSPI2_CS;
+	struct spi_slave *spi;
+	int display_index = g_dev ? g_dev->addr : 0;
+	int bus = g_dev ? g_dev->bus : 1;
+	struct spi_display_info *di = &spi_di[display_index];
+	int ret = 0;
+	int arg = 2;
+	uint reg;
+	u8 buf[80];
+
+	if (argc < 2)
+		return 1;
+	gpio_direction_output(cs_gpio, 1);
+	SETUP_IOMUX_PADS(spi_mosi_w_pads);
+
+	enable_spi_clk(1, bus);
+
+	/* Setup spi_slave */
+	spi = spi_setup_slave(bus, 0, di->speed_w, di->mode);
+	if (!spi) {
+		printf("%s: Failed to set up slave\n", __func__);
+		return 1;
+	}
+
+	/* Claim spi bus */
+	ret = spi_claim_bus(spi);
+	if (ret) {
+		debug("%s: Failed to claim SPI bus: %d\n", __func__, ret);
+		goto free_bus;
+	}
+
+	if (argc > ARRAY_SIZE(buf) - 3)
+		argc = ARRAY_SIZE(buf) - 3;
+
+	reg = simple_strtoul(argv[1], NULL, 16);
+	buf[0] = reg >> 8;
+	buf[1] = reg;
+	buf[2] = argc - arg;
+	while (arg < argc) {
+		buf[arg + 1] = simple_strtoul(argv[arg], NULL, 16);
+		arg++;
+	}
+	arg++;
+	buf[arg++] = 0;
+	buf[arg++] = 0;
+	buf[arg++] = 0;
+	SETUP_IOMUX_PADS(spi_ss0_pad);
+	di->spi_write_rtn(spi, buf);
+	SETUP_IOMUX_PADS(spi_ss0_gpio_pad);
+	spi_release_bus(spi);
+free_bus:
+	spi_free_slave(spi);
+	enable_spi_clk(0, bus);
+	return ret ? 1 : 0;
+}
+
+U_BOOT_CMD(
+	spid, 70, 0, do_spid,
+	"write cmd, data to spi display",
+	"reg16 [byte]"
+);
+
+static int do_spidr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	unsigned cs_gpio = GP_ECSPI2_CS;
+	struct spi_slave *spi;
+	int display_index = g_dev ? g_dev->addr : 0;
+	int bus = g_dev ? g_dev->bus : 1;
+	struct spi_display_info *di = &spi_di[display_index];
+	int ret = 0;
+	uint reg;
+	int val;
+
+	if (argc != 2)
+		return CMD_RET_USAGE;
+	gpio_direction_output(cs_gpio, 1);
+	SETUP_IOMUX_PADS(spi_mosi_r_pads);
+
+	enable_spi_clk(1, bus);
+
+	/* Setup spi_slave */
+	spi = spi_setup_slave(bus, 0, di->speed_r, di->mode);
+	if (!spi) {
+		printf("%s: Failed to set up slave\n", __func__);
+		return 1;
+	}
+
+	/* Claim spi bus */
+	ret = spi_claim_bus(spi);
+	if (ret) {
+		debug("%s: Failed to claim SPI bus: %d\n", __func__, ret);
+		goto free_bus;
+	}
+
+	reg = simple_strtoul(argv[1], NULL, 16);
+	SETUP_IOMUX_PADS(spi_ss0_pad);
+	val = di->spi_read_rtn(spi, reg);
+	SETUP_IOMUX_PADS(spi_ss0_gpio_pad);
+	printf("spidr: reg:0x%x = 0x%x\n", reg, val);
+	spi_release_bus(spi);
+free_bus:
+	spi_free_slave(spi);
+	enable_spi_clk(0, bus);
+	return ret ? 1 : 0;
+}
+
+U_BOOT_CMD(
+	spidr, 70, 0, do_spidr,
+	"read spi display register",
+	"reg16"
+);
diff --git a/board/boundary/jlm/spi_display.h b/board/boundary/jlm/spi_display.h
new file mode 100644
index 0000000000000000000000000000000000000000..e59275d3f2cc16b030f729d1e3a1797917ca54c8
--- /dev/null
+++ b/board/boundary/jlm/spi_display.h
@@ -0,0 +1,2 @@
+int detect_spi(struct display_info_t const *dev);
+void enable_spi_rgb(struct display_info_t const *dev);
diff --git a/configs/jlm_1g_defconfig b/configs/jlm_1g_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..f06510281453b0b6acd791bcb5b0972011e00de0
--- /dev/null
+++ b/configs/jlm_1g_defconfig
@@ -0,0 +1,71 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_TARGET_JLM=y
+CONFIG_FEC_MAC_FUSE=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/jlm/jlm_1g.cfg,MX6Q,DDR_MB=1024,DEFCONFIG=\"jlm_1g\""
+CONFIG_BOOTDELAY=1
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SATA=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DWC_AHSATA=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12000000
+CONFIG_FASTBOOT_BUF_SIZE=0x26000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_FSL_ESDHC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_NETDEVICES=y
+CONFIG_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Boundary"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/configs/jlm_2g_defconfig b/configs/jlm_2g_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..7d43d2392b69f907b16448f685cb677df48c3ea4
--- /dev/null
+++ b/configs/jlm_2g_defconfig
@@ -0,0 +1,71 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_TARGET_JLM=y
+CONFIG_FEC_MAC_FUSE=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/jlm/jlm_2g.cfg,MX6Q,DDR_MB=2048,DEFCONFIG=\"jlm_2g\""
+CONFIG_BOOTDELAY=1
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SATA=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DWC_AHSATA=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12000000
+CONFIG_FASTBOOT_BUF_SIZE=0x26000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_FSL_ESDHC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_NETDEVICES=y
+CONFIG_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Boundary"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/jlm.h b/include/configs/jlm.h
new file mode 100644
index 0000000000000000000000000000000000000000..fe5c1db078cf69011ae6cf2120d26f4f7cdb6ef2
--- /dev/null
+++ b/include/configs/jlm.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Boundary Devices Nitrogen6X
+ * and Freescale i.MX6Q Sabre Lite boards.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+#define CONFIG_MACH_TYPE	3769
+
+#define CONFIG_MXC_SPI_DISPLAY
+
+
+#define CONFIG_IMX_HDMI
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define BD_I2C_MASK	7
+
+#include "boundary.h"
+#define CONFIG_EXTRA_ENV_SETTINGS BD_BOUNDARY_ENV_SETTINGS \
+
+#endif	       /* __CONFIG_H */