From 9c2f9b2da650907b928995350cc4e29480fb0f80 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Wed, 8 Jun 2016 18:02:32 +0900
Subject: [PATCH] ARM: uniphier: insert dsb barrier to ensure visibility of
store
I noticed secondary CPUs sometimes fail to wake up, and the root
cause is that the sev instruction wakes up slave CPUs before the
preceding the register write is observed by them.
The read-back of the accessed register does not guarantee the order.
In order to ensure the order between the register write and the sev
instruction, a dsb instruction should be executed prior to the sev.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
arch/arm/mach-uniphier/arm64/smp_kick_cpus.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
index 64412e0ecce..5971ad256b8 100644
--- a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
+++ b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c
@@ -21,11 +21,11 @@ void uniphier_smp_kick_all_cpus(void)
rom_boot_rsv0 = map_sysmem(UNIPHIER_SMPCTRL_ROM_RSV0, SZ_8);
writeq((u64)uniphier_secondary_startup, rom_boot_rsv0);
- readq(rom_boot_rsv0); /* relax */
unmap_sysmem(rom_boot_rsv0);
uniphier_smp_setup();
- asm("sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */
+ asm("dsb ishst\n" /* Ensure the write to ROM_RSV0 is visible */
+ "sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */
}
--
GitLab