From 9c22aec4102de0f0dc35e21772d9f21d4616c3d2 Mon Sep 17 00:00:00 2001 From: Jagan Teki <jagannadh.teki@gmail.com> Date: Thu, 28 Jun 2018 19:40:46 +0530 Subject: [PATCH] usb: sunxi: Use proper reg_mask for clock gate, reset Masking clock gate, reset register bits based on the probed controller is proper only due to the assumption that masking should start with 0 even thought the controller has separate PHY or shared between OTG. unfortunately these are fixed due to lack of separate clock, reset drivers. Say for example EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) so we need to start reg_mask 0 - 2. This patch calculated the mask, based on the register base so that we can get the proper bits to set with respect to probed controller. We even do this masking by using PHY index specifier from dt, but dev_read_addr_size is failing for 64-bit boards. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 9 +++++---- drivers/usb/host/ehci-sunxi.c | 8 ++++++-- drivers/usb/host/ohci-sunxi.c | 10 +++++++--- 3 files changed, 18 insertions(+), 9 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index ee648366c74..02ce73954db 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -63,10 +63,11 @@ #ifdef CONFIG_SUNXI_GEN_SUN6I #if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) #define SUNXI_USBPHY_BASE 0x01c19000 -#define SUNXI_USB0_BASE 0x01c1a000 -#define SUNXI_USB1_BASE 0x01c1b000 -#define SUNXI_USB2_BASE 0x01c1c000 -#define SUNXI_USB3_BASE 0x01c1d000 +#define SUNXI_USB0_BASE SUNXI_USBPHY_BASE +#define SUNXI_USB1_BASE 0x01c1a000 +#define SUNXI_USB2_BASE 0x01c1b000 +#define SUNXI_USB3_BASE 0x01c1c000 +#define SUNXI_USB4_BASE 0x01c1d000 #else #define SUNXI_USB0_BASE 0x01c19000 #define SUNXI_USB1_BASE 0x01c1a000 diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c index 97d06d59758..7a79931a979 100644 --- a/drivers/usb/host/ehci-sunxi.c +++ b/drivers/usb/host/ehci-sunxi.c @@ -17,8 +17,10 @@ #include <generic-phy.h> #ifdef CONFIG_SUNXI_GEN_SUN4I +#define BASE_DIST 0x8000 #define AHB_CLK_DIST 2 #else +#define BASE_DIST 0x1000 #define AHB_CLK_DIST 1 #endif @@ -47,6 +49,7 @@ static int ehci_usb_probe(struct udevice *dev) struct ehci_hccr *hccr = (struct ehci_hccr *)devfdt_get_addr(dev); struct ehci_hcor *hcor; int extra_ahb_gate_mask = 0; + u8 reg_mask = 0; int phys, ret; priv->cfg = (const struct ehci_sunxi_cfg *)dev_get_driver_data(dev); @@ -86,10 +89,11 @@ no_phy: * This should go away once we've moved to the driver model for * clocks resp. phys. */ + reg_mask = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST; priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0; extra_ahb_gate_mask = priv->cfg->extra_ahb_gate_mask; - priv->ahb_gate_mask <<= phys * AHB_CLK_DIST; - extra_ahb_gate_mask <<= phys * AHB_CLK_DIST; + priv->ahb_gate_mask <<= reg_mask * AHB_CLK_DIST; + extra_ahb_gate_mask <<= reg_mask * AHB_CLK_DIST; setbits_le32(&priv->ccm->ahb_gate0, priv->ahb_gate_mask | extra_ahb_gate_mask); diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c index db6f438275c..0ddbdbe4609 100644 --- a/drivers/usb/host/ohci-sunxi.c +++ b/drivers/usb/host/ohci-sunxi.c @@ -17,8 +17,10 @@ #include <generic-phy.h> #ifdef CONFIG_SUNXI_GEN_SUN4I +#define BASE_DIST 0x8000 #define AHB_CLK_DIST 2 #else +#define BASE_DIST 0x1000 #define AHB_CLK_DIST 1 #endif @@ -48,6 +50,7 @@ static int ohci_usb_probe(struct udevice *dev) struct ohci_sunxi_priv *priv = dev_get_priv(dev); struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev); int extra_ahb_gate_mask = 0; + u8 reg_mask = 0; int phys, ret; priv->cfg = (const struct ohci_sunxi_cfg *)dev_get_driver_data(dev); @@ -89,12 +92,13 @@ no_phy: * This should go away once we've moved to the driver model for * clocks resp. phys. */ + reg_mask = ((uintptr_t)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST; priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0; extra_ahb_gate_mask = priv->cfg->extra_ahb_gate_mask; priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK; - priv->ahb_gate_mask <<= phys * AHB_CLK_DIST; - extra_ahb_gate_mask <<= phys * AHB_CLK_DIST; - priv->usb_gate_mask <<= phys; + priv->ahb_gate_mask <<= reg_mask * AHB_CLK_DIST; + extra_ahb_gate_mask <<= reg_mask * AHB_CLK_DIST; + priv->usb_gate_mask <<= reg_mask; setbits_le32(&priv->ccm->ahb_gate0, priv->ahb_gate_mask | extra_ahb_gate_mask); -- GitLab