diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 672742351b2a3088d7a103784411a1bc9c561786..b62842f3dc816f54a40bcd5d9ecd38c3e941ea0e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -499,6 +499,7 @@ config TARGET_UDOO
config TARGET_WANDBOARD
bool "Support wandboard"
select CPU_V7
+ select SUPPORT_SPL
config TARGET_WARP
bool "Support WaRP"
@@ -524,6 +525,10 @@ config TARGET_ARISTAINETOS
bool "Support aristainetos"
select CPU_V7
+config TARGET_ARISTAINETOS2
+ bool "Support aristainetos2"
+ select CPU_V7
+
config TARGET_MX6QARM2
bool "Support mx6qarm2"
select CPU_V7
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 055f44e8e46c210f3bd94dba47c130185192d3be..ae9994530459f59877bec8a3da04f4e8ac47dd79 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -140,23 +140,34 @@ int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
#endif
#ifdef CONFIG_SYS_I2C_MXC
-/* i2c_num can be from 0 - 2 */
+/* i2c_num can be from 0 - 3 */
int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
{
u32 reg;
u32 mask;
- if (i2c_num > 2)
+ if (i2c_num > 3)
return -EINVAL;
-
- mask = MXC_CCM_CCGR_CG_MASK
- << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
- reg = __raw_readl(&imx_ccm->CCGR2);
- if (enable)
- reg |= mask;
- else
- reg &= ~mask;
- __raw_writel(reg, &imx_ccm->CCGR2);
+ if (i2c_num < 3) {
+ mask = MXC_CCM_CCGR_CG_MASK
+ << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
+ + (i2c_num << 1));
+ reg = __raw_readl(&imx_ccm->CCGR2);
+ if (enable)
+ reg |= mask;
+ else
+ reg &= ~mask;
+ __raw_writel(reg, &imx_ccm->CCGR2);
+ } else {
+ mask = MXC_CCM_CCGR_CG_MASK
+ << (MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET);
+ reg = __raw_readl(&imx_ccm->CCGR1);
+ if (enable)
+ reg |= mask;
+ else
+ reg &= ~mask;
+ __raw_writel(reg, &imx_ccm->CCGR1);
+ }
return 0;
}
#endif
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 5d5bd0f54652390db66d2d2ec9db78fbcf76749f..86c8354217d6fb5ab2b7a02d646d0c211fbee20f 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -521,7 +521,8 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
/* MR0 */
val = ((tcl - 1) << 4) | /* CAS */
(1 << 8) | /* DLL Reset */
- ((twr - 3) << 9); /* Write Recovery */
+ ((twr - 3) << 9) | /* Write Recovery */
+ (sysinfo->pd_fast_exit << 12); /* Precharge PD PLL on */
debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs));
mmdc0->mdscr = MR(val, 0, 3, cs);
/* ZQ calibration */
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 21ef9d05731c6bc870e9eee235fd0b419d664dc1..b21bd03a8aac99a50bbdf9b2be6f3b2fda4b9d60 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -83,6 +83,85 @@ u32 get_cpu_rev(void)
return (type << 12) | (reg + 0x10);
}
+/*
+ * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
+ * defines a 2-bit SPEED_GRADING
+ */
+#define OCOTP_CFG3_SPEED_SHIFT 16
+#define OCOTP_CFG3_SPEED_800MHZ 0
+#define OCOTP_CFG3_SPEED_850MHZ 1
+#define OCOTP_CFG3_SPEED_1GHZ 2
+#define OCOTP_CFG3_SPEED_1P2GHZ 3
+
+u32 get_cpu_speed_grade_hz(void)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[0];
+ struct fuse_bank0_regs *fuse =
+ (struct fuse_bank0_regs *)bank->fuse_regs;
+ uint32_t val;
+
+ val = readl(&fuse->cfg3);
+ val >>= OCOTP_CFG3_SPEED_SHIFT;
+ val &= 0x3;
+
+ switch (val) {
+ /* Valid for IMX6DQ */
+ case OCOTP_CFG3_SPEED_1P2GHZ:
+ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+ return 1200000000;
+ /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
+ case OCOTP_CFG3_SPEED_1GHZ:
+ return 996000000;
+ /* Valid for IMX6DQ */
+ case OCOTP_CFG3_SPEED_850MHZ:
+ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+ return 852000000;
+ /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
+ case OCOTP_CFG3_SPEED_800MHZ:
+ return 792000000;
+ }
+ return 0;
+}
+
+/*
+ * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
+ * defines a 2-bit Temperature Grade
+ *
+ * return temperature grade and min/max temperature in celcius
+ */
+#define OCOTP_MEM0_TEMP_SHIFT 6
+
+u32 get_cpu_temp_grade(int *minc, int *maxc)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[1];
+ struct fuse_bank1_regs *fuse =
+ (struct fuse_bank1_regs *)bank->fuse_regs;
+ uint32_t val;
+
+ val = readl(&fuse->mem0);
+ val >>= OCOTP_MEM0_TEMP_SHIFT;
+ val &= 0x3;
+
+ if (minc && maxc) {
+ if (val == TEMP_AUTOMOTIVE) {
+ *minc = -40;
+ *maxc = 125;
+ } else if (val == TEMP_INDUSTRIAL) {
+ *minc = -40;
+ *maxc = 105;
+ } else if (val == TEMP_EXTCOMMERCIAL) {
+ *minc = -20;
+ *maxc = 105;
+ } else {
+ *minc = 0;
+ *maxc = 95;
+ }
+ }
+ return val;
+}
+
#ifdef CONFIG_REVISION_TAG
u32 __weak get_board_rev(void)
{
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index 067d08f131ad084fc5375945e848b24477a3453c..275befd2f851d10b73500665c10f6906e9de6267 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -16,6 +16,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
+#include <imx_thermal.h>
#include <ipu_pixfmt.h>
#include <thermal.h>
#include <sata.h>
@@ -24,6 +25,7 @@
#include <fsl_esdhc.h>
#endif
+#if defined(CONFIG_DISPLAY_CPUINFO)
static u32 reset_cause = -1;
static char *get_reset_cause(void)
@@ -60,6 +62,7 @@ u32 get_imx_reset_cause(void)
{
return reset_cause;
}
+#endif
#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
#if defined(CONFIG_MX53)
@@ -142,32 +145,62 @@ const char *get_imx_type(u32 imxtype)
int print_cpuinfo(void)
{
- u32 cpurev;
+ u32 cpurev, max_freq;
#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
struct udevice *thermal_dev;
- int cpu_tmp, ret;
+ int cpu_tmp, minc, maxc, ret;
#endif
cpurev = get_cpu_rev();
+#if defined(CONFIG_MX6)
+ printf("CPU: Freescale i.MX%s rev%d.%d",
+ get_imx_type((cpurev & 0xFF000) >> 12),
+ (cpurev & 0x000F0) >> 4,
+ (cpurev & 0x0000F) >> 0);
+ max_freq = get_cpu_speed_grade_hz();
+ if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
+ printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
+ } else {
+ printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
+ mxc_get_clock(MXC_ARM_CLK) / 1000000);
+ }
+#else
printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
get_imx_type((cpurev & 0xFF000) >> 12),
(cpurev & 0x000F0) >> 4,
(cpurev & 0x0000F) >> 0,
mxc_get_clock(MXC_ARM_CLK) / 1000000);
+#endif
#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
+ puts("CPU: ");
+ switch (get_cpu_temp_grade(&minc, &maxc)) {
+ case TEMP_AUTOMOTIVE:
+ puts("Automotive temperature grade ");
+ break;
+ case TEMP_INDUSTRIAL:
+ puts("Industrial temperature grade ");
+ break;
+ case TEMP_EXTCOMMERCIAL:
+ puts("Extended Commercial temperature grade ");
+ break;
+ default:
+ puts("Commercial temperature grade ");
+ break;
+ }
+ printf("(%dC to %dC)", minc, maxc);
ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
if (!ret) {
ret = thermal_get_temp(thermal_dev, &cpu_tmp);
if (!ret)
- printf("CPU: Temperature %d C\n", cpu_tmp);
+ printf(" at %dC\n", cpu_tmp);
else
- printf("CPU: Temperature: invalid sensor data\n");
+ puts(" - invalid sensor data\n");
} else {
- printf("CPU: Temperature: Can't find sensor device\n");
+ puts(" - invalid sensor device\n");
}
#endif
diff --git a/arch/arm/imx-common/i2c-mxv7.c b/arch/arm/imx-common/i2c-mxv7.c
index f3a5c3f3262d56dbf9f7e749aa1d757d9d9bbd9b..ff72b1a1fc8101984ae50ea39a46a5dc342a04fe 100644
--- a/arch/arm/imx-common/i2c-mxv7.c
+++ b/arch/arm/imx-common/i2c-mxv7.c
@@ -67,9 +67,12 @@ static void * const i2c_bases[] = {
#ifdef I2C3_BASE_ADDR
(void *)I2C3_BASE_ADDR,
#endif
+#ifdef I2C4_BASE_ADDR
+ (void *)I2C4_BASE_ADDR,
+#endif
};
-/* i2c_index can be from 0 - 2 */
+/* i2c_index can be from 0 - 3 */
int setup_i2c(unsigned i2c_index, int speed, int slave_addr,
struct i2c_pads_info *p)
{
diff --git a/arch/arm/include/asm/arch-imx/imx-regs.h b/arch/arm/include/asm/arch-imx/imx-regs.h
index 4de0779d28bebff6017d4d40bb0303b34b7c03a2..93e336951cd36f2c920687a4e1979399c0e72e61 100644
--- a/arch/arm/include/asm/arch-imx/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx/imx-regs.h
@@ -42,7 +42,7 @@
#define IMX_MMC_BASE (0x14000 + IMX_IO_BASE)
#define IMX_ASP_BASE (0x15000 + IMX_IO_BASE)
#define IMX_BTA_BASE (0x16000 + IMX_IO_BASE)
-#define IMX_I2C_BASE (0x17000 + IMX_IO_BASE)
+#define I2C1_BASE_ADDR (0x17000 + IMX_IO_BASE)
#define IMX_SSI_BASE (0x18000 + IMX_IO_BASE)
#define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE)
#define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE)
diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h
index 3dffa4a396bf9df10224b481ad0edc440bceecf7..78c4e9b08867a00252e84c0d9185de31d614d3a7 100644
--- a/arch/arm/include/asm/arch-mx25/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx25/imx-regs.h
@@ -293,13 +293,13 @@ struct cspi_regs {
#define IMX_ETB_SLOT4_BASE (0x43F0C000)
#define IMX_ETB_SLOT5_BASE (0x43F10000)
#define IMX_ECT_CTIO_BASE (0x43F18000)
-#define IMX_I2C_BASE (0x43F80000)
-#define IMX_I2C3_BASE (0x43F84000)
+#define I2C1_BASE_ADDR (0x43F80000)
+#define I2C3_BASE_ADDR (0x43F84000)
#define IMX_CAN1_BASE (0x43F88000)
#define IMX_CAN2_BASE (0x43F8C000)
#define UART1_BASE (0x43F90000)
#define UART2_BASE (0x43F94000)
-#define IMX_I2C2_BASE (0x43F98000)
+#define I2C2_BASE_ADDR (0x43F98000)
#define IMX_OWIRE_BASE (0x43F9C000)
#define IMX_CSPI1_BASE (0x43FA4000)
#define IMX_KPP_BASE (0x43FA8000)
diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h
index 7402e31354cf4926646676c46169364ebc886624..baf1d29cc3ecefc2ce0831f53da8c39bf1fed813 100644
--- a/arch/arm/include/asm/arch-mx27/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx27/imx-regs.h
@@ -184,13 +184,13 @@ struct fuse_bank0_regs {
#define UART2_BASE (0x0b000 + IMX_IO_BASE)
#define UART3_BASE (0x0c000 + IMX_IO_BASE)
#define UART4_BASE (0x0d000 + IMX_IO_BASE)
-#define IMX_I2C1_BASE (0x12000 + IMX_IO_BASE)
+#define I2C1_BASE_ADDR (0x12000 + IMX_IO_BASE)
#define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE)
#define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE)
#define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE)
#define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE)
#define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE)
-#define IMX_I2C2_BASE (0x1D000 + IMX_IO_BASE)
+#define I2C2_BASE_ADDR (0x1D000 + IMX_IO_BASE)
#define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE)
#define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE)
#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE)
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 0592ce01714f492fa7f7893e8c638d9baf9619d4..887d04850f63f242948298dff167d41ad7b1c8be 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -592,6 +592,8 @@ struct mxc_ccm_reg {
#define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
#define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10
#define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
+#define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET 8
+#define MXC_CCM_CCGR1_I2C4_SERIAL_MASK (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET)
#define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12
#define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 9a4ad8b5591605bdfb497ca4543cec1c96dd21ec..0d38d450daa8a37d80dfa9490e5dd948797c7f4c 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -277,6 +277,7 @@
#define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
#define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
#define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000)
+#define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
@@ -640,6 +641,25 @@ struct fuse_bank0_regs {
u32 rsvd7[3];
};
+struct fuse_bank1_regs {
+ u32 mem0;
+ u32 rsvd0[3];
+ u32 mem1;
+ u32 rsvd1[3];
+ u32 mem2;
+ u32 rsvd2[3];
+ u32 mem3;
+ u32 rsvd3[3];
+ u32 mem4;
+ u32 rsvd4[3];
+ u32 ana0;
+ u32 rsvd5[3];
+ u32 ana1;
+ u32 rsvd6[3];
+ u32 ana2;
+ u32 rsvd7[3];
+};
+
#ifdef CONFIG_MX6SX
struct fuse_bank4_regs {
u32 sjc_resp_low;
diff --git a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h
index 7c6c1e844d98e7497dc7bd1b0b3189867e631058..5dd9a50fdfafd6e91332e5026cd62366f77306e7 100644
--- a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h
@@ -146,7 +146,7 @@ enum {
MX6_PAD_CSI_DATA00__CSI1_DATA_2 = IOMUX_PAD(0x0394, 0x004C, 0, 0x06A8, 0, 0),
MX6_PAD_CSI_DATA00__ESAI_TX_CLK = IOMUX_PAD(0x0394, 0x004C, 1, 0x078C, 1, 0),
MX6_PAD_CSI_DATA00__AUDMUX_AUD6_TXC = IOMUX_PAD(0x0394, 0x004C, 2, 0x0684, 1, 0),
- MX6_PAD_CSI_DATA00__I2C1_SCL = IOMUX_PAD(0x0394, 0x004C, 3, 0x07A8, 0, 0),
+ MX6_PAD_CSI_DATA00__I2C1_SCL = IOMUX_PAD(0x0394, 0x004C, IOMUX_CONFIG_SION | 3, 0x07A8, 0, 0),
MX6_PAD_CSI_DATA00__UART6_RI_B = IOMUX_PAD(0x0394, 0x004C, 4, 0x0000, 0, 0),
MX6_PAD_CSI_DATA00__GPIO1_IO_14 = IOMUX_PAD(0x0394, 0x004C, 5, 0x0000, 0, 0),
MX6_PAD_CSI_DATA00__WEIM_DATA_23 = IOMUX_PAD(0x0394, 0x004C, 6, 0x0000, 0, 0),
@@ -157,7 +157,7 @@ enum {
MX6_PAD_CSI_DATA01__CSI1_DATA_3 = IOMUX_PAD(0x0398, 0x0050, 0, 0x06AC, 0, 0),
MX6_PAD_CSI_DATA01__ESAI_TX_FS = IOMUX_PAD(0x0398, 0x0050, 1, 0x077C, 1, 0),
MX6_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS = IOMUX_PAD(0x0398, 0x0050, 2, 0x0688, 1, 0),
- MX6_PAD_CSI_DATA01__I2C1_SDA = IOMUX_PAD(0x0398, 0x0050, 3, 0x07AC, 0, 0),
+ MX6_PAD_CSI_DATA01__I2C1_SDA = IOMUX_PAD(0x0398, 0x0050, IOMUX_CONFIG_SION | 3, 0x07AC, 0, 0),
MX6_PAD_CSI_DATA01__UART6_DSR_B = IOMUX_PAD(0x0398, 0x0050, 4, 0x0000, 0, 0),
MX6_PAD_CSI_DATA01__GPIO1_IO_15 = IOMUX_PAD(0x0398, 0x0050, 5, 0x0000, 0, 0),
MX6_PAD_CSI_DATA01__WEIM_DATA_22 = IOMUX_PAD(0x0398, 0x0050, 6, 0x0000, 0, 0),
@@ -211,7 +211,7 @@ enum {
MX6_PAD_CSI_DATA06__CSI1_DATA_8 = IOMUX_PAD(0x03AC, 0x0064, 0, 0x06C0, 0, 0),
MX6_PAD_CSI_DATA06__ESAI_TX2_RX3 = IOMUX_PAD(0x03AC, 0x0064, 1, 0x0798, 1, 0),
- MX6_PAD_CSI_DATA06__I2C4_SCL = IOMUX_PAD(0x03AC, 0x0064, 2, 0x07C0, 2, 0),
+ MX6_PAD_CSI_DATA06__I2C4_SCL = IOMUX_PAD(0x03AC, 0x0064, IOMUX_CONFIG_SION | 2, 0x07C0, 2, 0),
MX6_PAD_CSI_DATA06__KPP_COL_7 = IOMUX_PAD(0x03AC, 0x0064, 3, 0x07D0, 0, 0),
MX6_PAD_CSI_DATA06__UART6_RTS_B = IOMUX_PAD(0x03AC, 0x0064, 4, 0x0854, 0, 0),
MX6_PAD_CSI_DATA06__GPIO1_IO_20 = IOMUX_PAD(0x03AC, 0x0064, 5, 0x0000, 0, 0),
@@ -222,7 +222,7 @@ enum {
MX6_PAD_CSI_DATA07__CSI1_DATA_9 = IOMUX_PAD(0x03B0, 0x0068, 0, 0x06C4, 0, 0),
MX6_PAD_CSI_DATA07__ESAI_TX3_RX2 = IOMUX_PAD(0x03B0, 0x0068, 1, 0x079C, 1, 0),
- MX6_PAD_CSI_DATA07__I2C4_SDA = IOMUX_PAD(0x03B0, 0x0068, 2, 0x07C4, 2, 0),
+ MX6_PAD_CSI_DATA07__I2C4_SDA = IOMUX_PAD(0x03B0, 0x0068, IOMUX_CONFIG_SION | 2, 0x07C4, 2, 0),
MX6_PAD_CSI_DATA07__KPP_ROW_7 = IOMUX_PAD(0x03B0, 0x0068, 3, 0x07DC, 0, 0),
MX6_PAD_CSI_DATA07__UART6_CTS_B = IOMUX_PAD(0x03B0, 0x0068, 4, 0x0854, 1, 0),
MX6_PAD_CSI_DATA07__GPIO1_IO_21 = IOMUX_PAD(0x03B0, 0x0068, 5, 0x0000, 0, 0),
@@ -361,7 +361,7 @@ enum {
MX6_PAD_ENET2_RX_CLK__ENET2_RX_CLK = IOMUX_PAD(0x03E4, 0x009C, 0, 0x0774, 0, 0),
MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M = IOMUX_PAD(0x03E4, 0x009C, 1, 0x0000, 0, 0),
- MX6_PAD_ENET2_RX_CLK__I2C3_SCL = IOMUX_PAD(0x03E4, 0x009C, 2, 0x07B8, 1, 0),
+ MX6_PAD_ENET2_RX_CLK__I2C3_SCL = IOMUX_PAD(0x03E4, 0x009C, IOMUX_CONFIG_SION | 2, 0x07B8, 1, 0),
MX6_PAD_ENET2_RX_CLK__UART1_RTS_B = IOMUX_PAD(0x03E4, 0x009C, 3, 0x082C, 2, 0),
MX6_PAD_ENET2_RX_CLK__MLB_DATA = IOMUX_PAD(0x03E4, 0x009C, 4, 0x07EC, 1, 0),
MX6_PAD_ENET2_RX_CLK__GPIO2_IO_8 = IOMUX_PAD(0x03E4, 0x009C, 5, 0x0000, 0, 0),
@@ -372,7 +372,7 @@ enum {
MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK = IOMUX_PAD(0x03E8, 0x00A0, 0, 0x0000, 0, 0),
MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 = IOMUX_PAD(0x03E8, 0x00A0, 1, 0x076C, 1, 0),
- MX6_PAD_ENET2_TX_CLK__I2C3_SDA = IOMUX_PAD(0x03E8, 0x00A0, 2, 0x07BC, 1, 0),
+ MX6_PAD_ENET2_TX_CLK__I2C3_SDA = IOMUX_PAD(0x03E8, 0x00A0, IOMUX_CONFIG_SION | 2, 0x07BC, 1, 0),
MX6_PAD_ENET2_TX_CLK__UART1_CTS_B = IOMUX_PAD(0x03E8, 0x00A0, 3, 0x082C, 3, 0),
MX6_PAD_ENET2_TX_CLK__MLB_CLK = IOMUX_PAD(0x03E8, 0x00A0, 4, 0x07E8, 1, 0),
MX6_PAD_ENET2_TX_CLK__GPIO2_IO_9 = IOMUX_PAD(0x03E8, 0x00A0, 5, 0x0000, 0, 0),
@@ -420,7 +420,7 @@ enum {
MX6_PAD_KEY_COL4__KPP_COL_4 = IOMUX_PAD(0x03FC, 0x00B4, 0, 0x0000, 0, 0),
MX6_PAD_KEY_COL4__ENET2_MDC = IOMUX_PAD(0x03FC, 0x00B4, 1, 0x0000, 0, 0),
- MX6_PAD_KEY_COL4__I2C3_SCL = IOMUX_PAD(0x03FC, 0x00B4, 2, 0x07B8, 2, 0),
+ MX6_PAD_KEY_COL4__I2C3_SCL = IOMUX_PAD(0x03FC, 0x00B4, IOMUX_CONFIG_SION | 2, 0x07B8, 2, 0),
MX6_PAD_KEY_COL4__USDHC2_LCTL = IOMUX_PAD(0x03FC, 0x00B4, 3, 0x0000, 0, 0),
MX6_PAD_KEY_COL4__AUDMUX_AUD5_RXC = IOMUX_PAD(0x03FC, 0x00B4, 4, 0x0664, 0, 0),
MX6_PAD_KEY_COL4__GPIO2_IO_14 = IOMUX_PAD(0x03FC, 0x00B4, 5, 0x0000, 0, 0),
@@ -467,7 +467,7 @@ enum {
MX6_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x0410, 0x00C8, 0, 0x0000, 0, 0),
MX6_PAD_KEY_ROW4__ENET2_MDIO = IOMUX_PAD(0x0410, 0x00C8, 1, 0x0770, 3, 0),
- MX6_PAD_KEY_ROW4__I2C3_SDA = IOMUX_PAD(0x0410, 0x00C8, 2, 0x07BC, 2, 0),
+ MX6_PAD_KEY_ROW4__I2C3_SDA = IOMUX_PAD(0x0410, 0x00C8, IOMUX_CONFIG_SION | 2, 0x07BC, 2, 0),
MX6_PAD_KEY_ROW4__USDHC1_LCTL = IOMUX_PAD(0x0410, 0x00C8, 3, 0x0000, 0, 0),
MX6_PAD_KEY_ROW4__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x0410, 0x00C8, 4, 0x0668, 0, 0),
MX6_PAD_KEY_ROW4__GPIO2_IO_19 = IOMUX_PAD(0x0410, 0x00C8, 5, 0x0000, 0, 0),
@@ -780,7 +780,7 @@ enum {
MX6_PAD_LCD1_VSYNC__MMDC_DEBUG_3 = IOMUX_PAD(0x0484, 0x013C, 9, 0x0000, 0, 0),
MX6_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x0488, 0x0140, 0, 0x0000, 0, 0),
- MX6_PAD_NAND_ALE__I2C3_SDA = IOMUX_PAD(0x0488, 0x0140, 1, 0x07BC, 0, 0),
+ MX6_PAD_NAND_ALE__I2C3_SDA = IOMUX_PAD(0x0488, 0x0140, IOMUX_CONFIG_SION | 1, 0x07BC, 0, 0),
MX6_PAD_NAND_ALE__QSPI2_A_SS0_B = IOMUX_PAD(0x0488, 0x0140, 2, 0x0000, 0, 0),
MX6_PAD_NAND_ALE__ECSPI2_SS0 = IOMUX_PAD(0x0488, 0x0140, 3, 0x072C, 0, 0),
MX6_PAD_NAND_ALE__ESAI_TX3_RX2 = IOMUX_PAD(0x0488, 0x0140, 4, 0x079C, 0, 0),
@@ -813,7 +813,7 @@ enum {
MX6_PAD_NAND_CE1_B__SDMA_DEBUG_PC_8 = IOMUX_PAD(0x0490, 0x0148, 9, 0x0000, 0, 0),
MX6_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0494, 0x014C, 0, 0x0000, 0, 0),
- MX6_PAD_NAND_CLE__I2C3_SCL = IOMUX_PAD(0x0494, 0x014C, 1, 0x07B8, 0, 0),
+ MX6_PAD_NAND_CLE__I2C3_SCL = IOMUX_PAD(0x0494, 0x014C, IOMUX_CONFIG_SION | 1, 0x07B8, 0, 0),
MX6_PAD_NAND_CLE__QSPI2_A_SCLK = IOMUX_PAD(0x0494, 0x014C, 2, 0x0000, 0, 0),
MX6_PAD_NAND_CLE__ECSPI2_SCLK = IOMUX_PAD(0x0494, 0x014C, 3, 0x0720, 0, 0),
MX6_PAD_NAND_CLE__ESAI_TX2_RX3 = IOMUX_PAD(0x0494, 0x014C, 4, 0x0798, 0, 0),
@@ -1054,7 +1054,7 @@ enum {
MX6_PAD_QSPI1B_DATA1__SIM_M_HADDR_8 = IOMUX_PAD(0x04EC, 0x01A4, 7, 0x0000, 0, 0),
MX6_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 = IOMUX_PAD(0x04F0, 0x01A8, 0, 0x0000, 0, 0),
- MX6_PAD_QSPI1B_DATA2__I2C2_SDA = IOMUX_PAD(0x04F0, 0x01A8, 1, 0x07B4, 2, 0),
+ MX6_PAD_QSPI1B_DATA2__I2C2_SDA = IOMUX_PAD(0x04F0, 0x01A8, IOMUX_CONFIG_SION | 1, 0x07B4, 2, 0),
MX6_PAD_QSPI1B_DATA2__ECSPI5_RDY = IOMUX_PAD(0x04F0, 0x01A8, 2, 0x0000, 0, 0),
MX6_PAD_QSPI1B_DATA2__ESAI_TX5_RX0 = IOMUX_PAD(0x04F0, 0x01A8, 3, 0x07A4, 2, 0),
MX6_PAD_QSPI1B_DATA2__CSI1_DATA_20 = IOMUX_PAD(0x04F0, 0x01A8, 4, 0x06EC, 1, 0),
@@ -1063,7 +1063,7 @@ enum {
MX6_PAD_QSPI1B_DATA2__SIM_M_HADDR_5 = IOMUX_PAD(0x04F0, 0x01A8, 7, 0x0000, 0, 0),
MX6_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 = IOMUX_PAD(0x04F4, 0x01AC, 0, 0x0000, 0, 0),
- MX6_PAD_QSPI1B_DATA3__I2C2_SCL = IOMUX_PAD(0x04F4, 0x01AC, 1, 0x07B0, 2, 0),
+ MX6_PAD_QSPI1B_DATA3__I2C2_SCL = IOMUX_PAD(0x04F4, 0x01AC, IOMUX_CONFIG_SION | 1, 0x07B0, 2, 0),
MX6_PAD_QSPI1B_DATA3__ECSPI5_SS3 = IOMUX_PAD(0x04F4, 0x01AC, 2, 0x0000, 0, 0),
MX6_PAD_QSPI1B_DATA3__ESAI_TX_FS = IOMUX_PAD(0x04F4, 0x01AC, 3, 0x077C, 2, 0),
MX6_PAD_QSPI1B_DATA3__CSI1_DATA_19 = IOMUX_PAD(0x04F4, 0x01AC, 4, 0x06E8, 1, 0),
@@ -1389,7 +1389,7 @@ enum {
MX6_PAD_SD2_DATA0__AUDMUX_AUD6_RXD = IOMUX_PAD(0x0588, 0x0240, 1, 0x0674, 2, 0),
MX6_PAD_SD2_DATA0__KPP_ROW_7 = IOMUX_PAD(0x0588, 0x0240, 2, 0x07DC, 1, 0),
MX6_PAD_SD2_DATA0__PWM1_OUT = IOMUX_PAD(0x0588, 0x0240, 3, 0x0000, 0, 0),
- MX6_PAD_SD2_DATA0__I2C4_SDA = IOMUX_PAD(0x0588, 0x0240, 4, 0x07C4, 3, 0),
+ MX6_PAD_SD2_DATA0__I2C4_SDA = IOMUX_PAD(0x0588, 0x0240, IOMUX_CONFIG_SION | 4, 0x07C4, 3, 0),
MX6_PAD_SD2_DATA0__GPIO6_IO_8 = IOMUX_PAD(0x0588, 0x0240, 5, 0x0000, 0, 0),
MX6_PAD_SD2_DATA0__ECSPI4_SS3 = IOMUX_PAD(0x0588, 0x0240, 6, 0x0000, 0, 0),
MX6_PAD_SD2_DATA0__UART4_RX = IOMUX_PAD(0x0588, 0x0240, 7, 0x0848, 4, 0),
@@ -1400,7 +1400,7 @@ enum {
MX6_PAD_SD2_DATA1__AUDMUX_AUD6_TXC = IOMUX_PAD(0x058C, 0x0244, 1, 0x0684, 2, 0),
MX6_PAD_SD2_DATA1__KPP_COL_7 = IOMUX_PAD(0x058C, 0x0244, 2, 0x07D0, 1, 0),
MX6_PAD_SD2_DATA1__PWM2_OUT = IOMUX_PAD(0x058C, 0x0244, 3, 0x0000, 0, 0),
- MX6_PAD_SD2_DATA1__I2C4_SCL = IOMUX_PAD(0x058C, 0x0244, 4, 0x07C0, 3, 0),
+ MX6_PAD_SD2_DATA1__I2C4_SCL = IOMUX_PAD(0x058C, 0x0244, IOMUX_CONFIG_SION | 4, 0x07C0, 3, 0),
MX6_PAD_SD2_DATA1__GPIO6_IO_9 = IOMUX_PAD(0x058C, 0x0244, 5, 0x0000, 0, 0),
MX6_PAD_SD2_DATA1__ECSPI4_SS2 = IOMUX_PAD(0x058C, 0x0244, 6, 0x0000, 0, 0),
MX6_PAD_SD2_DATA1__UART4_TX = IOMUX_PAD(0x058C, 0x0244, 7, 0x0848, 5, 0),
@@ -1450,7 +1450,7 @@ enum {
MX6_PAD_SD3_CMD__SDMA_DEBUG_EVENT_CHANNEL_4 = IOMUX_PAD(0x059C, 0x0254, 9, 0x0000, 0, 0),
MX6_PAD_SD3_DATA0__USDHC3_DATA0 = IOMUX_PAD(0x05A0, 0x0258, 0, 0x0000, 0, 0),
- MX6_PAD_SD3_DATA0__I2C4_SCL = IOMUX_PAD(0x05A0, 0x0258, 1, 0x07C0, 0, 0),
+ MX6_PAD_SD3_DATA0__I2C4_SCL = IOMUX_PAD(0x05A0, 0x0258, IOMUX_CONFIG_SION | 1, 0x07C0, 0, 0),
MX6_PAD_SD3_DATA0__ECSPI2_SS1 = IOMUX_PAD(0x05A0, 0x0258, 2, 0x0000, 0, 0),
MX6_PAD_SD3_DATA0__AUDMUX_AUD6_RXD = IOMUX_PAD(0x05A0, 0x0258, 3, 0x0674, 0, 0),
MX6_PAD_SD3_DATA0__LCDIF2_DATA_1 = IOMUX_PAD(0x05A0, 0x0258, 4, 0x0000, 0, 0),
@@ -1461,7 +1461,7 @@ enum {
MX6_PAD_SD3_DATA0__SDMA_DEBUG_EVT_CHN_LINES_0 = IOMUX_PAD(0x05A0, 0x0258, 9, 0x0000, 0, 0),
MX6_PAD_SD3_DATA1__USDHC3_DATA1 = IOMUX_PAD(0x05A4, 0x025C, 0, 0x0000, 0, 0),
- MX6_PAD_SD3_DATA1__I2C4_SDA = IOMUX_PAD(0x05A4, 0x025C, 1, 0x07C4, 0, 0),
+ MX6_PAD_SD3_DATA1__I2C4_SDA = IOMUX_PAD(0x05A4, 0x025C, IOMUX_CONFIG_SION | 1, 0x07C4, 0, 0),
MX6_PAD_SD3_DATA1__ECSPI2_SS2 = IOMUX_PAD(0x05A4, 0x025C, 2, 0x0000, 0, 0),
MX6_PAD_SD3_DATA1__AUDMUX_AUD6_TXC = IOMUX_PAD(0x05A4, 0x025C, 3, 0x0684, 0, 0),
MX6_PAD_SD3_DATA1__LCDIF2_DATA_0 = IOMUX_PAD(0x05A4, 0x025C, 4, 0x0000, 0, 0),
@@ -1583,7 +1583,7 @@ enum {
MX6_PAD_SD4_DATA2__USDHC4_DATA2 = IOMUX_PAD(0x05D0, 0x0288, 0, 0x0000, 0, 0),
MX6_PAD_SD4_DATA2__RAWNAND_DATA12 = IOMUX_PAD(0x05D0, 0x0288, 1, 0x0000, 0, 0),
- MX6_PAD_SD4_DATA2__I2C2_SDA = IOMUX_PAD(0x05D0, 0x0288, 2, 0x07B4, 0, 0),
+ MX6_PAD_SD4_DATA2__I2C2_SDA = IOMUX_PAD(0x05D0, 0x0288, IOMUX_CONFIG_SION | 2, 0x07B4, 0, 0),
MX6_PAD_SD4_DATA2__AUDMUX_AUD3_TXFS = IOMUX_PAD(0x05D0, 0x0288, 3, 0x0640, 0, 0),
MX6_PAD_SD4_DATA2__LCDIF2_DATA_10 = IOMUX_PAD(0x05D0, 0x0288, 4, 0x0000, 0, 0),
MX6_PAD_SD4_DATA2__GPIO6_IO_16 = IOMUX_PAD(0x05D0, 0x0288, 5, 0x0000, 0, 0),
@@ -1594,7 +1594,7 @@ enum {
MX6_PAD_SD4_DATA3__USDHC4_DATA3 = IOMUX_PAD(0x05D4, 0x028C, 0, 0x0000, 0, 0),
MX6_PAD_SD4_DATA3__RAWNAND_DATA13 = IOMUX_PAD(0x05D4, 0x028C, 1, 0x0000, 0, 0),
- MX6_PAD_SD4_DATA3__I2C2_SCL = IOMUX_PAD(0x05D4, 0x028C, 2, 0x07B0, 0, 0),
+ MX6_PAD_SD4_DATA3__I2C2_SCL = IOMUX_PAD(0x05D4, 0x028C, IOMUX_CONFIG_SION | 2, 0x07B0, 0, 0),
MX6_PAD_SD4_DATA3__AUDMUX_AUD3_TXD = IOMUX_PAD(0x05D4, 0x028C, 3, 0x0630, 0, 0),
MX6_PAD_SD4_DATA3__LCDIF2_DATA_9 = IOMUX_PAD(0x05D4, 0x028C, 4, 0x0000, 0, 0),
MX6_PAD_SD4_DATA3__GPIO6_IO_17 = IOMUX_PAD(0x05D4, 0x028C, 5, 0x0000, 0, 0),
@@ -1661,14 +1661,14 @@ enum {
MX6_PAD_USB_H_DATA__USB_H_DATA = IOMUX_PAD(0x05EC, 0x02A4, 0, 0x0000, 0, 0),
MX6_PAD_USB_H_DATA__PWM2_OUT = IOMUX_PAD(0x05EC, 0x02A4, 1, 0x0000, 0, 0),
MX6_PAD_USB_H_DATA__ANATOP_24M_OUT = IOMUX_PAD(0x05EC, 0x02A4, 2, 0x0000, 0, 0),
- MX6_PAD_USB_H_DATA__I2C4_SDA = IOMUX_PAD(0x05EC, 0x02A4, 3, 0x07C4, 1, 0),
+ MX6_PAD_USB_H_DATA__I2C4_SDA = IOMUX_PAD(0x05EC, 0x02A4, IOMUX_CONFIG_SION | 3, 0x07C4, 1, 0),
MX6_PAD_USB_H_DATA__WDOG3_WDOG_B = IOMUX_PAD(0x05EC, 0x02A4, 4, 0x0000, 0, 0),
MX6_PAD_USB_H_DATA__GPIO7_IO_10 = IOMUX_PAD(0x05EC, 0x02A4, 5, 0x0000, 0, 0),
MX6_PAD_USB_H_STROBE__USB_H_STROBE = IOMUX_PAD(0x05F0, 0x02A8, 0, 0x0000, 0, 0),
MX6_PAD_USB_H_STROBE__PWM1_OUT = IOMUX_PAD(0x05F0, 0x02A8, 1, 0x0000, 0, 0),
MX6_PAD_USB_H_STROBE__ANATOP_32K_OUT = IOMUX_PAD(0x05F0, 0x02A8, 2, 0x0000, 0, 0),
- MX6_PAD_USB_H_STROBE__I2C4_SCL = IOMUX_PAD(0x05F0, 0x02A8, 3, 0x07C0, 1, 0),
+ MX6_PAD_USB_H_STROBE__I2C4_SCL = IOMUX_PAD(0x05F0, 0x02A8, IOMUX_CONFIG_SION | 3, 0x07C0, 1, 0),
MX6_PAD_USB_H_STROBE__WDOG3_WDOG_RST_B_DEB = IOMUX_PAD(0x05F0, 0x02A8, 4, 0x0000, 0, 0),
MX6_PAD_USB_H_STROBE__GPIO7_IO_11 = IOMUX_PAD(0x05F0, 0x02A8, 5, 0x0000, 0, 0),
};
diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h
index 28ba84415f05b667d24dd329f1a1953189e67a53..c5832912b4221f21ce9e958d15040a2dc9490f5a 100644
--- a/arch/arm/include/asm/arch-mx6/sys_proto.h
+++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
@@ -16,6 +16,8 @@
u32 get_nr_cpus(void);
u32 get_cpu_rev(void);
+u32 get_cpu_speed_grade_hz(void);
+u32 get_cpu_temp_grade(int *minc, int *maxc);
/* returns MXC_CPU_ value */
#define cpu_type(rev) (((rev) >> 12)&0xff)
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index a7d765af359d168a22f7c62cb38890c4a848b980..202198133cfbc560cdaf6e6ba46d54fc71ff2534 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -74,7 +74,7 @@
#define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000)
#define ESAI_FIFO_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000)
#define WDOG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00065000)
-#define I2C0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00066000)
+#define I2C1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00066000)
#define WKUP_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006A000)
#define CCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006B000)
#define GPC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000)
diff --git a/arch/arm/include/asm/imx-common/dma.h b/arch/arm/include/asm/imx-common/dma.h
index d5c1f7f255a3c5f6eee70634d6dd747ac5639530..7d421b3967cfb8295abfa4cb84d8f0d048879a5f 100644
--- a/arch/arm/include/asm/imx-common/dma.h
+++ b/arch/arm/include/asm/imx-common/dma.h
@@ -22,7 +22,7 @@
#define DMA_PIO_WORDS CONFIG_ARCH_DMA_PIO_WORDS
#endif
-#define MXS_DMA_ALIGNMENT 32
+#define MXS_DMA_ALIGNMENT ARCH_DMA_MINALIGN
/*
* MXS DMA channels
diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig
index b8e380eb8487c6e5bbc57290bb55f9101ef89a82..500b665cb95a6feae18656ec30275c5b14cd7de5 100644
--- a/board/aristainetos/Kconfig
+++ b/board/aristainetos/Kconfig
@@ -10,3 +10,16 @@ config SYS_CONFIG_NAME
default "aristainetos"
endif
+
+if TARGET_ARISTAINETOS2
+
+config SYS_BOARD
+ default "aristainetos"
+
+config SYS_SOC
+ default "mx6"
+
+config SYS_CONFIG_NAME
+ default "aristainetos2"
+
+endif
diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS
index d45d4236c629607b1f8fd4f4f204375793088b0f..78c9b693e1c5ec14a36b16dfde5a510686b5c4bd 100644
--- a/board/aristainetos/MAINTAINERS
+++ b/board/aristainetos/MAINTAINERS
@@ -4,3 +4,5 @@ S: Maintained
F: board/aristainetos/
F: include/configs/aristainetos.h
F: configs/aristainetos_defconfig
+F: include/configs/aristainetos2.h
+F: configs/aristainetos2_defconfig
diff --git a/board/aristainetos/aristainetos-v1.c b/board/aristainetos/aristainetos-v1.c
new file mode 100644
index 0000000000000000000000000000000000000000..d6a761430d9a6a68ecf0e4d9482ca248ecd268c8
--- /dev/null
+++ b/board/aristainetos/aristainetos-v1.c
@@ -0,0 +1,279 @@
+/*
+ * (C) Copyright 2015
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/video.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <pwm.h>
+
+struct i2c_pads_info i2c_pad_info3 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
+ .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
+ .gp = IMX_GPIO_NR(3, 17)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
+ .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
+ .gp = IMX_GPIO_NR(3, 18)
+ }
+};
+
+iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const uart5_pads[] = {
+ MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const gpio_pads[] = {
+ /* LED enable */
+ MX6_PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* spi flash WP protect */
+ MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* backlight enable */
+ MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* LED yellow */
+ MX6_PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* LED red */
+ MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* LED green */
+ MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* LED blue */
+ MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* i2c4 scl */
+ MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* i2c4 sda */
+ MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* spi CS 1 */
+ MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const misc_pads[] = {
+ MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* OTG Power enable */
+ MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const enet_pads[] = {
+ MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(0x4001b0a8),
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+ /* set GPIO_16 as ENET_REF_CLK_OUT */
+ setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
+}
+
+static iomux_v3_cfg_t const backlight_pads[] = {
+ MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_SD4_DAT1__PWM3_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const ecspi4_pads[] = {
+ MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const display_pads[] = {
+ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL),
+ MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
+ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
+ MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
+ MX6_PAD_DI0_PIN4__GPIO4_IO20,
+ MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
+ MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
+ MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
+ MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
+ MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
+ MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
+ MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
+ MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
+ MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
+ MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
+ MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
+ MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
+ MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
+ MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
+ MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
+ MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
+ MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
+ MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
+ MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
+ MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
+ MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
+ MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
+ MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
+ MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
+};
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
+ ? (IMX_GPIO_NR(3, 20)) : -1;
+}
+
+static void setup_spi(void)
+{
+ int i;
+
+ imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
+ for (i = 0; i < 3; i++)
+ enable_spi_clk(true, i);
+
+ /* set cs1 to high */
+ gpio_direction_output(ECSPI4_CS1, 1);
+}
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
+}
+
+int board_eth_init(bd_t *bis)
+{
+ struct iomuxc *iomuxc_regs =
+ (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int ret;
+
+ /* clear gpr1[14], gpr1[18:17] to select anatop clock */
+ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
+
+ ret = enable_fec_anatop_clock(ENET_50MHZ);
+ if (ret)
+ return ret;
+
+ setup_iomux_enet();
+ return cpu_eth_init(bis);
+}
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+ imx_iomux_v3_setup_multiple_pads(
+ display_pads,
+ ARRAY_SIZE(display_pads));
+ imx_iomux_v3_setup_multiple_pads(
+ backlight_pads,
+ ARRAY_SIZE(backlight_pads));
+
+ /* enable backlight PWM 3 */
+ if (pwm_init(2, 0, 0))
+ goto error;
+ /* duty cycle 500ns, period: 3000ns */
+ if (pwm_config(2, 500, 3000))
+ goto error;
+ if (pwm_enable(2))
+ goto error;
+ return;
+
+error:
+ puts("error init pwm for backlight\n");
+ return;
+}
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ int reg;
+
+ enable_ipu_clock();
+
+ reg = readl(&mxc_ccm->cs2cdr);
+ /* select pll 5 clock */
+ reg &= MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK;
+ reg &= MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK;
+ writel(reg, &mxc_ccm->cs2cdr);
+
+ imx_iomux_v3_setup_multiple_pads(backlight_pads,
+ ARRAY_SIZE(backlight_pads));
+}
+
+static void setup_iomux_gpio(void)
+{
+ imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ setup_iomux_gpio();
+
+ setup_display();
+ return 0;
+}
+
+
+static void setup_i2c4(void)
+{
+ /* i2c4 not used, set it to gpio input */
+ gpio_request(IMX_GPIO_NR(1, 7), "i2c4_scl");
+ gpio_direction_input(IMX_GPIO_NR(1, 7));
+ gpio_request(IMX_GPIO_NR(1, 8), "i2c4_sda");
+ gpio_direction_input(IMX_GPIO_NR(1, 8));
+}
+
+static void setup_board_gpio(void)
+{
+ /* enable LED */
+ gpio_request(IMX_GPIO_NR(2, 13), "LED ena");
+ gpio_direction_output(IMX_GPIO_NR(2, 13), 0);
+
+ gpio_request(IMX_GPIO_NR(1, 3), "LED yellow");
+ gpio_direction_output(IMX_GPIO_NR(1, 3), 1);
+ gpio_request(IMX_GPIO_NR(1, 4), "LED red");
+ gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
+ gpio_request(IMX_GPIO_NR(1, 5), "LED green");
+ gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
+ gpio_request(IMX_GPIO_NR(1, 6), "LED blue");
+ gpio_direction_output(IMX_GPIO_NR(1, 6), 1);
+}
+
+static void setup_board_spi(void)
+{
+}
diff --git a/board/aristainetos/aristainetos-v2.c b/board/aristainetos/aristainetos-v2.c
new file mode 100644
index 0000000000000000000000000000000000000000..7a440310437ad9d77e2bc334e755c67c1db0736d
--- /dev/null
+++ b/board/aristainetos/aristainetos-v2.c
@@ -0,0 +1,627 @@
+/*
+ * (C) Copyright 2015
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <asm/imx-common/video.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <asm/arch/crm_regs.h>
+#include <linux/fb.h>
+#include <ipu_pixfmt.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <pwm.h>
+#include <micrel.h>
+#include <spi.h>
+#include <video.h>
+#include <../drivers/video/ipu.h>
+#if defined(CONFIG_VIDEO_BMP_LOGO)
+ #include <bmp_logo.h>
+#endif
+
+#define USDHC2_PAD_CTRL (PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define ECSPI1_CS0 IMX_GPIO_NR(4, 9) /* 4.3 display controller */
+#define ECSPI4_CS0 IMX_GPIO_NR(3, 29)
+#define SOFT_RESET_GPIO IMX_GPIO_NR(7, 13)
+#define SD2_DRIVER_ENABLE IMX_GPIO_NR(7, 8)
+
+struct i2c_pads_info i2c_pad_info3 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
+ .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
+ .gp = IMX_GPIO_NR(1, 5)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
+ .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
+ .gp = IMX_GPIO_NR(1, 6)
+ }
+};
+
+struct i2c_pads_info i2c_pad_info4 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_GPIO_7__I2C4_SCL | PC,
+ .gpio_mode = MX6_PAD_GPIO_7__GPIO1_IO07 | PC,
+ .gp = IMX_GPIO_NR(1, 7)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_GPIO_8__I2C4_SDA | PC,
+ .gpio_mode = MX6_PAD_GPIO_8__GPIO1_IO08 | PC,
+ .gp = IMX_GPIO_NR(1, 8)
+ }
+};
+
+iomux_v3_cfg_t const uart1_pads[] = {
+ MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D19__UART1_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D20__UART1_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const uart2_pads[] = {
+ MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const uart3_pads[] = {
+ MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const uart4_pads[] = {
+ MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const gpio_pads[] = {
+ /* LED enable*/
+ MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* LED yellow */
+ MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* LED red */
+ MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* LED green */
+ MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* LED blue */
+ MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* spi flash WP protect */
+ MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* spi CS 0 */
+ MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* spi bus #2 SS driver enable */
+ MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* RST_LOC# PHY reset input (has pull-down!)*/
+ MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* SD 2 level shifter output enable */
+ MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* SD1 card detect input */
+ MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* SD1 write protect input */
+ MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* SD2 card detect input */
+ MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* SD2 write protect input */
+ MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* Touchscreen IRQ */
+ MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const misc_pads[] = {
+ /* USB_OTG_ID = GPIO1_24*/
+ MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* H1 Power enable = GPIO1_0*/
+ MX6_PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* OTG Power enable = GPIO4_15*/
+ MX6_PAD_KEY_ROW4__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const enet_pads[] = {
+ MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const backlight_pads[] = {
+ /* backlight PWM brightness control */
+ MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* backlight enable */
+ MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ /* LCD power enable */
+ MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const ecspi1_pads[] = {
+ MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(SPI_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+}
+
+iomux_v3_cfg_t const ecspi4_pads[] = {
+ MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const display_pads[] = {
+ MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL),
+ MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
+ MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
+ MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
+ MX6_PAD_DI0_PIN4__GPIO4_IO20,
+ MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
+ MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
+ MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
+ MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
+ MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
+ MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
+ MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
+ MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
+ MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
+ MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
+ MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
+ MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
+ MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
+ MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
+ MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
+ MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
+ MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
+ MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
+ MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
+ MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
+ MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
+ MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
+ MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
+ MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
+};
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+ if (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
+ return IMX_GPIO_NR(5, 2);
+
+ if (bus == 0 && cs == 0)
+ return IMX_GPIO_NR(4, 9);
+
+ return -1;
+}
+
+static void setup_spi(void)
+{
+ int i;
+
+ imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+ imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
+ for (i = 0; i < 4; i++)
+ enable_spi_clk(true, i);
+
+ gpio_direction_output(ECSPI1_CS0, 1);
+ gpio_direction_output(ECSPI4_CS1, 0);
+
+ /* set cs0 to high (second device on spi bus #4) */
+ gpio_direction_output(ECSPI4_CS0, 1);
+}
+
+static void setup_iomux_uart(void)
+{
+ switch (CONFIG_MXC_UART_BASE) {
+ case UART1_BASE:
+ imx_iomux_v3_setup_multiple_pads(uart1_pads,
+ ARRAY_SIZE(uart1_pads));
+ break;
+ case UART2_BASE:
+ imx_iomux_v3_setup_multiple_pads(uart2_pads,
+ ARRAY_SIZE(uart2_pads));
+ break;
+ case UART3_BASE:
+ imx_iomux_v3_setup_multiple_pads(uart3_pads,
+ ARRAY_SIZE(uart3_pads));
+ break;
+ case UART4_BASE:
+ imx_iomux_v3_setup_multiple_pads(uart4_pads,
+ ARRAY_SIZE(uart4_pads));
+ break;
+ }
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ /* control data pad skew - devaddr = 0x02, register = 0x04 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+ /* rx data pad skew - devaddr = 0x02, register = 0x05 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+ /* tx data pad skew - devaddr = 0x02, register = 0x06 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
+ /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
+ ksz9031_phy_extended_write(phydev, 0x02,
+ MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+ MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ setup_iomux_enet();
+ return cpu_eth_init(bis);
+}
+
+static int rotate_logo_one(unsigned char *out, unsigned char *in)
+{
+ int i, j;
+
+ for (i = 0; i < BMP_LOGO_WIDTH; i++)
+ for (j = 0; j < BMP_LOGO_HEIGHT; j++)
+ out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] =
+ in[i * BMP_LOGO_WIDTH + j];
+ return 0;
+}
+
+/*
+ * Rotate the BMP_LOGO (only)
+ * Will only work, if the logo is square, as
+ * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables
+ */
+void rotate_logo(int rotations)
+{
+ unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT];
+ unsigned char *in_logo;
+ int i, j;
+
+ if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT)
+ return;
+
+ in_logo = bmp_logo_bitmap;
+
+ /* one 90 degree rotation */
+ if (rotations == 1 || rotations == 2 || rotations == 3)
+ rotate_logo_one(out_logo, in_logo);
+
+ /* second 90 degree rotation */
+ if (rotations == 2 || rotations == 3)
+ rotate_logo_one(in_logo, out_logo);
+
+ /* third 90 degree rotation */
+ if (rotations == 3)
+ rotate_logo_one(out_logo, in_logo);
+
+ /* copy result back to original array */
+ if (rotations == 1 || rotations == 3)
+ for (i = 0; i < BMP_LOGO_WIDTH; i++)
+ for (j = 0; j < BMP_LOGO_HEIGHT; j++)
+ in_logo[i * BMP_LOGO_WIDTH + j] =
+ out_logo[i * BMP_LOGO_WIDTH + j];
+}
+
+static void enable_display_power(void)
+{
+ imx_iomux_v3_setup_multiple_pads(backlight_pads,
+ ARRAY_SIZE(backlight_pads));
+
+ /* backlight enable */
+ gpio_direction_output(IMX_GPIO_NR(6, 31), 1);
+ /* LCD power enable */
+ gpio_direction_output(IMX_GPIO_NR(6, 15), 1);
+
+ /* enable backlight PWM 1 */
+ if (pwm_init(0, 0, 0))
+ goto error;
+ /* duty cycle 500ns, period: 3000ns */
+ if (pwm_config(0, 50000, 300000))
+ goto error;
+ if (pwm_enable(0))
+ goto error;
+ return;
+
+error:
+ puts("error init pwm for backlight\n");
+ return;
+}
+
+static void enable_lvds(struct display_info_t const *dev)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ int reg;
+ s32 timeout = 100000;
+
+ /* set PLL5 clock */
+ reg = readl(&ccm->analog_pll_video);
+ reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
+ writel(reg, &ccm->analog_pll_video);
+
+ /* set PLL5 to 232720000Hz */
+ reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
+ reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26);
+ reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
+ reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
+ writel(reg, &ccm->analog_pll_video);
+
+ writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238),
+ &ccm->analog_pll_video_num);
+ writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240),
+ &ccm->analog_pll_video_denom);
+
+ reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
+ writel(reg, &ccm->analog_pll_video);
+
+ while (timeout--)
+ if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
+ break;
+ if (timeout < 0)
+ printf("Warning: video pll lock timeout!\n");
+
+ reg = readl(&ccm->analog_pll_video);
+ reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
+ reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
+ writel(reg, &ccm->analog_pll_video);
+
+ /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
+ reg = readl(&ccm->cs2cdr);
+ reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+ | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+ reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+ | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+ writel(reg, &ccm->cs2cdr);
+
+ reg = readl(&ccm->cscmr2);
+ reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+ writel(reg, &ccm->cscmr2);
+
+ reg = readl(&ccm->chsccdr);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+ << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+ writel(reg, &ccm->chsccdr);
+
+ reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+ | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
+ | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
+ | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+ | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
+ | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
+ | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+ writel(reg, &iomux->gpr[2]);
+
+ reg = readl(&iomux->gpr[3]);
+ reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
+ | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+ << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+ writel(reg, &iomux->gpr[3]);
+
+ return;
+}
+
+static void enable_spi_display(struct display_info_t const *dev)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ int reg;
+ s32 timeout = 100000;
+
+#if defined(CONFIG_VIDEO_BMP_LOGO)
+ rotate_logo(3); /* portrait display in landscape mode */
+#endif
+
+ /*
+ * set ldb clock to 28341000 Hz calculated through the formula:
+ * (XRES + LEFT_M + RIGHT_M + HSYNC_LEN) *
+ * (YRES + UPPER_M + LOWER_M + VSYNC_LEN) * REFRESH)
+ * see:
+ * https://community.freescale.com/thread/308170
+ */
+ ipu_set_ldb_clock(28341000);
+
+ reg = readl(&ccm->cs2cdr);
+
+ /* select pll 5 clock */
+ reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+ | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+ writel(reg, &ccm->cs2cdr);
+
+ /* set PLL5 to 197994996Hz */
+ reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
+ reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21);
+ reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
+ reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
+ writel(reg, &ccm->analog_pll_video);
+
+ writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4),
+ &ccm->analog_pll_video_num);
+ writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240),
+ &ccm->analog_pll_video_denom);
+
+ reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
+ writel(reg, &ccm->analog_pll_video);
+
+ while (timeout--)
+ if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
+ break;
+ if (timeout < 0)
+ printf("Warning: video pll lock timeout!\n");
+
+ reg = readl(&ccm->analog_pll_video);
+ reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
+ reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
+ writel(reg, &ccm->analog_pll_video);
+
+ /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
+ reg = readl(&ccm->cs2cdr);
+ reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
+ | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
+ reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
+ | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+ writel(reg, &ccm->cs2cdr);
+
+ reg = readl(&ccm->cscmr2);
+ reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
+ writel(reg, &ccm->cscmr2);
+
+ reg = readl(&ccm->chsccdr);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+ << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
+ reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
+ reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET);
+ reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
+ reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
+ writel(reg, &ccm->chsccdr);
+
+ reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
+ | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
+ | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
+ | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
+ | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
+ | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
+ | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
+ writel(reg, &iomux->gpr[2]);
+
+ reg = readl(&iomux->gpr[3]);
+ reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
+ | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
+ << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
+ writel(reg, &iomux->gpr[3]);
+
+ imx_iomux_v3_setup_multiple_pads(
+ display_pads,
+ ARRAY_SIZE(display_pads));
+
+ return;
+}
+static void setup_display(void)
+{
+ enable_ipu_clock();
+ enable_display_power();
+}
+
+static void setup_iomux_gpio(void)
+{
+ imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+ setup_iomux_gpio();
+
+ gpio_direction_output(SOFT_RESET_GPIO, 1);
+ gpio_direction_output(SD2_DRIVER_ENABLE, 1);
+ setup_display();
+ return 0;
+}
+
+static void setup_i2c4(void)
+{
+ setup_i2c(3, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
+ &i2c_pad_info4);
+}
+
+static void setup_board_gpio(void)
+{
+ /* enable all LEDs */
+ gpio_request(IMX_GPIO_NR(2, 13), "LED ena"); /* 25 */
+ gpio_direction_output(IMX_GPIO_NR(1, 25), 0);
+
+ /* switch off Status LEDs */
+ gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */
+ gpio_direction_output(IMX_GPIO_NR(6, 16), 1);
+ gpio_request(IMX_GPIO_NR(2, 28), "LED red"); /* 60 */
+ gpio_direction_output(IMX_GPIO_NR(2, 28), 1);
+ gpio_request(IMX_GPIO_NR(5, 4), "LED green"); /* 132 */
+ gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
+ gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */
+ gpio_direction_output(IMX_GPIO_NR(2, 29), 1);
+}
+
+static void setup_board_spi(void)
+{
+ /* enable spi bus #2 SS drivers */
+ gpio_direction_output(IMX_GPIO_NR(6, 6), 1);
+}
+
+int board_late_init(void)
+{
+ char *my_bootdelay;
+ char bootmode = 0;
+ char const *panel = getenv("panel");
+
+ /*
+ * Check the boot-source. If booting from NOR Flash,
+ * disable bootdelay
+ */
+ gpio_request(IMX_GPIO_NR(7, 6), "bootsel0");
+ gpio_direction_input(IMX_GPIO_NR(7, 6));
+ gpio_request(IMX_GPIO_NR(7, 7), "bootsel1");
+ gpio_direction_input(IMX_GPIO_NR(7, 7));
+ gpio_request(IMX_GPIO_NR(7, 1), "bootsel2");
+ gpio_direction_input(IMX_GPIO_NR(7, 1));
+ bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 6)) ? 1 : 0) << 0;
+ bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 7)) ? 1 : 0) << 1;
+ bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 1)) ? 1 : 0) << 2;
+
+ if (bootmode == 7) {
+ my_bootdelay = getenv("nor_bootdelay");
+ if (my_bootdelay != NULL)
+ setenv("bootdelay", my_bootdelay);
+ else
+ setenv("bootdelay", "-2");
+ }
+
+ /* if we have the lg panel, we can initialze it now */
+ if (panel)
+ if (!strcmp(panel, displays[1].mode.name))
+ lg4573_spi_startup(0, 0, 10000000, SPI_MODE_0);
+
+ return 0;
+}
+
diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c
index 8330bb64bdae56163054bb266dc88b5af0443397..0c39ee6cf1f43859d80aa77393a635a43297344a 100644
--- a/board/aristainetos/aristainetos.c
+++ b/board/aristainetos/aristainetos.c
@@ -58,6 +58,13 @@ DECLARE_GLOBAL_DATA_PTR;
#define ECSPI4_CS1 IMX_GPIO_NR(5, 2)
+#if (CONFIG_SYS_BOARD_VERSION == 1)
+#include "./aristainetos-v1.c"
+#elif (CONFIG_SYS_BOARD_VERSION == 2)
+#include "./aristainetos-v2.c"
+#endif
+
+
struct i2c_pads_info i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
@@ -84,89 +91,6 @@ struct i2c_pads_info i2c_pad_info2 = {
}
};
-struct i2c_pads_info i2c_pad_info3 = {
- .scl = {
- .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
- .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
- .gp = IMX_GPIO_NR(3, 17)
- },
- .sda = {
- .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
- .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
- .gp = IMX_GPIO_NR(3, 18)
- }
-};
-
-int dram_init(void)
-{
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
-
- return 0;
-}
-
-iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const uart5_pads[] = {
- MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const gpio_pads[] = {
- /* LED enable */
- MX6_PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* spi flash WP protect */
- MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* backlight enable */
- MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* LED yellow */
- MX6_PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* LED red */
- MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* LED green */
- MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* LED blue */
- MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* i2c4 scl */
- MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* i2c4 sda */
- MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* spi CS 1 */
- MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const misc_pads[] = {
- MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
- /* OTG Power enable */
- MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const enet_pads[] = {
- MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(0x4001b0a8),
- MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-static void setup_iomux_enet(void)
-{
- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
- imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
-
- /* set GPIO_16 as ENET_REF_CLK_OUT */
- setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
-}
-
iomux_v3_cfg_t const usdhc1_pads[] = {
MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -176,86 +100,11 @@ iomux_v3_cfg_t const usdhc1_pads[] = {
MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
-iomux_v3_cfg_t const usdhc2_pads[] = {
- MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-};
-
-iomux_v3_cfg_t const ecspi4_pads[] = {
- MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-static iomux_v3_cfg_t const display_pads[] = {
- MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL),
- MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
- MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
- MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
- MX6_PAD_DI0_PIN4__GPIO4_IO20,
- MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
- MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
- MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
- MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
- MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
- MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
- MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
- MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
- MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
- MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
- MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
- MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
- MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
- MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
- MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
- MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
- MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
- MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
- MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
- MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
- MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
- MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
- MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
- MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
-};
-
-static iomux_v3_cfg_t const backlight_pads[] = {
- MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_SD4_DAT1__PWM3_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
- return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
- ? (IMX_GPIO_NR(3, 20)) : -1;
-}
-
-static void setup_spi(void)
-{
- int i;
-
- imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
- for (i = 0; i < 3; i++)
- enable_spi_clk(true, i);
-
- /* set cs1 to high */
- gpio_direction_output(ECSPI4_CS1, 1);
-}
-
-static void setup_iomux_gpio(void)
+int dram_init(void)
{
- imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
-}
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
-static void setup_iomux_uart(void)
-{
- imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
+ return 0;
}
#ifdef CONFIG_FSL_ESDHC
@@ -272,13 +121,24 @@ int board_mmc_getcd(struct mmc *mmc)
int board_mmc_init(bd_t *bis)
{
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
- usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-
imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
- imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
-
- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]) |
- fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
+#if (CONFIG_SYS_BOARD_VERSION == 2)
+ /*
+ * usdhc2 has a levelshifter on the carrier board Rev. DV1,
+ * that will automatically detect the driving direction.
+ * During initialisation this isn't working correctly,
+ * which causes DAT3 to be driven low towards the SD-card.
+ * This causes a SD-card enetring the SPI-Mode
+ * and therefore getting inaccessible until next power cycle.
+ * As workaround we drive the DAT3 line as GPIO and set it high.
+ * This makes usdhc2 unusable in u-boot, but works for the
+ * initialisation in Linux
+ */
+ imx_iomux_v3_setup_pad(MX6_PAD_SD2_DAT3__GPIO1_IO12 |
+ MUX_PAD_CTRL(NO_PAD_CTRL));
+ gpio_direction_output(IMX_GPIO_NR(1, 12) , 1);
+#endif
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}
#endif
@@ -291,48 +151,6 @@ int overwrite_console(void)
return 1;
}
-int board_eth_init(bd_t *bis)
-{
- struct iomuxc *iomuxc_regs =
- (struct iomuxc *)IOMUXC_BASE_ADDR;
- int ret;
-
- setup_iomux_enet();
- /* clear gpr1[14], gpr1[18:17] to select anatop clock */
- clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
-
- ret = enable_fec_anatop_clock(ENET_50MHZ);
- if (ret)
- return ret;
-
- return cpu_eth_init(bis);
-}
-#if defined(CONFIG_VIDEO_IPUV3)
-
-static void enable_lvds(struct display_info_t const *dev)
-{
- imx_iomux_v3_setup_multiple_pads(
- display_pads,
- ARRAY_SIZE(display_pads));
- imx_iomux_v3_setup_multiple_pads(
- backlight_pads,
- ARRAY_SIZE(backlight_pads));
-
- /* enable backlight PWM 3 */
- if (pwm_init(2, 0, 0))
- goto error;
- /* duty cycle 500ns, period: 3000ns */
- if (pwm_config(2, 500, 3000))
- goto error;
- if (pwm_enable(2))
- goto error;
- return;
-
-error:
- puts("error init pwm for backlight\n");
- return;
-}
-
struct display_info_t const displays[] = {
{
.bus = -1,
@@ -356,43 +174,39 @@ struct display_info_t const displays[] = {
.vmode = FB_VMODE_NONINTERLACED
}
}
+#if (CONFIG_SYS_BOARD_VERSION == 2)
+ , {
+ .bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = NULL,
+ .enable = enable_spi_display,
+ .mode = {
+ .name = "lg4573",
+ .refresh = 60,
+ .xres = 480,
+ .yres = 800,
+ .pixclock = 37037,
+ .left_margin = 59,
+ .right_margin = 10,
+ .upper_margin = 15,
+ .lower_margin = 15,
+ .hsync_len = 10,
+ .vsync_len = 15,
+ .sync = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT |
+ FB_SYNC_VERT_HIGH_ACT,
+ .vmode = FB_VMODE_NONINTERLACED
+ }
+ }
+#endif
};
size_t display_count = ARRAY_SIZE(displays);
-static void setup_display(void)
-{
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- int reg;
-
- enable_ipu_clock();
-
- reg = readl(&mxc_ccm->cs2cdr);
- /* select pll 5 clock */
- reg &= MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK;
- reg &= MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK;
- writel(reg, &mxc_ccm->cs2cdr);
-
- imx_iomux_v3_setup_multiple_pads(backlight_pads,
- ARRAY_SIZE(backlight_pads));
-}
-
/* no console on this board */
int board_cfb_skip(void)
{
return 1;
}
-#endif
-
-int board_early_init_f(void)
-{
- setup_iomux_uart();
- setup_iomux_gpio();
-
-#if defined(CONFIG_VIDEO_IPUV3)
- setup_display();
-#endif
- return 0;
-}
iomux_v3_cfg_t nfc_pads[] = {
MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
@@ -424,6 +238,9 @@ static void setup_gpmi_nand(void)
imx_iomux_v3_setup_multiple_pads(nfc_pads,
ARRAY_SIZE(nfc_pads));
+ /* gate ENFC_CLK_ROOT clock first,before clk source switch */
+ clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
/* config gpmi and bch clock to 100 MHz */
clrsetbits_le32(&mxc_ccm->cs2cdr,
MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
@@ -433,6 +250,9 @@ static void setup_gpmi_nand(void)
MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
+ /* enable ENFC_CLK_ROOT clock */
+ setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
/* enable gpmi and bch clock gating */
setbits_le32(&mxc_ccm->CCGR4,
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
@@ -460,43 +280,26 @@ int board_init(void)
&i2c_pad_info2);
setup_i2c(2, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE,
&i2c_pad_info3);
-
- /* i2c4 not used, set it to gpio input */
- gpio_request(IMX_GPIO_NR(1, 7), "i2c4_scl");
- gpio_direction_input(IMX_GPIO_NR(1, 7));
- gpio_request(IMX_GPIO_NR(1, 8), "i2c4_sda");
- gpio_direction_input(IMX_GPIO_NR(1, 8));
+ setup_i2c4();
/* SPI NOR Flash read only */
gpio_request(CONFIG_GPIO_ENABLE_SPI_FLASH, "ena_spi_nor");
gpio_direction_output(CONFIG_GPIO_ENABLE_SPI_FLASH, 0);
gpio_free(CONFIG_GPIO_ENABLE_SPI_FLASH);
- /* enable LED */
- gpio_request(IMX_GPIO_NR(2, 13), "LED ena");
- gpio_direction_output(IMX_GPIO_NR(2, 13), 0);
-
- gpio_request(IMX_GPIO_NR(1, 3), "LED yellow");
- gpio_direction_output(IMX_GPIO_NR(1, 3), 1);
- gpio_request(IMX_GPIO_NR(1, 4), "LED red");
- gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
- gpio_request(IMX_GPIO_NR(1, 5), "LED green");
- gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
- gpio_request(IMX_GPIO_NR(1, 6), "LED blue");
- gpio_direction_output(IMX_GPIO_NR(1, 6), 1);
-
+ setup_board_gpio();
setup_gpmi_nand();
+ setup_board_spi();
/* GPIO_1 for USB_OTG_ID */
- setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK);
+ clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0);
imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
-
return 0;
}
int checkboard(void)
{
- puts("Board: aristaitenos\n");
+ printf("Board: %s\n", CONFIG_BOARDNAME);
return 0;
}
diff --git a/board/aristainetos/aristainetos2.cfg b/board/aristainetos/aristainetos2.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..dc2143bc4525b1cd0aab7e1be5d1644f36957f07
--- /dev/null
+++ b/board/aristainetos/aristainetos2.cfg
@@ -0,0 +1,34 @@
+/*
+ * (C) Copyright 2015
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd
+ */
+BOOT_FROM spi
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup2.cfg"
+#include "nt5cc256m16cp.cfg"
+#include "clocks2.cfg"
+#include "axi.cfg"
diff --git a/board/aristainetos/axi.cfg b/board/aristainetos/axi.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..0bb816ce79d91dce2d30b0dccc93d2ec1349a761
--- /dev/null
+++ b/board/aristainetos/axi.cfg
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
+
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
+DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
diff --git a/board/aristainetos/clocks2.cfg b/board/aristainetos/clocks2.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..987d9a47b0155a103ceb1b5acbf92d5b5bf04c06
--- /dev/null
+++ b/board/aristainetos/clocks2.cfg
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* set the default clock gate to save power */
+DATA 4, CCM_CCGR0, 0x00c03f3f
+DATA 4, CCM_CCGR1, 0x0030fcff
+DATA 4, CCM_CCGR2, 0x0fffcfc0
+DATA 4, CCM_CCGR3, 0x3ff0300f
+DATA 4, CCM_CCGR4, 0xfffff300
+DATA 4, CCM_CCGR5, 0x0f0000c3
+DATA 4, CCM_CCGR6, 0x00000fff
diff --git a/board/aristainetos/ddr-setup2.cfg b/board/aristainetos/ddr-setup2.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..3d5d8945a3467dc481c9eacca289dbc6bb2ab89d
--- /dev/null
+++ b/board/aristainetos/ddr-setup2.cfg
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+/* DDR IO TYPE */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+/* Clock */
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030
+/* Address */
+DATA 4, MX6_IOM_DRAM_CAS, 0x00000030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00000030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+/* Control */
+DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+/* Data Strobe */
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000028
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00000028
diff --git a/board/aristainetos/nt5cc256m16cp.cfg b/board/aristainetos/nt5cc256m16cp.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..2ff41e9c1412d5412fabbde679e6ea85651ce43e
--- /dev/null
+++ b/board/aristainetos/nt5cc256m16cp.cfg
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+/* ZQ Calibration */
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
+/*
+ * DQS gating, read delay, write delay calibration values
+ */
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42190217
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x017B017B
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4176017B
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x015F016C
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4C4C4D4C
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4A4D4C48
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3F40
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3538382E
+/* read data bit delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+/* Complete calibration by forced measurment */
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+/* in DDR3, 64-bit mode, only MMDC0 is initiated */
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00020025
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x676B5313
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8B63
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
+DATA 4, MX6_MMDC_P0_MDOR, 0x006B1023
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
+DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000
+
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+
+/* final ddr setup */
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025565
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
diff --git a/board/freescale/common/pfuze.c b/board/freescale/common/pfuze.c
index 4980bf7b0089528db6f0dc5a4c45d4db99d4eaa5..d6a209e1a3743fd6d732915e44d98293feb07d1d 100644
--- a/board/freescale/common/pfuze.c
+++ b/board/freescale/common/pfuze.c
@@ -71,10 +71,10 @@ struct pmic *pfuze_common_init(unsigned char i2cbus)
pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
- pmic_reg_read(p, PUZE_100_SW1ABCONF, ®);
+ pmic_reg_read(p, PFUZE100_SW1ABCONF, ®);
reg &= ~SW1xCONF_DVSSPEED_MASK;
reg |= SW1xCONF_DVSSPEED_4US;
- pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
+ pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
/* Set SW1C standby voltage to 0.975V */
pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
diff --git a/board/gateworks/gw_ventana/README b/board/gateworks/gw_ventana/README
index 888657cb0c79f6c9447fff876315049aeb73a61e..697e5c8bb4c7582309a4446e918d9026741a0727 100644
--- a/board/gateworks/gw_ventana/README
+++ b/board/gateworks/gw_ventana/README
@@ -3,6 +3,12 @@ U-Boot for the Gateworks Ventana Product Family boards
This file contains information for the port of U-Boot to the Gateworks
Ventana Product family boards.
+The entire Ventana product family (http://www.gateworks.com/product#ventana)
+is supported by a single bootloader build by using a common SPL and U-Boot
+that dynamically determines the characterstics of the board at runtime via
+information from an EEPROM on the board programmed at the factory and supports
+all of the various boot mediums available.
+
1. Secondary Program Loader (SPL)
---------------------------------
@@ -28,8 +34,20 @@ To build U-Boot for the Gateworks Ventana product family:
make
-3. Boot source, boot from NAND
-------------------------------
+3. Boot source:
+---------------
+
+The Gateworks Ventana boards support booting from NAND or micro-SD depending
+on the board model. The IMX6 BOOT ROM will choose a boot media based on eFUSE
+settings programmed at the factory.
+
+Boards with NAND flash will always boot from NAND, and NAND-less boards will
+always boot from micro-SD. However, it is possible to use the U-Boot bmode
+command (or the technique it uses) to essentially bootstrap to another boot
+media at runtime.
+
+3.1. boot from NAND
+-------------------
The i.MX6 BOOT ROM expects some structures that provide details of NAND layout
and bad block information (referred to as 'bootstreams') which are replicated
@@ -77,7 +95,226 @@ via the mtdparts env var:
- rootfs: the rest
This information is taken from:
- http://trac.gateworks.com/wiki/ventana/bootloader#NANDFLASH
+ http://trac.gateworks.com/wiki/ventana/bootloader#nand
+
+More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manual.
+
+3.1. boot from micro-SD
+-----------------------
+
+When the IMX6 eFUSE settings have been factory programmed to boot from
+micro-SD the SPL will be loaded from offset 0x400 (1KB). Once the SPL is
+booted, it will load and execute U-boot (u-boot.img) from offset 69KB
+on the micro-SD (defined by CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR).
+
+While it is technically possible to enable the SPL to be able to load
+U-Boot from a file on a FAT/EXT filesystem on the micro-SD, we chose to
+use raw micro-SD access to keep the code-size and boot time of the SPL down.
+
+For these reasons a micro-SD that will be used as an IMX6 primary boot
+device must be carefully partitioned and prepared.
+
+The following shell commands are executed on a Linux host (adjust DEV to the
+block storage device of your micro-SD):
+
+ DEV=/dev/sdc
+ # zero out 1MB of device
+ sudo dd if=/dev/zero of=$DEV count=1 bs=1M oflag=sync status=none && sync
+ # copy SPL to 1KB offset
+ sudo dd if=SPL of=$DEV bs=1K seek=1 oflag=sync status=none && sync
+ # copy U-Boot to 69KB offset
+ sudo dd if=u-boot.img of=$DEV bs=1K seek=69 oflag=sync status=none && sync
+ # create a partition table with a single rootfs partition starting at 1MB
+ printf "1,,L\n" | sudo sfdisk --in-order --no-reread -L -uM $DEV && sync
+ # format partition
+ sudo mkfs.ext4 -L root ${DEV}1
+ # mount the partition
+ sudo udisks --mount ${DEV}1
+ # extract filesystem
+ sudo tar xvf rootfs.tar.gz -C /media/root
+ # flush and unmount
+ sync && sudo umount /media/root
+
+The above assumes the default Ventana micro-SD partitioning scheme
+ - spl : 1KB-69KB (68KB) required by IMX6 BOOT ROM
+ - uboot : 69KB-709KB (640KB) defined by
+ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
+ - env : 709KB-965KB (256KB) defined by
+ CONFIG_ENV_MMC_SIZE
+ CONFIG_ENV_MMC_OFFSET_REDUND
+ - rootfs : 1MB-
+
+This information is taken from:
+ http://trac.gateworks.com/wiki/ventana/bootloader#microsd
More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manual.
+4. Falcon Mode
+------------------------------
+
+The Gateworks Ventana board config enables Falcon mode (CONFIG_SPL_OS_BOOT)
+which allows the SPL to boot directly to an OS instead of to U-Boot
+(u-boot.img) thus acheiving a faster overall boot time. The time savings
+depends on your boot medium (ie NAND Flash vs micro-SD) and size/storage
+of the OS. The time savings can be anywhere from 2 seconds (256MB NAND Flash
+with ~1MB kernel) to 6 seconds or more (2GB NAND Flash with ~6 kernel)
+
+The Gateworks Ventana board supports Falcon mode for the following boot
+medium:
+ - NAND flash
+ - micro-SD
+
+For all boot mediums, raw mode is used. While support of more complex storage
+such as files on top of FAT/EXT filesystem is possible but not practical
+as the size of the SPL is fairly limitted (to 64KB based on the smallest
+size of available IMX6 iRAM) as well as the fact that this would increase
+OS load time which defeats the purpose of Falcon mode in the first place.
+
+The SPL decides to boot either U-Boot (u-boot.img) or the OS (args + kernel)
+based on the return value of the spl_start_uboot() function. While often
+this can simply be the state of a GPIO based pushbutton or DIP switch, for
+Gateworks Ventana, we use the U-Boot environment 'boot_os' variable which if
+set to '1' will choose to boot the OS rather than U-Boot. While the choice
+of adding env support to the SPL adds a little bit of time to the boot
+process as well as (significant really) SPL code space this was deemed most
+flexible as within the large variety of Gateworks Ventana boards not all of
+them have a user pushbutton and that pushbutton may be configured as a hard
+reset per user configuration.
+
+To use Falcon mode it is required that you first 'prepare' the 'args' data
+that is stored on your boot medium along with the kernel (which can be any
+OS or bare-metal application). In the case of the Linux kernel the 'args'
+is the flatenned device-tree which normally gets altered prior to booting linux
+by U-Boot's 'bootm' command. To achieve this for SPL we use the
+'spl export fdt' command in U-Boot after loading the kernel and dtb which
+will go through the same process of modifying the device-tree for the board
+being executed on but not jump to the kernel. This allows you to save the
+args data to the location the SPL expects it and then enable Falcon mode.
+
+It is important to realize that there are certain values in the dtb that
+are board model specific (IMX6Q vs IMX6DL for example) and board specific
+(board serial number, MAC addrs) so you do not want to use the 'args'
+data prepared from one board on another board.
+
+4.1. Falcon Mode on NAND flash
+------------------------------
+To prepare a Gateworks Ventana board that boots from NAND flash for Falcon
+mode you must program your flash such that the 'args' and 'kernel' are
+located where defined at compile time by the following:
+ CONFIG_CMD_SPL_NAND_OFS 17MB - offset of 'args'
+ CONFIG_SYS_NAND_SPL_KERNEL_OFFS 18MB - offset of 'kernel'
+
+The location offsets defined above are defaults chosen by Gateworks and are
+flexible if you want to re-define them.
+
+The following steps executed in U-Boot will configure Falcon mode for NAND
+using rootfs (ubi), kernel (uImage), and dtb from the network:
+
+ # change mtd partitions to the above mapping
+ Ventana > setenv mtdparts 'mtdparts=nand:14m(spl),2m(uboot),1m(env),1m(args),10m(kernel),-(rootfs)'
+
+ # flash rootfs (at 28MB)
+ Ventana > tftp ${loadaddr} rootfs_${flash_layout}.ubi && \
+ nand erase.part rootfs && nand write ${loadaddr} rootfs ${filesize}
+
+ # load the device-tree
+ Ventana > tftp ${fdt_addr} ventana/${fdt_file2}
+
+ # load the kernel
+ Ventana > tftp ${loadaddr} ventana/uImage
+
+ # flash kernel (at 18MB)
+ Ventana > nand erase.part kernel && nand write ${loadaddr} kernel ${filesize}
+
+ # set kernel args for the console and rootfs (used by spl export)
+ Ventana > setenv bootargs 'console=ttymxc1,115200 root=ubi0:rootfs ubi.mtd=5 rootfstype=ubifs quiet'
+
+ # create args based on env, board, EEPROM, and dtb
+ Ventana > spl export fdt ${loadaddr} - ${fdt_addr}
+
+ # flash args (at 17MB)
+ Ventana > nand erase.part args && nand write 18000000 args 100000
+
+ # set boot_os env var to enable booting to Linux
+ Ventana > setenv boot_os 1 && saveenv
+
+Be sure to adjust 'bootargs' above to your OS needs (this will be different
+for various distros such as OpenWrt, Yocto, Android, etc). You can use the
+value obtained from 'cat /proc/cmdline' when booted to Linux.
+
+This information is taken from:
+ http://trac.gateworks.com/wiki/ventana/bootloader/falcon-mode#nand
+
+
+4.2. Falcon Mode on micro-SD card
+---------------------------------
+
+To prepare a Gateworks Ventana board with a primary boot device of micro-SD
+you first need to make sure you build U-Boot with CONFIG_ENV_IS_IN_MMC
+instead of CONFIG_ENV_IS_IN_NAND.
+
+For micro-SD based Falcon mode you must program your micro-SD such that
+the 'args' and 'kernel' are located where defined at compile time
+by the following:
+ CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 (1MB) - offset of 'args'
+ CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 (2MB) - offset of 'kernel'
+
+The location offsets defined above are defaults chosen by Gateworks and are
+flexible if you want to re-define them.
+
+First you must prepare a micro-SD such that the SPL can be loaded by the
+IMX6 BOOT ROM (fixed offset of 1KB), and U-Boot can be loaded by the SPL
+(fixed offset of 69KB defined by CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR).
+
+The following shell commands are executed on a Linux host (adjust DEV to the
+block storage device of your micro-SD):
+
+ DEV=/dev/sdc
+ # zero out 1MB of device
+ sudo dd if=/dev/zero of=$DEV count=1 bs=1M oflag=sync status=none && sync
+ # copy SPL to 1KB offset
+ sudo dd if=SPL of=$DEV bs=1K seek=1 oflag=sync status=none && sync
+ # copy U-Boot to 69KB offset
+ sudo dd if=u-boot.img of=$DEV bs=1K seek=69 oflag=sync status=none && sync
+ # create a partition table with a single rootfs partition starting at 10MB
+ printf "10,,L\n" | sudo sfdisk --in-order --no-reread -L -uM $DEV && sync
+ # format partition
+ sudo mkfs.ext4 -L root ${DEV}1
+ # mount the partition
+ sudo udisks --mount ${DEV}1
+ # extract filesystem
+ sudo tar xvf rootfs.tar.gz -C /media/root
+ # flush and unmount
+ sync && sudo umount /media/root
+
+Now that your micro-SD partitioning has been adjusted to leave room for the
+raw 'args' and 'kernel' data boot the board with the prepared micro-SD, break
+out in U-Boot and use the following to enable Falcon mode:
+
+ # load device-tree from rootfs
+ Ventana > ext2load mmc 0:1 ${fdt_addr} boot/${fdt_file2}
+
+ # load kernel from rootfs
+ Ventana > ext2load mmc 0:1 ${loadaddr} boot/uImage
+
+ # write kernel at 2MB offset
+ Ventana > mmc write ${loadaddr} 0x1000 0x4000
+
+ # setup kernel bootargs
+ Ventana > setenv bootargs 'console=ttymxc1,115200 root=/dev/mmcblk0p1 rootfstype=ext4 rootwait rw'
+
+ # prepare args
+ Ventana > spl export fdt ${loadaddr} - ${fdt_addr}
+
+ # write args 1MB data (0x800 sectors) to 1MB offset (0x800 sectors)
+ Ventana > mmc write 18000000 0x800 0x800
+
+ # set boot_os to enable falcon mode
+ Ventana > setenv boot_os 1 && saveenv
+
+Be sure to adjust 'bootargs' above to your OS needs (this will be different
+for various distros such as OpenWrt, Yocto, Android, etc). You can use the
+value obtained from 'cat /proc/cmdline' when booted to Linux.
+
+This information is taken from:
+ http://trac.gateworks.com/wiki/ventana/bootloader/falcon-mode#microsd
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c
index 79cb5943d0ef38c932aa49b9fc78df81838066ac..9f5d2b17cd09717451b4b211c5591f1a2dfa9ae3 100644
--- a/board/gateworks/gw_ventana/gw_ventana_spl.c
+++ b/board/gateworks/gw_ventana/gw_ventana_spl.c
@@ -14,6 +14,7 @@
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/mxc_i2c.h>
+#include <environment.h>
#include <spl.h>
#include "gsc.h"
@@ -551,7 +552,29 @@ void spl_board_init(void)
default:
puts("Unknown boot device\n");
}
+
+ /* PMIC init */
+ setup_pmic();
+}
+
+#ifdef CONFIG_SPL_OS_BOOT
+/* return 1 if we wish to boot to uboot vs os (falcon mode) */
+int spl_start_uboot(void)
+{
+ int ret = 1;
+
+ debug("%s\n", __func__);
+#ifdef CONFIG_SPL_ENV_SUPPORT
+ env_init();
+ env_relocate_spec();
+ debug("boot_os=%s\n", getenv("boot_os"));
+ if (getenv_yesno("boot_os") == 1)
+ ret = 0;
+#endif
+ debug("%s booting %s\n", __func__, ret ? "uboot" : "linux");
+ return ret;
}
+#endif
void reset_cpu(ulong addr)
{
diff --git a/board/solidrun/mx6-microsom/800mhz_2x128mx16.cfg b/board/solidrun/mx6-microsom/800mhz_2x128mx16.cfg
deleted file mode 100644
index 40747abbdb2b0e79dc722578fd628fdfb5fd2cd3..0000000000000000000000000000000000000000
--- a/board/solidrun/mx6-microsom/800mhz_2x128mx16.cfg
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2013 SolidRun ltd.
- * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* ZQ Calibrations */
-DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
-DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003
-/* write leveling */
-DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x005a0057
-DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x004a0052
-/*
- * DQS gating, read delay, write delay calibration values
- * based on calibration compare of 0x00ffff00
- */
-DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x02480240
-DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02340230
-DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40404440
-DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x38343034
-/* read data bit delay */
-DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
-DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
-/* Complete calibration by forced measurement */
-DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
-DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
-
-/*
- * MMDC init:
- * in DDR3, 32-bit mode, only MMDC0 is initiated:
- */
-DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d
-DATA 4, MX6_MMDC_P0_MDOTC, 0x00333040
-
-DATA 4, MX6_MMDC_P0_MDCFG0, 0x3f435313
-DATA 4, MX6_MMDC_P0_MDCFG1, 0xb66e8b63
-
-DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db
-DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
-DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
-DATA 4, MX6_MMDC_P0_MDOR, 0x00431023
-/* CS0_END - 0x2fffffff, 512M */
-DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
-
-/* MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled */
-DATA 4, 0x021b0400, 0x11420000
-
-/* MMDC0_MDCTL- row-14bits; col-10bits; burst length 8;32-bit data bus */
-DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
-
-/*
- * Initialize 2GB DDR3 - Hynix H5TQ2G63BFR-H9C
- * MR2
- */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008032
-/* MR3 */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
-/* MR1 */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00008031
-/* MR0 */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030
-/* ZQ calibration */
-DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
-/* final DDR setup */
-DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
-DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007
-DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d
-DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
-DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
diff --git a/board/solidrun/mx6-microsom/clocks.cfg b/board/solidrun/mx6-microsom/clocks.cfg
deleted file mode 100644
index 12888113fbf63d1fcdc451d35b9958a32769c42e..0000000000000000000000000000000000000000
--- a/board/solidrun/mx6-microsom/clocks.cfg
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2013 SolidRun ltd.
- * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* set the default clock gate to save power */
-DATA 4, CCM_CCGR0, 0x00C03F3F
-DATA 4, CCM_CCGR1, 0x0030FC03
-DATA 4, CCM_CCGR2, 0x0FFFC000
-DATA 4, CCM_CCGR3, 0x3FF00000
-DATA 4, CCM_CCGR4, 0x00FFF300
-DATA 4, CCM_CCGR5, 0x0F0000C3
-DATA 4, CCM_CCGR6, 0x000003FF
-
-/* enable AXI cache for VDOA/VPU/IPU */
-DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
-/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
-DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
-DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
-
-/*
- * Setup CCM_CCOSR register as follows:
- *
- * cko1_en = 1 --> CKO1 enabled
- * cko1_div = 111 --> divide by 8
- * cko1_sel = 1011 --> ahb_clk_root
- *
- * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
- */
-DATA 4, CCM_CCOSR, 0x000000fb
diff --git a/board/solidrun/mx6-microsom/ddr-800mhz-32bit-setup.cfg b/board/solidrun/mx6-microsom/ddr-800mhz-32bit-setup.cfg
deleted file mode 100644
index f92fc19de47fe749f47c3f001a99908ca4109479..0000000000000000000000000000000000000000
--- a/board/solidrun/mx6-microsom/ddr-800mhz-32bit-setup.cfg
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright (C) 2013 Boundary Devices
- * Copyright (C) 2013 SolidRun ltd.
- * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * DDR3 settings
- * MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
- * memory bus width: 64 bits x16/x32/x64
- * MX6DL ddr is limited to 800 MHz(400 MHz clock)
- * memory bus width: 64 bits x16/x32/x64
- * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
- * memory bus width: 32 bits x16/x32
- */
-/* DDR IO TYPE */
-DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000
-DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
-/* Clock */
-DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000028
-DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000028
-/* Address */
-DATA 4, MX6_IOM_DRAM_CAS, 0x00000010
-DATA 4, MX6_IOM_DRAM_RAS, 0x00000010
-DATA 4, MX6_IOM_GRP_ADDDS, 0x00000010
-/* Control */
-DATA 4, MX6_IOM_DRAM_RESET, 0x00000010
-DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
-DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
-DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
-DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000010
-DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000010
-DATA 4, MX6_IOM_GRP_CTLDS, 0x00000010
-
-/*
- * Data Strobe: IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL - DDR_INPUT=0, CMOS,
- * CMOS mode saves power, but have less timing margin in case of DDR
- * timing issue on your board you can try DDR_MODE: [= 0x00020000]
- */
-DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
-
-DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028
-DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028
-DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028
-DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028
-DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000000
-DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000000
-DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000000
-DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000000
-
-/*
- * DATA:IOMUXC_SW_PAD_CTL_GRP_DDRMODE - DDR_INPUT=0, CMOS,
- * CMOS mode saves power, but have less timing margin in case of DDR
- * timing issue on your board you can try DDR_MODE: [= 0x00020000]
- */
-DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
-
-DATA 4, MX6_IOM_GRP_B0DS, 0x00000028
-DATA 4, MX6_IOM_GRP_B1DS, 0x00000028
-DATA 4, MX6_IOM_GRP_B2DS, 0x00000028
-DATA 4, MX6_IOM_GRP_B3DS, 0x00000028
-DATA 4, MX6_IOM_GRP_B4DS, 0x00000000
-DATA 4, MX6_IOM_GRP_B5DS, 0x00000000
-DATA 4, MX6_IOM_GRP_B6DS, 0x00000000
-DATA 4, MX6_IOM_GRP_B7DS, 0x00000000
-
-DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028
-DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028
-DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028
-DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028
-DATA 4, MX6_IOM_DRAM_DQM4, 0x00000000
-DATA 4, MX6_IOM_DRAM_DQM5, 0x00000000
-DATA 4, MX6_IOM_DRAM_DQM6, 0x00000000
-DATA 4, MX6_IOM_DRAM_DQM7, 0x00000000
diff --git a/board/wandboard/MAINTAINERS b/board/wandboard/MAINTAINERS
index b986980437e8f46aa8fa8d3f50c5786c427682fa..0680517c36fbe38221a26badd0bd3f9c7af41d7a 100644
--- a/board/wandboard/MAINTAINERS
+++ b/board/wandboard/MAINTAINERS
@@ -3,6 +3,4 @@ M: Fabio Estevam <fabio.estevam@freescale.com>
S: Maintained
F: board/wandboard/
F: include/configs/wandboard.h
-F: configs/wandboard_dl_defconfig
-F: configs/wandboard_quad_defconfig
-F: configs/wandboard_solo_defconfig
+F: configs/wandboard_defconfig
diff --git a/board/wandboard/Makefile b/board/wandboard/Makefile
index 5b50ecaf22d69a64f7803d0fabb2f7b0017560e2..db9f4a685190d5a95bdb516be377766d20745777 100644
--- a/board/wandboard/Makefile
+++ b/board/wandboard/Makefile
@@ -4,4 +4,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := wandboard.o
+obj-y := wandboard.o spl.o
diff --git a/board/wandboard/README b/board/wandboard/README
index 1f678e16a9ba0c2358093dcfe5ca311fececcd46..c6c01322b64cd2a11d47b9443f63a43b3449b960 100644
--- a/board/wandboard/README
+++ b/board/wandboard/README
@@ -12,31 +12,25 @@ http://www.wandboard.org/
Building U-boot for Wandboard
-----------------------------
-To build U-Boot for the Wandboard Dual Lite version:
+To build U-Boot for the Wandboard:
-$ make wandboard_dl_config
-$ make
-
-To build U-Boot for the Wandboard Solo version:
-
-$ make wandboard_solo_config
-$ make
-
-To build U-Boot for the Wandboard Quad version:
-
-$ make wandboard_quad_config
+$ make wandboard_config
$ make
Flashing U-boot into the SD card
--------------------------------
-- After the 'make' command completes, the generated 'u-boot.imx' binary must be
+- After the 'make' command completes, the generated 'SPL' binary must be
flashed into the SD card;
-$ sudo dd if=u-boot.imx of=/dev/mmcblk0 bs=512 seek=2; sync
+$ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
(Note - the SD card node may vary, so adjust this as needed).
+- Flash the u-boot.img image into the SD card:
+
+sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
- Insert the SD card into the slot located in the bottom of the board (same side
as the mx6 processor)
diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c
new file mode 100644
index 0000000000000000000000000000000000000000..77afae7afd6fa51cd898e515f6482eb6ba7f13c3
--- /dev/null
+++ b/board/wandboard/spl.c
@@ -0,0 +1,317 @@
+/*
+ * Copyright (C) 2014 Wandboard
+ * Author: Tungyi Lin <tungyilin1127@gmail.com>
+ * Richard Hu <hakahu@gmail.com>
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/video.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_SPL_BUILD)
+#include <asm/arch/mx6-ddr.h>
+/*
+ * Driving strength:
+ * 0x30 == 40 Ohm
+ * 0x28 == 48 Ohm
+ */
+
+#define IMX6DQ_DRIVE_STRENGTH 0x30
+#define IMX6SDL_DRIVE_STRENGTH 0x28
+
+/* configure MX6Q/DUAL mmdc DDR io registers */
+static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
+ .dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_cas = IMX6DQ_DRIVE_STRENGTH,
+ .dram_ras = IMX6DQ_DRIVE_STRENGTH,
+ .dram_reset = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
+ .dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
+};
+
+/* configure MX6Q/DUAL mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
+ .grp_ddr_type = 0x000c0000,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_ddrpke = 0x00000000,
+ .grp_addds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
+ .grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
+struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
+ .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_cas = IMX6SDL_DRIVE_STRENGTH,
+ .dram_ras = IMX6SDL_DRIVE_STRENGTH,
+ .dram_reset = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdba2 = 0x00000000,
+ .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
+ .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
+struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+ .grp_ddr_type = 0x000c0000,
+ .grp_ddrmode_ctl = 0x00020000,
+ .grp_ddrpke = 0x00000000,
+ .grp_addds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
+ .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
+};
+
+/* H5T04G63AFR-PB */
+static struct mx6_ddr3_cfg h5t04g63afr = {
+ .mem_speed = 1600,
+ .density = 4,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 15,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+/* H5TQ2G63DFR-H9 */
+static struct mx6_ddr3_cfg h5tq2g63dfr = {
+ .mem_speed = 1333,
+ .density = 2,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1350,
+ .trcmin = 4950,
+ .trasmin = 3600,
+};
+
+static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = {
+ .p0_mpwldectrl0 = 0x001f001f,
+ .p0_mpwldectrl1 = 0x001f001f,
+ .p1_mpwldectrl0 = 0x001f001f,
+ .p1_mpwldectrl1 = 0x001f001f,
+ .p0_mpdgctrl0 = 0x4301030d,
+ .p0_mpdgctrl1 = 0x03020277,
+ .p1_mpdgctrl0 = 0x4300030a,
+ .p1_mpdgctrl1 = 0x02780248,
+ .p0_mprddlctl = 0x4536393b,
+ .p1_mprddlctl = 0x36353441,
+ .p0_mpwrdlctl = 0x41414743,
+ .p1_mpwrdlctl = 0x462f453f,
+};
+
+/* DDR 64bit 2GB */
+static struct mx6_ddr_sysinfo mem_q = {
+ .dsize = 2,
+ .cs1_mirror = 0,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32,
+ .ncs = 1,
+ .bi_on = 1,
+ .rtt_nom = 1,
+ .rtt_wr = 0,
+ .ralat = 5,
+ .walat = 0,
+ .mif3_mode = 3,
+ .rst_to_cke = 0x23,
+ .sde_to_rst = 0x10,
+};
+
+static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
+ .p0_mpwldectrl0 = 0x001f001f,
+ .p0_mpwldectrl1 = 0x001f001f,
+ .p1_mpwldectrl0 = 0x001f001f,
+ .p1_mpwldectrl1 = 0x001f001f,
+ .p0_mpdgctrl0 = 0x420e020e,
+ .p0_mpdgctrl1 = 0x02000200,
+ .p1_mpdgctrl0 = 0x42020202,
+ .p1_mpdgctrl1 = 0x01720172,
+ .p0_mprddlctl = 0x494c4f4c,
+ .p1_mprddlctl = 0x4a4c4c49,
+ .p0_mpwrdlctl = 0x3f3f3133,
+ .p1_mpwrdlctl = 0x39373f2e,
+};
+
+static struct mx6_mmdc_calibration mx6s_512m_mmdc_calib = {
+ .p0_mpwldectrl0 = 0x0040003c,
+ .p0_mpwldectrl1 = 0x0032003e,
+ .p0_mpdgctrl0 = 0x42350231,
+ .p0_mpdgctrl1 = 0x021a0218,
+ .p0_mprddlctl = 0x4b4b4e49,
+ .p0_mpwrdlctl = 0x3f3f3035,
+};
+
+/* DDR 64bit 1GB */
+static struct mx6_ddr_sysinfo mem_dl = {
+ .dsize = 2,
+ .cs1_mirror = 0,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32,
+ .ncs = 1,
+ .bi_on = 1,
+ .rtt_nom = 1,
+ .rtt_wr = 0,
+ .ralat = 5,
+ .walat = 0,
+ .mif3_mode = 3,
+ .rst_to_cke = 0x23,
+ .sde_to_rst = 0x10,
+};
+
+/* DDR 32bit 512MB */
+static struct mx6_ddr_sysinfo mem_s = {
+ .dsize = 1,
+ .cs1_mirror = 0,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32,
+ .ncs = 1,
+ .bi_on = 1,
+ .rtt_nom = 1,
+ .rtt_wr = 0,
+ .ralat = 5,
+ .walat = 0,
+ .mif3_mode = 3,
+ .rst_to_cke = 0x23,
+ .sde_to_rst = 0x10,
+};
+
+static void ccgr_init(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ writel(0x00C03F3F, &ccm->CCGR0);
+ writel(0x0030FC03, &ccm->CCGR1);
+ writel(0x0FFFC000, &ccm->CCGR2);
+ writel(0x3FF00000, &ccm->CCGR3);
+ writel(0x00FFF300, &ccm->CCGR4);
+ writel(0x0F0000C3, &ccm->CCGR5);
+ writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* enable AXI cache for VDOA/VPU/IPU */
+ writel(0xF00000CF, &iomux->gpr[4]);
+ /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+ writel(0x007F007F, &iomux->gpr[6]);
+ writel(0x007F007F, &iomux->gpr[7]);
+}
+
+static void spl_dram_init(void)
+{
+ if (is_cpu_type(MXC_CPU_MX6SOLO)) {
+ mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+ mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr);
+ } else if (is_cpu_type(MXC_CPU_MX6DL)) {
+ mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+ mx6_dram_cfg(&mem_dl, &mx6dl_1g_mmdc_calib, &h5tq2g63dfr);
+ } else if (is_cpu_type(MXC_CPU_MX6Q)) {
+ mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
+ mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &h5t04g63afr);
+ }
+
+ udelay(100);
+}
+
+void board_init_f(ulong dummy)
+{
+ ccgr_init();
+
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ gpr_init();
+
+ /* iomux */
+ board_early_init_f();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+#endif
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 1075c6589d5d2ecda1a94301ee4d2b6f32eb9434..90625ab9e0690b41858f44c6bdd7273b038aeafa 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -53,66 +53,66 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
- gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
+ gd->ram_size = imx_ddr_size();
return 0;
}
static iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
static iomux_v3_cfg_t const usdhc1_pads[] = {
- MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
/* Carrier MicroSD Card Detect */
- MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
/* SOM MicroSD Card Detect */
- MX6_PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static iomux_v3_cfg_t const enet_pads[] = {
- MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
/* AR8031 PHY Reset */
- MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static void setup_iomux_uart(void)
{
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+ SETUP_IOMUX_PADS(uart1_pads);
}
static void setup_iomux_enet(void)
{
- imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+ SETUP_IOMUX_PADS(enet_pads);
/* Reset AR8031 PHY */
gpio_direction_output(ETH_PHY_RESET, 0);
@@ -156,15 +156,13 @@ int board_mmc_init(bd_t *bis)
for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
switch (index) {
case 0:
- imx_iomux_v3_setup_multiple_pads(
- usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ SETUP_IOMUX_PADS(usdhc3_pads);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg[0].max_bus_width = 4;
gpio_direction_input(USDHC3_CD_GPIO);
break;
case 1:
- imx_iomux_v3_setup_multiple_pads(
- usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ SETUP_IOMUX_PADS(usdhc1_pads);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
usdhc_cfg[1].max_bus_width = 4;
gpio_direction_input(USDHC1_CD_GPIO);
@@ -218,54 +216,66 @@ int board_phy_config(struct phy_device *phydev)
}
#if defined(CONFIG_VIDEO_IPUV3)
-struct i2c_pads_info i2c2_pad_info = {
+struct i2c_pads_info mx6q_i2c2_pad_info = {
.scl = {
- .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL
+ .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
| MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12
+ .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
| MUX_PAD_CTRL(I2C_PAD_CTRL),
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
- .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA
+ .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
| MUX_PAD_CTRL(I2C_PAD_CTRL),
- .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13
+ .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+
+struct i2c_pads_info mx6dl_i2c2_pad_info = {
+ .scl = {
+ .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
+ | MUX_PAD_CTRL(I2C_PAD_CTRL),
+ .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
| MUX_PAD_CTRL(I2C_PAD_CTRL),
.gp = IMX_GPIO_NR(4, 13)
}
};
static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
- MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
- MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSync */
- MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSync */
- MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04
- | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm), /* Contrast */
- MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* DISP0_DRDY */
-
- MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
- MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
- MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
- MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
- MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
- MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
- MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
- MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
- MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
- MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
- MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
- MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
- MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
- MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
- MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
- MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
- MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
- MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
-
- MX6_PAD_SD4_DAT2__GPIO2_IO10
- | MUX_PAD_CTRL(NO_PAD_CTRL), /* DISP0_BKLEN */
- MX6_PAD_SD4_DAT3__GPIO2_IO11
- | MUX_PAD_CTRL(NO_PAD_CTRL), /* DISP0_VDDEN */
+ IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
+ IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
+ IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
+ IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
+ IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
+ IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
+ IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
+ IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
+ IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
+ IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
+ IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
+ IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
+ IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
+ IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
+ IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
+ IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
+ IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
+ IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
+ IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
+ IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
+ IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
+ IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
+ IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
+ IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
+ IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
};
static void do_enable_hdmi(struct display_info_t const *dev)
@@ -281,9 +291,7 @@ static int detect_i2c(struct display_info_t const *dev)
static void enable_fwadapt_7wvga(struct display_info_t const *dev)
{
- imx_iomux_v3_setup_multiple_pads(
- fwadapt_7wvga_pads,
- ARRAY_SIZE(fwadapt_7wvga_pads));
+ SETUP_IOMUX_PADS(fwadapt_7wvga_pads);
gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
@@ -346,7 +354,7 @@ static void setup_display(void)
writel(reg, &mxc_ccm->chsccdr);
/* Disable LCD backlight */
- imx_iomux_v3_setup_pad(MX6_PAD_DI0_PIN4__GPIO4_IO20);
+ SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
gpio_direction_input(IMX_GPIO_NR(4, 20));
}
#endif /* CONFIG_VIDEO_IPUV3 */
@@ -391,6 +399,12 @@ int board_late_init(void)
add_board_boot_modes(board_boot_modes);
#endif
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+ setenv("board_rev", "MX6Q");
+ else
+ setenv("board_rev", "MX6DL");
+#endif
return 0;
}
@@ -399,7 +413,11 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c2_pad_info);
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
+ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
+ else
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
return 0;
}
diff --git a/common/env_nand.c b/common/env_nand.c
index 9c9bb82c0faf81f3d6d6295f99ecfcfd3a1cea2b..92e0e053dfe6b57abe49156bc246e780089a4af0 100644
--- a/common/env_nand.c
+++ b/common/env_nand.c
@@ -233,6 +233,12 @@ int saveenv(void)
}
#endif /* CMD_SAVEENV */
+#if defined(CONFIG_SPL_BUILD)
+static int readenv(size_t offset, u_char *buf)
+{
+ return nand_spl_load_image(offset, CONFIG_ENV_SIZE, buf);
+}
+#else
static int readenv(size_t offset, u_char *buf)
{
size_t end = offset + CONFIG_ENV_RANGE;
@@ -266,6 +272,7 @@ static int readenv(size_t offset, u_char *buf)
return 0;
}
+#endif /* #if defined(CONFIG_SPL_BUILD) */
#ifdef CONFIG_ENV_OFFSET_OOB
int get_nand_env_oob(nand_info_t *nand, unsigned long *result)
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 5d688d6f0fcbccc0c9d153930c5414c9032d10d7..c96345eff2dc0cf9ca85c6bb50b7494e614b43db 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -76,7 +76,7 @@ static int mmc_load_image_raw_os(struct mmc *mmc)
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR,
CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS,
(void *)CONFIG_SYS_SPL_ARGS_ADDR);
- if (err) {
+ if (err == 0) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("spl: mmc block read error\n");
#endif
diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..e536646c969dc33e13f9cbd6679c41c4a4135ef7
--- /dev/null
+++ b/configs/aristainetos2_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL"
+CONFIG_ARM=y
+CONFIG_TARGET_ARISTAINETOS2=y
diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig
index f54fdd05a1628c4466ab983ab3b020dca8123bc4..460e2d022c07036327150454280cf859d79d2f1c 100644
--- a/configs/marsboard_defconfig
+++ b/configs/marsboard_defconfig
@@ -1,3 +1,5 @@
CONFIG_ARM=y
CONFIG_TARGET_EMBESTMX6BOARDS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,ENV_IS_IN_SPI_FLASH"
+CONFIG_DM=y
+CONFIG_DM_THERMAL=y
diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig
index c0b689b4612f99545789ef01dbbe1422f9e26e96..ae0036a28af32895f9e38a87015f863feae716fb 100644
--- a/configs/riotboard_defconfig
+++ b/configs/riotboard_defconfig
@@ -1,3 +1,5 @@
CONFIG_ARM=y
CONFIG_TARGET_EMBESTMX6BOARDS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024,ENV_IS_IN_MMC"
+CONFIG_DM=y
+CONFIG_DM_THERMAL=y
diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..1ccac5a63e4b8c5758edae2336b4df687dc75c37
--- /dev/null
+++ b/configs/wandboard_defconfig
@@ -0,0 +1,6 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL"
+CONFIG_ARM=y
+CONFIG_TARGET_WANDBOARD=y
+CONFIG_DM=y
+CONFIG_DM_THERMAL=y
diff --git a/configs/wandboard_dl_defconfig b/configs/wandboard_dl_defconfig
deleted file mode 100644
index 0136cdfdf9bca20f5499287bbe3464a8ea068461..0000000000000000000000000000000000000000
--- a/configs/wandboard_dl_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_WANDBOARD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024"
diff --git a/configs/wandboard_quad_defconfig b/configs/wandboard_quad_defconfig
deleted file mode 100644
index 0f9bdf936c24cc609ef9b9e4083cbd36c47eb1a4..0000000000000000000000000000000000000000
--- a/configs/wandboard_quad_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_WANDBOARD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048"
diff --git a/configs/wandboard_solo_defconfig b/configs/wandboard_solo_defconfig
deleted file mode 100644
index 57a227c9442c775bf9fe1c5401901639089bc9b6..0000000000000000000000000000000000000000
--- a/configs/wandboard_solo_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_WANDBOARD=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512"
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 81adf6f450329d38ed6179f71d2dc92460accec3..b3c50aaf3091a1f0454dfb4c311a3b07c95d18a8 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -170,6 +170,9 @@ static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed)
u8 idx = i2c_clk_div[clk_idx][1];
int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
+ if (!base)
+ return -ENODEV;
+
/* Store divider value */
writeb(idx, base + (IFDR << reg_shift));
@@ -351,6 +354,10 @@ static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
int ret;
int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
+
+ if (!i2c_bus->base)
+ return -ENODEV;
+
for (retry = 0; retry < 3; retry++) {
ret = i2c_init_transfer_(i2c_bus, chip, addr, alen);
if (ret >= 0)
@@ -503,35 +510,30 @@ static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
return ret;
}
+#if !defined(I2C2_BASE_ADDR)
+#define I2C2_BASE_ADDR 0
+#endif
+
+#if !defined(I2C3_BASE_ADDR)
+#define I2C3_BASE_ADDR 0
+#endif
+
+#if !defined(I2C4_BASE_ADDR)
+#define I2C4_BASE_ADDR 0
+#endif
+
static struct mxc_i2c_bus mxc_i2c_buses[] = {
-#if defined(CONFIG_MX25)
- { 0, IMX_I2C_BASE },
- { 1, IMX_I2C2_BASE },
- { 2, IMX_I2C3_BASE },
-#elif defined(CONFIG_MX27)
- { 0, IMX_I2C1_BASE },
- { 1, IMX_I2C2_BASE },
-#elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \
- defined(CONFIG_MX51) || defined(CONFIG_MX53) || \
- defined(CONFIG_MX6)
- { 0, I2C1_BASE_ADDR },
- { 1, I2C2_BASE_ADDR },
- { 2, I2C3_BASE_ADDR },
-#elif defined(CONFIG_LS102XA)
- { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
- { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
- { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
-#elif defined(CONFIG_VF610)
- { 0, I2C0_BASE_ADDR, I2C_QUIRK_FLAG },
-#elif defined(CONFIG_FSL_LSCH3)
+#if defined(CONFIG_LS102XA) || defined(CONFIG_FSL_LSCH3)
{ 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
{ 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
{ 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
{ 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
#else
-#error "architecture not supported"
+ { 0, I2C1_BASE_ADDR, 0 },
+ { 1, I2C2_BASE_ADDR, 0 },
+ { 2, I2C3_BASE_ADDR, 0 },
+ { 3, I2C4_BASE_ADDR, 0 },
#endif
- { }
};
struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap)
diff --git a/drivers/pwm/pwm-imx-util.c b/drivers/pwm/pwm-imx-util.c
index 79d86028de275962c78b3e728d7c420ac69b4a2b..f92c3700f8eaf686ca17f4116dffb00ec5745fb8 100644
--- a/drivers/pwm/pwm-imx-util.c
+++ b/drivers/pwm/pwm-imx-util.c
@@ -21,16 +21,12 @@ struct pwm_regs *pwm_id_to_reg(int pwm_id)
switch (pwm_id) {
case 0:
return (struct pwm_regs *)PWM1_BASE_ADDR;
- break;
case 1:
return (struct pwm_regs *)PWM2_BASE_ADDR;
- break;
case 2:
return (struct pwm_regs *)PWM3_BASE_ADDR;
- break;
case 3:
return (struct pwm_regs *)PWM4_BASE_ADDR;
- break;
default:
printf("unknown pwm_id: %d\n", pwm_id);
break;
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 40bf0275437fefbd4deaecd6934e2b4ccb2392aa..47799fc0d1fb87c5c5ffb95967264d231825d4b9 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -18,6 +18,9 @@ int pwm_init(int pwm_id, int div, int invert)
{
struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
+ if (!pwm)
+ return -1;
+
writel(0, &pwm->ir);
return 0;
}
@@ -28,6 +31,9 @@ int pwm_config(int pwm_id, int duty_ns, int period_ns)
unsigned long period_cycles, duty_cycles, prescale;
u32 cr;
+ if (!pwm)
+ return -1;
+
pwm_imx_get_parms(period_ns, duty_ns, &period_cycles, &duty_cycles,
&prescale);
@@ -47,6 +53,9 @@ int pwm_enable(int pwm_id)
{
struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
+ if (!pwm)
+ return -1;
+
setbits_le32(&pwm->cr, PWMCR_EN);
return 0;
}
@@ -55,5 +64,8 @@ void pwm_disable(int pwm_id)
{
struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
+ if (!pwm)
+ return;
+
clrbits_le32(&pwm->cr, PWMCR_EN);
}
diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
index 0bd9cfd0304587275c2e36d10198280681d7a607..0d893c9d0674e6bd4cca1be7aab94c3ee17031e6 100644
--- a/drivers/thermal/imx_thermal.c
+++ b/drivers/thermal/imx_thermal.c
@@ -12,15 +12,15 @@
#include <fuse.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
#include <dm.h>
#include <errno.h>
#include <malloc.h>
#include <thermal.h>
#include <imx_thermal.h>
-#define TEMPERATURE_MIN -40
-#define TEMPERATURE_HOT 80
-#define TEMPERATURE_MAX 125
+/* board will busyloop until this many degrees C below CPU max temperature */
+#define TEMPERATURE_HOT_DELTA 5 /* CPU maxT - 5C */
#define FACTOR0 10000000
#define FACTOR1 15976
#define FACTOR2 4297157
@@ -34,14 +34,21 @@
#define MISC0_REFTOP_SELBIASOFF (1 << 3)
#define TEMPSENSE1_MEASURE_FREQ 0xffff
+struct thermal_data {
+ unsigned int fuse;
+ int critical;
+ int minc;
+ int maxc;
+};
+
static int read_cpu_temperature(struct udevice *dev)
{
int temperature;
unsigned int reg, n_meas;
const struct imx_thermal_plat *pdata = dev_get_platdata(dev);
struct anatop_regs *anatop = (struct anatop_regs *)pdata->regs;
- unsigned int *priv = dev_get_priv(dev);
- u32 fuse = *priv;
+ struct thermal_data *priv = dev_get_priv(dev);
+ u32 fuse = priv->fuse;
int t1, n1;
u32 c1, c2;
u64 temp64;
@@ -119,13 +126,15 @@ static int read_cpu_temperature(struct udevice *dev)
int imx_thermal_get_temp(struct udevice *dev, int *temp)
{
+ struct thermal_data *priv = dev_get_priv(dev);
int cpu_tmp = 0;
cpu_tmp = read_cpu_temperature(dev);
- while (cpu_tmp > TEMPERATURE_MIN && cpu_tmp < TEMPERATURE_MAX) {
- if (cpu_tmp >= TEMPERATURE_HOT) {
- printf("CPU Temperature is %d C, too hot to boot, waiting...\n",
- cpu_tmp);
+ while (cpu_tmp > priv->minc && cpu_tmp < priv->maxc) {
+ if (cpu_tmp >= priv->critical) {
+ printf("CPU Temperature (%dC) too close to max (%dC)",
+ cpu_tmp, priv->maxc);
+ puts(" waiting...\n");
udelay(5000000);
cpu_tmp = read_cpu_temperature(dev);
} else {
@@ -147,7 +156,7 @@ static int imx_thermal_probe(struct udevice *dev)
unsigned int fuse = ~0;
const struct imx_thermal_plat *pdata = dev_get_platdata(dev);
- unsigned int *priv = dev_get_priv(dev);
+ struct thermal_data *priv = dev_get_priv(dev);
/* Read Temperature calibration data fuse */
fuse_read(pdata->fuse_bank, pdata->fuse_word, &fuse);
@@ -158,7 +167,10 @@ static int imx_thermal_probe(struct udevice *dev)
return -EPERM;
}
- *priv = fuse;
+ /* set critical cooling temp */
+ get_cpu_temp_grade(&priv->minc, &priv->maxc);
+ priv->critical = priv->maxc - TEMPERATURE_HOT_DELTA;
+ priv->fuse = fuse;
enable_thermal_clk();
@@ -170,6 +182,6 @@ U_BOOT_DRIVER(imx_thermal) = {
.id = UCLASS_THERMAL,
.ops = &imx_thermal_ops,
.probe = imx_thermal_probe,
- .priv_auto_alloc_size = sizeof(unsigned int),
+ .priv_auto_alloc_size = sizeof(struct thermal_data),
.flags = DM_FLAG_PRE_RELOC,
};
diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h
new file mode 100644
index 0000000000000000000000000000000000000000..1abaabf7e39129647ee26f343d278c070b535913
--- /dev/null
+++ b/include/configs/aristainetos-common.h
@@ -0,0 +1,276 @@
+/*
+ * (C) Copyright 2015
+ * (C) Copyright 2014
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6Q SabreSD board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __ARISTAINETOS_COMMON_CONFIG_H
+#define __ARISTAINETOS_COMMON_CONFIG_H
+
+#include "mx6_common.h"
+
+#define CONFIG_MACH_TYPE 4501
+#define CONFIG_MMCROOT "/dev/mmcblk0p1"
+#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (64 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_MXC_UART
+
+#define CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+
+/* MMC Configs */
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC_PHYADDR 0
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_MTD
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS 3
+#define CONFIG_SF_DEFAULT_SPEED 20000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
+
+/* Command definition */
+#define CONFIG_CMD_BMODE
+#define CONFIG_CMD_SETEXPR
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=u-boot.scr\0" \
+ "fit_file=/boot/system.itb\0" \
+ "loadaddr=0x12000000\0" \
+ "fit_addr_r=0x14000000\0" \
+ "uboot=/boot/u-boot.imx\0" \
+ "uboot_sz=d0000\0" \
+ "rescue_sys_addr=f0000\0" \
+ "rescue_sys_length=f10000\0" \
+ "panel=lb07wv8\0" \
+ "splashpos=m,m\0" \
+ "console=" CONFIG_CONSOLE_DEV "\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
+ "set_fit_default=fdt addr ${fit_addr_r};fdt set /configurations " \
+ "default ${board_type}\0" \
+ "get_env=mw ${loadaddr} 0 0x20000;" \
+ "mmc rescan;" \
+ "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} env.txt;" \
+ "env import -t ${loadaddr}\0" \
+ "default_env=mw ${loadaddr} 0 0x20000;" \
+ "env export -t ${loadaddr} serial# ethaddr eth1addr " \
+ "board_type panel;" \
+ "env default -a;" \
+ "env import -t ${loadaddr}\0" \
+ "loadbootscript=" \
+ "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "mmcpart=1\0" \
+ "mmcdev=0\0" \
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs addmtd addmisc set_fit_default;" \
+ "bootm ${fit_addr_r}\0" \
+ "mmc_load_fit=ext2load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \
+ "${fit_file}\0" \
+ "mmc_load_uboot=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
+ "${uboot}\0" \
+ "mmc_upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \
+ "setexpr cmp_buf ${loadaddr} + ${uboot_sz};" \
+ "setexpr uboot_maxsize ${uboot_sz} - 400;" \
+ "mw.b ${cmp_buf} 0x00 ${uboot_sz};" \
+ "run mmc_load_uboot;sf probe;sf erase 0 ${uboot_sz};" \
+ "sf write ${loadaddr} 400 ${filesize};" \
+ "sf read ${cmp_buf} 400 ${uboot_sz};" \
+ "cmp.b ${loadaddr} ${cmp_buf} ${uboot_maxsize}\0" \
+ "ubiboot=echo Booting from ubi ...; " \
+ "run ubiargs addmtd addmisc set_fit_default;" \
+ "bootm ${fit_addr_r}\0" \
+ "ubifs_load_fit=sf probe;ubi part ubi 2048;ubifsmount ubi:rootfs;" \
+ "ubifsload ${fit_addr_r} /boot/system.itb; " \
+ "imi ${fit_addr_r}\0 " \
+ "rescueargs=setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/ram rw\0 " \
+ "rescueboot=echo Booting rescue system from NOR ...; " \
+ "run rescueargs addmtd addmisc set_fit_default;" \
+ "bootm ${fit_addr_r}\0" \
+ "rescue_load_fit=sf probe;sf read ${fit_addr_r} ${rescue_sys_addr} " \
+ "${rescue_sys_length}; imi ${fit_addr_r}\0" \
+ CONFIG_EXTRA_ENV_BOARD_SETTINGS
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run mmc_load_fit; then " \
+ "run mmcboot; " \
+ "else " \
+ "if run ubifs_load_fit; then " \
+ "run ubiboot; " \
+ "else " \
+ "if run rescue_load_fit; then " \
+ "run rescueboot; " \
+ "else " \
+ "echo RESCUE SYSTEM BOOT " \
+ "FAILURE;" \
+ "fi; " \
+ "fi; " \
+ "fi; " \
+ "fi; " \
+ "else " \
+ "if run ubifs_load_fit; then " \
+ "run ubiboot; " \
+ "else " \
+ "if run rescue_load_fit; then " \
+ "run rescueboot; " \
+ "else " \
+ "echo RESCUE SYSTEM BOOT FAILURE;" \
+ "fi; " \
+ "fi; " \
+ "fi"
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
+#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
+
+#define CONFIG_STACKSIZE (128 * 1024)
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_SIZE (12 * 1024)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SECT_SIZE (0x010000)
+#define CONFIG_ENV_OFFSET (0x0d0000)
+#define CONFIG_ENV_OFFSET_REDUND (0x0e0000)
+
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+
+/* I2C */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED 100000
+#define CONFIG_SYS_I2C_SLAVE 0x7f
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x00} }
+
+/* NAND stuff */
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NAND_TRIMFFS
+#define CONFIG_NAND_MXS
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+#define CONFIG_APBH_DMA
+#define CONFIG_APBH_DMA_BURST
+#define CONFIG_APBH_DMA_BURST8
+
+/* RTC */
+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
+#define CONFIG_SYS_RTC_BUS_NUM 2
+#define CONFIG_RTC_M41T11
+#define CONFIG_CMD_DATE
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS 0
+
+/* UBI support */
+#define CONFIG_LZO
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_RBTREE
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+
+#define CONFIG_MTD_UBI_FASTMAP
+#define CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT 1
+
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_IMX_WATCHDOG
+
+#define CONFIG_FIT
+
+/* Framebuffer */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+/* check this console not needed, after test remove it */
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IPUV3_CLK 198000000
+#define CONFIG_IMX_VIDEO_SKIP
+
+#define CONFIG_CMD_BMP
+
+#define CONFIG_PWM_IMX
+#define CONFIG_IMX6_PWM_PER_CLK 66000000
+
+#endif /* __ARISTAINETOS_COMMON_CONFIG_H */
diff --git a/include/configs/aristainetos.h b/include/configs/aristainetos.h
index cc2679077630dc1c7e72822b5ffbad8807a8da0c..258866a473a87675cf7b4bc9eb9fa1884afc71a9 100644
--- a/include/configs/aristainetos.h
+++ b/include/configs/aristainetos.h
@@ -13,333 +13,31 @@
#ifndef __ARISTAINETOS_CONFIG_H
#define __ARISTAINETOS_CONFIG_H
-#define CONFIG_MX6
-
-#include "mx6_common.h"
-#include <linux/sizes.h>
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
-
-#define CONFIG_MACH_TYPE 4501
-#define CONFIG_MMCROOT "/dev/mmcblk0p1"
+#define CONFIG_SYS_BOARD_VERSION 1
#define CONFIG_HOSTNAME aristainetos
-#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
-
-#define CONFIG_SYS_GENERIC_BOARD
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (64 * SZ_1M)
+#define CONFIG_BOARDNAME "aristainetos"
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_MXC_GPIO
-
-#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART5_BASE
#define CONFIG_CONSOLE_DEV "ttymxc4"
-#define CONFIG_CMD_FUSE
-#define CONFIG_MXC_OCOTP
-
-/* MMC Configs */
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-
-#define CONFIG_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_FEC_MXC
-#define CONFIG_MII
-#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE RMII
-#define CONFIG_ETHPRIME "FEC"
-#define CONFIG_FEC_MXC_PHYADDR 0
-
-#define CONFIG_PHYLIB
-#define CONFIG_PHY_MICREL
-#define CONFIG_CMD_SF
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_MTD
-#define CONFIG_SPI_FLASH_STMICRO
-#define CONFIG_MXC_SPI
-#define CONFIG_SF_DEFAULT_BUS 3
#define CONFIG_SF_DEFAULT_CS 0
-#define CONFIG_SF_DEFAULT_SPEED 20000000
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-#define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-/* Command definition */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BMODE
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_SETEXPR
-#undef CONFIG_CMD_IMLS
-
-#define CONFIG_BOOTDELAY 3
-
-#define CONFIG_LOADADDR 0x12000000
-#define CONFIG_SYS_TEXT_BASE 0x17800000
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "script=u-boot.scr\0" \
- "fit_file=/boot/system.itb\0" \
- "loadaddr=0x12000000\0" \
- "fit_addr_r=0x14000000\0" \
- "uboot=/boot/u-boot.imx\0" \
- "uboot_sz=d0000\0" \
- "rescue_sys_addr=f0000\0" \
- "rescue_sys_length=f10000\0" \
+#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \
"board_type=aristainetos7@1\0" \
- "panel=lb07wv8\0" \
- "splashpos=m,m\0" \
- "console=" CONFIG_CONSOLE_DEV "\0" \
- "fdt_high=0xffffffff\0" \
- "initrd_high=0xffffffff\0" \
"mtdids=nand0=gpmi-nand,nor0=spi3.0\0" \
"mtdparts=mtdparts=spi3.0:832k(u-boot),64k(env),64k(env-red)," \
"-(rescue-system);gpmi-nand:-(ubi)\0" \
"addmisc=setenv bootargs ${bootargs} consoleblank=0\0" \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
- "set_fit_default=fdt addr ${fit_addr_r};fdt set /configurations " \
- "default ${board_type}\0" \
- "get_env=mw ${loadaddr} 0 0x20000;" \
- "mmc rescan;" \
- "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} env.txt;" \
- "env import -t ${loadaddr}\0" \
- "default_env=mw ${loadaddr} 0 0x20000;" \
- "env export -t ${loadaddr} serial# ethaddr eth1addr " \
- "board_type panel;" \
- "env default -a;" \
- "env import -t ${loadaddr}\0" \
- "loadbootscript=" \
- "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
- "bootscript=echo Running bootscript from mmc ...; " \
- "source\0" \
- "mmcpart=1\0" \
- "mmcdev=0\0" \
- "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
- "mmcargs=setenv bootargs console=${console},${baudrate} " \
- "root=${mmcroot}\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs addmtd addmisc set_fit_default;" \
- "bootm ${fit_addr_r}\0" \
- "mmc_load_fit=ext2load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \
- "${fit_file}\0" \
- "mmc_load_uboot=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
- "${uboot}\0" \
- "mmc_upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \
- "setexpr cmp_buf ${loadaddr} + ${uboot_sz};" \
- "setexpr uboot_maxsize ${uboot_sz} - 400;" \
- "mw.b ${cmp_buf} 0x00 ${uboot_sz};" \
- "run mmc_load_uboot;sf probe;sf erase 0 ${uboot_sz};" \
- "sf write ${loadaddr} 400 ${filesize};" \
- "sf read ${cmp_buf} 400 ${uboot_sz};" \
- "cmp.b ${loadaddr} ${cmp_buf} ${uboot_maxsize}\0" \
"ubiargs=setenv bootargs console=${console},${baudrate} " \
- "ubi.mtd=0,2048 root=ubi0:rootfs rootfstype=ubifs\0 " \
- "ubiboot=echo Booting from ubi ...; " \
- "run ubiargs addmtd addmisc set_fit_default;" \
- "bootm ${fit_addr_r}\0" \
- "ubifs_load_fit=sf probe;ubi part ubi 2048;ubifsmount ubi:rootfs;" \
- "ubifsload ${fit_addr_r} /boot/system.itb; " \
- "imi ${fit_addr_r}\0 " \
- "rescueargs=setenv bootargs console=${console},${baudrate} " \
- "root=/dev/ram rw\0 " \
- "rescueboot=echo Booting rescue system from NOR ...; " \
- "run rescueargs addmtd addmisc set_fit_default;" \
- "bootm ${fit_addr_r}\0" \
- "rescue_load_fit=sf probe;sf read ${fit_addr_r} ${rescue_sys_addr} " \
- "${rescue_sys_length}; imi ${fit_addr_r}\0 "
-
-#define CONFIG_BOOTCOMMAND \
- "mmc dev ${mmcdev};" \
- "if mmc rescan; then " \
- "if run loadbootscript; then " \
- "run bootscript; " \
- "else " \
- "if run mmc_load_fit; then " \
- "run mmcboot; " \
- "else " \
- "if run ubifs_load_fit; then " \
- "run ubiboot; " \
- "else " \
- "if run rescue_load_fit; then " \
- "run rescueboot; " \
- "else " \
- "echo RESCUE SYSTEM BOOT " \
- "FAILURE;" \
- "fi; " \
- "fi; " \
- "fi; " \
- "fi; " \
- "else " \
- "if run ubifs_load_fit; then " \
- "run ubiboot; " \
- "else " \
- "if run rescue_load_fit; then " \
- "run rescueboot; " \
- "else " \
- "echo RESCUE SYSTEM BOOT FAILURE;" \
- "fi; " \
- "fi; " \
- "fi"
-
-#define CONFIG_ARP_TIMEOUT 200UL
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE 256
-
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
-#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_STACKSIZE (128 * 1024)
-
-/* Physical Memory Map */
-#define CONFIG_NR_DRAM_BANKS 1
-#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
-
-#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
-#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-
-#define CONFIG_SYS_INIT_SP_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
- (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH
-
-#define CONFIG_ENV_SIZE (12 * 1024)
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
-#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
-#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
-#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
-#define CONFIG_ENV_SECT_SIZE (0x010000)
-#define CONFIG_ENV_OFFSET (0x0d0000)
-#define CONFIG_ENV_OFFSET_REDUND (0x0e0000)
-
-#define CONFIG_OF_LIBFDT
-
-#define CONFIG_CMD_CACHE
-
-#define CONFIG_SYS_FSL_USDHC_NUM 2
-
-#define CONFIG_CMD_I2C
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_MXC
-#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
-#define CONFIG_SYS_I2C_SPEED 100000
-#define CONFIG_SYS_I2C_SLAVE 0x7f
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x00} }
-
-#define CONFIG_CMD_GPIO
-#define CONFIG_GPIO_ENABLE_SPI_FLASH IMX_GPIO_NR(2, 15)
-
-/* NAND stuff */
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NAND_TRIMFFS
-#define CONFIG_NAND_MXS
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE 0x40000000
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* DMA stuff, needed for GPMI/MXS NAND support */
-#define CONFIG_APBH_DMA
-#define CONFIG_APBH_DMA_BURST
-#define CONFIG_APBH_DMA_BURST8
-
-/* RTC */
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_SYS_RTC_BUS_NUM 2
-#define CONFIG_RTC_M41T11
-#define CONFIG_CMD_DATE
-
-/* USB Configs */
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_FAT
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_MX6
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
-#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
-#define CONFIG_MXC_USB_FLAGS 0
+ "ubi.mtd=0,2048 root=ubi0:rootfs rootfstype=ubifs\0 "
#define ARISTAINETOS_USB_OTG_PWR IMX_GPIO_NR(4, 15)
#define ARISTAINETOS_USB_H1_PWR IMX_GPIO_NR(3, 31)
+#define CONFIG_GPIO_ENABLE_SPI_FLASH IMX_GPIO_NR(2, 15)
-/* UBI support */
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_PARTITIONS
-#define CONFIG_MTD_DEVICE
-#define CONFIG_RBTREE
-#define CONFIG_LZO
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-
-#define CONFIG_MTD_UBI_FASTMAP
-#define CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT 1
-
-#define CONFIG_HW_WATCHDOG
-#define CONFIG_IMX_WATCHDOG
-
-#define CONFIG_FIT
-
-/* Framebuffer */
-#define CONFIG_VIDEO
-#define CONFIG_VIDEO_IPUV3
-/* check this console not needed, after test remove it */
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
-#define CONFIG_VIDEO_BMP_RLE8
-#define CONFIG_SPLASH_SCREEN
-#define CONFIG_SPLASH_SCREEN_ALIGN
-#define CONFIG_BMP_16BPP
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_VIDEO_BMP_LOGO
-#define CONFIG_IPUV3_CLK 198000000
-#define CONFIG_IMX_VIDEO_SKIP
-
-#define CONFIG_CMD_BMP
+#include "aristainetos-common.h"
-#define CONFIG_PWM_IMX
-#define CONFIG_IMX6_PWM_PER_CLK 66000000
#endif /* __ARISTAINETOS_CONFIG_H */
diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h
new file mode 100644
index 0000000000000000000000000000000000000000..faeafe2dda25b7ed8af05a73d070dd82c2c63d60
--- /dev/null
+++ b/include/configs/aristainetos2.h
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2015
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on:
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6DL aristainetos2 board.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __ARISTAINETOS2_CONFIG_H
+#define __ARISTAINETOS2_CONFIG_H
+
+#define CONFIG_SYS_BOARD_VERSION 2
+#define CONFIG_HOSTNAME aristainetos2
+#define CONFIG_BOARDNAME "aristainetos2"
+
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_MXC_UART_BASE UART2_BASE
+#define CONFIG_CONSOLE_DEV "ttymxc1"
+
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_PHY_MICREL_KSZ9031
+
+#define CONFIG_SF_DEFAULT_CS 1
+
+#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \
+ "board_type=aristainetos2_7@1\0" \
+ "nor_bootdelay=-2\0" \
+ "mtdids=nand0=gpmi-nand,nor0=spi3.1\0" \
+ "mtdparts=mtdparts=spi3.1:832k(u-boot),64k(env),64k(env-red)," \
+ "-(rescue-system);gpmi-nand:-(ubi)\0" \
+ "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0\0" \
+ "ubiargs=setenv bootargs console=${console},${baudrate} " \
+ "ubi.mtd=0,4096 root=ubi0:rootfs rootfstype=ubifs\0 "
+
+#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
+
+#define ARISTAINETOS_USB_OTG_PWR IMX_GPIO_NR(4, 15)
+#define ARISTAINETOS_USB_H1_PWR IMX_GPIO_NR(1, 0)
+#define CONFIG_GPIO_ENABLE_SPI_FLASH IMX_GPIO_NR(2, 15)
+
+/* Framebuffer */
+#define CONFIG_SYS_LDB_CLOCK 33246000
+#define CONFIG_LG4573
+
+#define CONFIG_CMD_BMP
+
+#define CONFIG_PWM_IMX
+#define CONFIG_IMX6_PWM_PER_CLK 66000000
+
+#include "aristainetos-common.h"
+
+#endif /* __ARISTAINETOS2_CONFIG_H */
diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h
index b189bf116f316649aa6c9309fcc2194fea82cd1d..dd06c05b8e05b6439b11e96f7f79693fedc94a4a 100644
--- a/include/configs/cgtqmx6eval.h
+++ b/include/configs/cgtqmx6eval.h
@@ -13,64 +13,25 @@
#ifndef __CONFIG_CGTQMX6EVAL_H
#define __CONFIG_CGTQMX6EVAL_H
-#define CONFIG_MX6
-
#include "mx6_common.h"
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define CONFIG_MACH_TYPE 4122
-#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MISC_INIT_R
-#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART2_BASE
/* MMC Configs */
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-
/* Miscellaneous commands */
#define CONFIG_CMD_BMODE
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/* Command definition */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_IMLS
-
-#define CONFIG_BOOTDELAY 3
-
-#define CONFIG_LOADADDR 0x12000000
-#define CONFIG_SYS_TEXT_BASE 0x17800000
-
#define CONFIG_DEFAULT_FDT_FILE "imx6q-congatec.dtb"
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -127,25 +88,15 @@
"else echo ERR: Fail to boot from mmc; fi"
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "CGT-QMX6-Quad U-Boot > "
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE 256
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x10010000
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-#define CONFIG_CMDLINE_EDITING
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
@@ -160,9 +111,7 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH
-
+/* Environment organization */
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_ENV_IS_IN_MMC
@@ -170,11 +119,4 @@
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_OF_LIBFDT
-#define CONFIG_CMD_BOOTZ
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-#define CONFIG_CMD_CACHE
-#endif
-
#endif /* __CONFIG_CGTQMX6EVAL_H */
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index d6e5a2b2435f71c00d09aef61597afb899545e8b..a3908d0ef514d029bbafc2732d5f0a1911346577 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -11,40 +11,20 @@
#ifndef __CONFIG_CM_FX6_H
#define __CONFIG_CM_FX6_H
-#include <asm/arch/imx-regs.h>
-#include <config_distro_defaults.h>
#include "mx6_common.h"
/* Machine config */
-#define CONFIG_MX6
#define CONFIG_SYS_LITTLE_ENDIAN
#define CONFIG_MACH_TYPE 4273
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_CMD_GPIO
-#endif
-
-/* Display information on boot */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_TIMESTAMP
-
/* CMD */
-#include <config_cmd_default.h>
#define CONFIG_CMD_GREPENV
-#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_XIMG
#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_IMLS
/* MMC */
-#define CONFIG_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_USDHC_NUM 3
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
@@ -70,14 +50,10 @@
/* Shell */
#define CONFIG_SYS_PROMPT "CM-FX6 # "
-#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
/* SPI flash */
-#define CONFIG_SYS_NO_FLASH
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_BUS 0
#define CONFIG_SF_DEFAULT_CS 0
@@ -85,7 +61,6 @@
#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
/* Environment */
-#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
@@ -262,22 +237,11 @@
#define CONFIG_DWC_AHSATA_PORT_ID 0
#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
-/* GPIO */
-#define CONFIG_MXC_GPIO
-
/* Boot */
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_LOADADDR 0x10800000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
#define CONFIG_SERIAL_TAG
/* misc */
-#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_STACKSIZE (128 * 1024)
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */
diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h
index e9f5bed9ffc27637ecd4b42454076e6a61330d31..56950e05dbbb243b5be5c6c29c00ee2317ad9afd 100644
--- a/include/configs/embestmx6boards.h
+++ b/include/configs/embestmx6boards.h
@@ -13,36 +13,19 @@
#ifndef __RIOTBOARD_CONFIG_H
#define __RIOTBOARD_CONFIG_H
-#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
-
-#include "mx6_common.h"
-#include <linux/sizes.h>
-
-#define CONFIG_SYS_GENERIC_BOARD
-
#define CONFIG_MXC_UART_BASE UART2_BASE
#define CONFIG_CONSOLE_DEV "ttymxc1"
#define CONFIG_MMCROOT "/dev/mmcblk1p2"
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
-#define CONFIG_MX6
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
+#define CONFIG_IMX6_THERMAL
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
@@ -71,15 +54,8 @@
#define CONFIG_MXC_USB_FLAGS 0
/* MMC Configs */
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_BOUNCE_BUFFER
-
#define CONFIG_FEC_MXC
#define CONFIG_MII
#define IMX_FEC_BASE ENET_BASE_ADDR
@@ -101,39 +77,21 @@
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#endif
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
/* Command definition */
-#include <config_cmd_default.h>
#undef CONFIG_CMD_FPGA
#define CONFIG_CMD_BMODE
#define CONFIG_CMD_SETEXPR
-#undef CONFIG_CMD_IMLS
-
-#define CONFIG_LOADADDR 0x12000000
-#define CONFIG_SYS_TEXT_BASE 0x17800000
#define CONFIG_ARP_TIMEOUT 200UL
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_SYS_CBSIZE 256
-
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x10010000
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
#define CONFIG_STACKSIZE (128 * 1024)
/* Physical Memory Map */
@@ -149,9 +107,7 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH
-
+/* Environment organization */
#define CONFIG_ENV_SIZE (8 * 1024)
#if defined(CONFIG_ENV_IS_IN_MMC)
@@ -173,10 +129,6 @@
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
-#define CONFIG_CMD_CACHE
-#endif
-
/* Framebuffer */
#define CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
@@ -195,6 +147,7 @@
#define CONFIG_IMX_VIDEO_SKIP
#include <config_distro_defaults.h>
+#include "mx6_common.h"
/* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
* 1M script, 1M pxe and the ramdisk at the end */
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index b20b3388ef62d1c28eca608810fd606adb456967..406bf2e53d4a0e82e5f7b20bcb07f65dacfc207f 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -11,35 +11,36 @@
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
-#define CONFIG_SPL_FAT_SUPPORT
-/*
-#define CONFIG_SPL_SATA_SUPPORT
-*/
+#define CONFIG_SPL_POWER_SUPPORT
/* Location in NAND to read U-Boot from */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS (14 * 1024 * 1024)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (14 * SZ_1M)
+
+/* Falcon Mode */
+#define CONFIG_CMD_SPL
+#define CONFIG_SPL_OS_BOOT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
+#define CONFIG_CMD_SPL_WRITE_SIZE (128 * SZ_1K)
+
+/* Falcon Mode - NAND support: args@17MB kernel@18MB */
+#define CONFIG_CMD_SPL_NAND_OFS (17 * SZ_1M)
+#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS (18 * SZ_1M)
+
+/* Falcon Mode - MMC support: args@1MB kernel@2MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */
#include "imx6_spl.h" /* common IMX6 SPL configuration */
#include "mx6_common.h"
-#define CONFIG_MX6
-#define CONFIG_DISPLAY_CPUINFO /* display cpu info */
-#define CONFIG_DISPLAY_BOARDINFO_LATE /* display board info (after reloc) */
#define CONFIG_MACH_TYPE 4520 /* Gateworks Ventana Platform */
-#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
-
-/* ATAGs */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
+/* Serial ATAG */
#define CONFIG_SERIAL_TAG
-#define CONFIG_REVISION_TAG
-
-#define CONFIG_SYS_GENERIC_BOARD
/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
/* Init Functions */
#define CONFIG_BOARD_EARLY_INIT_F
@@ -116,22 +117,11 @@
#define CONFIG_I2C_EDID
/* MMC Configs */
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 1
-#define CONFIG_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_BOUNCE_BUFFER
/* Filesystem support */
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
#define CONFIG_CMD_UBIFS
-#define CONFIG_DOS_PARTITION
/*
* SATA Configs
@@ -169,8 +159,6 @@
#define CONFIG_POWER_LTC3676_I2C_ADDR 0x3c
/* Various command support */
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
@@ -178,12 +166,10 @@
#define CONFIG_CMD_BMODE /* set eFUSE shadow for a boot dev and reset */
#define CONFIG_CMD_HDMIDETECT /* detect HDMI output device */
#define CONFIG_CMD_SETEXPR
-#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_GSC
#define CONFIG_CMD_EECONFIG /* Gateworks EEPROM config cmd */
#define CONFIG_CMD_UBI
#define CONFIG_RBTREE
-#define CONFIG_LZO
#define CONFIG_CMD_FUSE /* eFUSE read/write support */
#ifdef CONFIG_CMD_FUSE
#define CONFIG_MXC_OCOTP
@@ -249,30 +235,17 @@
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
-/* serial console (ttymxc1,115200) */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "Ventana > "
-#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_CMDLINE_EDITING
#define CONFIG_HWCONFIG
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Memory configuration */
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x10010000
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
-#define CONFIG_SYS_TEXT_BASE 0x17800000
-#define CONFIG_SYS_LOAD_ADDR 0x12000000
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
@@ -286,12 +259,10 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH /* no NOR flash */
-
/*
* MTD Command for mtdparts
*/
+#define CONFIG_LZO
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
@@ -305,26 +276,26 @@
#endif
/* Persistent Environment Config */
-#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
#ifdef CONFIG_SPI_FLASH
#define CONFIG_ENV_IS_IN_SPI_FLASH
#else
#define CONFIG_ENV_IS_IN_NAND
#endif
#if defined(CONFIG_ENV_IS_IN_MMC)
- #define CONFIG_ENV_OFFSET (6 * 64 * 1024)
- #define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
+ #define CONFIG_ENV_OFFSET (709 * SZ_1K)
+ #define CONFIG_ENV_SIZE (128 * SZ_1K)
+ #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + (128 * SZ_1K))
#elif defined(CONFIG_ENV_IS_IN_NAND)
- #define CONFIG_ENV_OFFSET (16 << 20)
- #define CONFIG_ENV_SECT_SIZE (128 << 10)
+ #define CONFIG_ENV_OFFSET (16 * SZ_1M)
+ #define CONFIG_ENV_SECT_SIZE (128 * SZ_1K)
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
- #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + (512 << 10))
+ #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + (512 * SZ_1K))
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
- #define CONFIG_ENV_OFFSET (512 * 1024)
- #define CONFIG_ENV_SECT_SIZE (64 * 1024)
- #define CONFIG_ENV_SIZE (8 * 1024)
+ #define CONFIG_ENV_OFFSET (512 * SZ_1K)
+ #define CONFIG_ENV_SECT_SIZE (64 * SZ_1K)
+ #define CONFIG_ENV_SIZE (8 * SZ_1K)
#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
@@ -332,8 +303,6 @@
#endif
/* Environment */
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_IPADDR 192.168.1.1
#define CONFIG_SERVERIP 192.168.1.146
#define HWCONFIG_DEFAULT \
@@ -486,11 +455,6 @@
/* Device Tree Support */
#define CONFIG_OF_BOARD_SETUP
-#define CONFIG_OF_LIBFDT
#define CONFIG_FDT_FIXUP_PARTITIONS
-#ifndef CONFIG_SYS_DCACHE_OFF
- #define CONFIG_CMD_CACHE
-#endif
-
#endif /* __CONFIG_H */
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index e0528ce4b928839ce1619d6694e3b08f9be58f57..233c6d2e88f46368a699bb028bf481d3c9831102 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -31,4 +31,78 @@
#define CONFIG_MP
#define CONFIG_MXC_GPT_HCLK
+#define CONFIG_SYS_NO_FLASH
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
+#include <config_cmd_default.h>
+
+#ifndef CONFIG_MX6
+#define CONFIG_MX6
+#endif
+
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_SYS_GENERIC_BOARD
+
+/* ATAGs */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Boot options */
+#define CONFIG_LOADADDR 0x12000000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0x17800000
+#endif
+#ifndef CONFIG_BOOTDELAY
+#define CONFIG_BOOTDELAY 3
+#endif
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* Filesystems and image support */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_SUPPORT_RAW_INITRD
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 512
+#define CONFIG_SYS_MAXARGS 32
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+/* GPIO */
+#define CONFIG_MXC_GPIO
+#define CONFIG_CMD_GPIO
+
+/* MMC */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+
#endif
diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h
index b6f9d4e580b75cb957937de1a2256a2ab2257a33..21c3f960aef391f9604f803dad73ad8d4468fedc 100644
--- a/include/configs/mx6cuboxi.h
+++ b/include/configs/mx6cuboxi.h
@@ -8,45 +8,23 @@
#ifndef __MX6CUBOXI_CONFIG_H
#define __MX6CUBOXI_CONFIG_H
-#include <linux/sizes.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
#include "mx6_common.h"
-#define CONFIG_MX6
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#include "imx6_spl.h"
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
#define CONFIG_IMX6_THERMAL
-#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
#define CONFIG_CMD_FUSE
#define CONFIG_MXC_OCOTP
/* MMC Configs */
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
-#define CONFIG_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
/* Ethernet Configuration */
#define CONFIG_FEC_MXC
@@ -61,11 +39,6 @@
#define CONFIG_PHYLIB
#define CONFIG_PHY_ATHEROS
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
/* Framebuffer */
#define CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
@@ -107,19 +80,9 @@
"setenv stderr serial; " \
"fi;"
-#define CONFIG_SYS_NO_FLASH
-
/* Command definition */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_SETEXPR
-#define CONFIG_BOOTDELAY 1
-
-#define CONFIG_LOADADDR 0x12000000
-#define CONFIG_SYS_TEXT_BASE 0x17800000
-
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_CONSOLE_DEV "ttymxc0"
#define CONFIG_MMCROOT "/dev/mmcblk0p2"
@@ -229,12 +192,8 @@
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
#define CONFIG_CMDLINE_EDITING
/* Physical Memory Map */
@@ -253,7 +212,4 @@
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (8 * 64 * 1024)
-#define CONFIG_OF_LIBFDT
-#define CONFIG_CMD_CACHE
-
#endif /* __MX6CUBOXI_CONFIG_H */
diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
index 5412dd3c51dc958e39333f06ac29eab291d072ef..20b1f9c52f2d0b1f06a9eef58bd8aee67a40723a 100644
--- a/include/configs/mx6qarm2.h
+++ b/include/configs/mx6qarm2.h
@@ -9,43 +9,20 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MX6
-
#include "mx6_common.h"
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-#include <asm/arch/imx-regs.h>
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#define CONFIG_SYS_GENERIC_BOARD
-
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART4_BASE
/* MMC Configs */
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
@@ -56,21 +33,6 @@
#define CONFIG_FEC_XCV_TYPE RGMII
#define CONFIG_FEC_MXC_PHYADDR 0
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/* Command definition */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_IMLS
-
-#define CONFIG_BOOTDELAY 3
-
-#define CONFIG_LOADADDR 0x12000000
-#define CONFIG_SYS_TEXT_BASE 0x17800000
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
@@ -148,21 +110,9 @@
#define CONFIG_ARP_TIMEOUT 200UL
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE 256
-
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x10010000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-#define CONFIG_CMDLINE_EDITING
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
@@ -176,17 +126,12 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH
-
+/* Environment organization */
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1
-#define CONFIG_OF_LIBFDT
-#define CONFIG_CMD_BOOTZ
-
/* USB Configs */
#define CONFIG_CMD_USB
#ifdef CONFIG_CMD_USB
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index b72522bf522d38b11151b4dff47aa57c4a24c796..6a37ae738490677cc27fb0000f2729ae800e2b97 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -9,32 +9,15 @@
#ifndef __MX6QSABRE_COMMON_CONFIG_H
#define __MX6QSABRE_COMMON_CONFIG_H
-#define CONFIG_MX6
-
#include "mx6_common.h"
-#include <linux/sizes.h>
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
#define CONFIG_IMX6_THERMAL
-#define CONFIG_SYS_GENERIC_BOARD
-
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
@@ -44,20 +27,8 @@
#endif
/* MMC Configs */
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
@@ -83,23 +54,9 @@
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#endif
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
/* Command definition */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_BMODE
-#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_SETEXPR
-#undef CONFIG_CMD_IMLS
-
-#define CONFIG_BOOTDELAY 1
-
-#define CONFIG_LOADADDR 0x12000000
-#define CONFIG_SYS_TEXT_BASE 0x17800000
#ifdef CONFIG_SUPPORT_EMMC_BOOT
#define EMMC_ENV \
@@ -211,22 +168,10 @@
#define CONFIG_ARP_TIMEOUT 200UL
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x10010000
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-#define CONFIG_CMDLINE_EDITING
#define CONFIG_STACKSIZE (128 * 1024)
/* Physical Memory Map */
@@ -242,9 +187,7 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH
-
+/* Environment organization */
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_ENV_IS_IN_MMC
@@ -253,12 +196,6 @@
#define CONFIG_ENV_OFFSET (8 * 64 * 1024)
#endif
-#define CONFIG_OF_LIBFDT
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-#define CONFIG_CMD_CACHE
-#endif
-
/* Framebuffer */
#define CONFIG_VIDEO
#define CONFIG_VIDEO_IPUV3
diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
index dab2fd2ea2b399808580ebd2802cc38a9f383c06..41162ca202160e86749284e20f99e5f4ac88955c 100644
--- a/include/configs/mx6sabresd.h
+++ b/include/configs/mx6sabresd.h
@@ -9,9 +9,6 @@
#ifndef __MX6QSABRESD_CONFIG_H
#define __MX6QSABRESD_CONFIG_H
-#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
-
#ifdef CONFIG_SPL
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index cd023de287dfee998da09edcca20b2ac663c1e80..2b8bb2a50deeb8a68cbb45fa897118d2f2291aa6 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -9,45 +9,22 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
-#include <linux/sizes.h>
#include "mx6_common.h"
-#define CONFIG_MX6
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#define MACH_TYPE_MX6SLEVK 4307
#define CONFIG_MACH_TYPE MACH_TYPE_MX6SLEVK
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-#define CONFIG_SYS_GENERIC_BOARD
-
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
/* MMC Configs */
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
-#define CONFIG_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-
/* I2C Configs */
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
@@ -75,21 +52,6 @@
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/* Command definition */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_IMLS
-
-#define CONFIG_BOOTDELAY 3
-
-#define CONFIG_LOADADDR 0x82000000
-#define CONFIG_SYS_TEXT_BASE 0x87800000
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
@@ -165,20 +127,9 @@
"else run netboot; fi"
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE 256
-
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_512M)
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-#define CONFIG_CMDLINE_EDITING
#define CONFIG_STACKSIZE SZ_128K
/* Physical Memory Map */
@@ -195,9 +146,7 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH
-
+/* Environment organization */
#define CONFIG_ENV_SIZE SZ_8K
#if defined CONFIG_SYS_BOOT_SPINOR
@@ -213,13 +162,6 @@
#define CONFIG_ENV_IS_IN_MMC
#endif
-#define CONFIG_OF_LIBFDT
-#define CONFIG_CMD_BOOTZ
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-#define CONFIG_CMD_CACHE
-#endif
-
#define CONFIG_CMD_SF
#ifdef CONFIG_CMD_SF
#define CONFIG_SPI_FLASH
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 248303c3211f0bf78a714072280223d8e8f003d9..46e126276cee87df01846285f7c7e9afbd87d388 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -10,50 +10,22 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/arch/imx-regs.h>
-#include <linux/sizes.h>
#include "mx6_common.h"
-#define CONFIG_MX6
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
#ifdef CONFIG_SPL
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#include "imx6_spl.h"
#endif
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_SYS_GENERIC_BOARD
-
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/* Command definition */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_IMLS
-
-#define CONFIG_BOOTDELAY 3
-
-#define CONFIG_LOADADDR 0x80800000
-#define CONFIG_SYS_TEXT_BASE 0x87800000
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
@@ -129,20 +101,9 @@
"else run netboot; fi"
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE 1024
-
-#define CONFIG_SYS_MAXARGS 256
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-#define CONFIG_CMDLINE_EDITING
#define CONFIG_STACKSIZE SZ_128K
/* Physical Memory Map */
@@ -160,18 +121,8 @@
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* MMC Configuration */
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
-#define CONFIG_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-
/* I2C Configs */
#define CONFIG_CMD_I2C
#define CONFIG_SYS_I2C
@@ -233,9 +184,6 @@
#define CONFIG_MXC_OCOTP
#endif
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH
-
#define CONFIG_CMD_TIME
#define CONFIG_FSL_QSPI
@@ -260,13 +208,6 @@
#define CONFIG_ENV_SIZE SZ_8K
#define CONFIG_ENV_IS_IN_MMC
-#define CONFIG_OF_LIBFDT
-#define CONFIG_CMD_BOOTZ
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-#define CONFIG_CMD_CACHE
-#endif
-
#define CONFIG_SYS_FSL_USDHC_NUM 3
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_SYS_MMC_ENV_DEV 2 /*USDHC4*/
diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index eaa2c2cd363d4ec4c5713187ad7b8ee0b4080f61..9313b9ff3d541866760a7c03dcc26476fe2605a2 100644
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -11,28 +11,14 @@
#define __CONFIG_H
#include "mx6_common.h"
-#define CONFIG_MX6
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MACH_TYPE 3769
-#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_SYS_GENERIC_BOARD
-
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MISC_INIT_R
-#define CONFIG_MXC_GPIO
-#define CONFIG_CMD_GPIO
#define CONFIG_CI_UDC
#define CONFIG_USBD_HS
#define CONFIG_USB_GADGET_DUALSPEED
@@ -68,21 +54,9 @@
#define CONFIG_I2C_EDID
/* MMC Configs */
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-
#ifdef CONFIG_MX6Q
#define CONFIG_CMD_SATA
#endif
@@ -115,7 +89,6 @@
/* USB Configs */
#define CONFIG_CMD_USB
-#define CONFIG_CMD_FAT
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MX6
#define CONFIG_USB_STORAGE
@@ -153,23 +126,8 @@
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/* Command definition */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_IMLS
-
-#define CONFIG_BOOTDELAY 1
-
#define CONFIG_PREBOOT ""
-#define CONFIG_LOADADDR 0x12000000
-#define CONFIG_SYS_TEXT_BASE 0x17800000
-
#ifdef CONFIG_CMD_SATA
#define CONFIG_DRIVE_SATA "sata "
#else
@@ -324,22 +282,10 @@
#endif
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT "U-Boot > "
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SYS_MAXARGS 48
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x10010000
#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-#define CONFIG_CMDLINE_EDITING
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
@@ -353,9 +299,7 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH
-
+/* Environment organization */
#define CONFIG_ENV_SIZE (8 * 1024)
#if defined(CONFIG_SABRELITE)
@@ -376,23 +320,12 @@
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
#endif
-#define CONFIG_OF_LIBFDT
-#define CONFIG_CMD_BOOTZ
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-#define CONFIG_CMD_CACHE
-#endif
-
#define CONFIG_CMD_BMP
#define CONFIG_CMD_TIME
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_ALT_MEMTEST
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_SUPPORT_RAW_INITRD
-#define CONFIG_CMD_FS_GENERIC
-
/*
* PCI express
*/
diff --git a/include/configs/novena.h b/include/configs/novena.h
index 425db8adee409aa757c9859d66cc74fd93b4b13a..1f9326961c11c45954f0ae504482d0aafde32f0c 100644
--- a/include/configs/novena.h
+++ b/include/configs/novena.h
@@ -10,41 +10,22 @@
#define __CONFIG_H
/* System configurations */
-#define CONFIG_MX6
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_MISC_INIT_R
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DOS_PARTITION
-#define CONFIG_FAT_WRITE
#define CONFIG_FIT
#define CONFIG_KEYBOARD
-#define CONFIG_MXC_GPIO
-#define CONFIG_OF_LIBFDT
-#define CONFIG_SYS_GENERIC_BOARD
-#define CONFIG_SYS_NO_FLASH
-#include "configs/mx6_common.h"
-#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
-#include <config_cmd_default.h>
+#include "mx6_common.h"
/* U-Boot Commands */
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BMODE
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
#define CONFIG_CMD_I2C
#define CONFIG_CMD_FUSE
#define CONFIG_CMD_MII
-#define CONFIG_CMD_MMC
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING
@@ -55,18 +36,9 @@
#define CONFIG_VIDEO
/* U-Boot general configurations */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
-#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
- /* Boot argument buffer size */
#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
-#define CONFIG_AUTO_COMPLETE /* Command auto complete */
-#define CONFIG_CMDLINE_EDITING /* Command history etc */
-#define CONFIG_SYS_HUSH_PARSER
/* U-Boot environment */
-#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_SIZE (16 * 1024)
/*
* Environment is on MMC, starting at offset 512KiB from start of the card.
@@ -86,12 +58,9 @@
#endif
/* Booting Linux */
-#define CONFIG_BOOTDELAY 5
#define CONFIG_BOOTFILE "fitImage"
#define CONFIG_BOOTARGS "console=ttymxc1,115200 "
#define CONFIG_BOOTCOMMAND "run net_nfs"
-#define CONFIG_LOADADDR 0x18000000
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_HOSTNAME novena
/* Physical Memory Map */
@@ -118,11 +87,6 @@
#define CONFIG_SPL_MMC_SUPPORT
#include "imx6_spl.h" /* common IMX6 SPL configuration */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
/* Ethernet Configuration */
#ifdef CONFIG_CMD_NET
#define CONFIG_FEC_MXC
@@ -152,15 +116,8 @@
#endif
/* MMC Configs */
-#ifdef CONFIG_CMD_MMC
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 2
-#endif
/* OCOTP Configs */
#ifdef CONFIG_CMD_FUSE
@@ -196,8 +153,6 @@
/* UART */
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART2_BASE
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_CONS_INDEX 1
/* USB Configs */
#ifdef CONFIG_CMD_USB
diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h
index 200f40af31b5348e63b88f440730bfa87d4273ce..699b037b947b2e72ce6179617c3b1f6facb7dfc4 100644
--- a/include/configs/ot1200.h
+++ b/include/configs/ot1200.h
@@ -9,25 +9,12 @@
#define __CONFIG_H
#include "mx6_common.h"
-#define CONFIG_MX6
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_SYS_GENERIC_BOARD
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MISC_INIT_R
-#define CONFIG_MXC_GPIO
/* FUSE Configs */
#define CONFIG_CMD_FUSE
@@ -74,16 +61,9 @@
#define IMX_OTPWRITE_ENABLED
/* MMC Configs */
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 2
-#define CONFIG_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_BOUNCE_BUFFER
-
/* USB Configs */
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
@@ -146,36 +126,10 @@
#define CONFIG_CMD_BMODE
#define CONFIG_CMD_SETEXPR
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/* Command definition */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_IMLS
-
-#define CONFIG_BOOTDELAY 2
-
#define CONFIG_PREBOOT ""
-#define CONFIG_LOADADDR 0x12000000
-#define CONFIG_SYS_TEXT_BASE 0x17800000
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_CBSIZE 1024
-
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-#define CONFIG_CMDLINE_EDITING
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
@@ -190,9 +144,7 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH
-
+/* Environment organization */
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE (64 * 1024) /* 64 kb */
#define CONFIG_ENV_OFFSET (1024 * 1024)
@@ -203,24 +155,6 @@
#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
-#define CONFIG_OF_LIBFDT
-#define CONFIG_CMD_BOOTZ
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-#define CONFIG_CMD_CACHE
-#endif
-
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_SUPPORT_RAW_INITRD
-
-/* FS Configs */
-#define CONFIG_CMD_EXT3
-#define CONFIG_CMD_EXT4
-#define CONFIG_DOS_PARTITION
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_LIB_UUID
-#define CONFIG_CMD_FS_UUID
-
#define CONFIG_BOOTP_SERVERIP
#define CONFIG_BOOTP_BOOTFILE
diff --git a/include/configs/platinum.h b/include/configs/platinum.h
index 91ffc7c068b5d3f237c965a13396df4a39cee40c..5ab22e7d5f6b1df4a1839469fc0cd642a6dc5eae 100644
--- a/include/configs/platinum.h
+++ b/include/configs/platinum.h
@@ -7,8 +7,6 @@
#ifndef __PLATINUM_CONFIG_H__
#define __PLATINUM_CONFIG_H__
-#define CONFIG_SYS_GENERIC_BOARD
-
/* SPL */
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
@@ -18,24 +16,16 @@
#include "imx6_spl.h" /* common IMX6 SPL configuration */
#include "mx6_common.h"
-#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
/*
* Console configuration
*/
-#include <config_cmd_default.h>
#define CONFIG_CMD_BMODE
#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
#define CONFIG_CMD_FUSE
-#define CONFIG_CMD_GPIO
#define CONFIG_CMD_I2C
-#undef CONFIG_CMD_IMLS
#define CONFIG_CMD_MII
-#define CONFIG_CMD_MMC
#define CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NAND_TRIMFFS
@@ -50,14 +40,9 @@
* Hardware configuration
*/
-/* GPIO config */
-#define CONFIG_MXC_GPIO
-
/* UART config */
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_CONS_INDEX 1
/* I2C config */
#define CONFIG_SYS_I2C
@@ -66,14 +51,8 @@
#define CONFIG_SYS_I2C_SPEED 100000
/* MMC config */
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 1
-#define CONFIG_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_DOS_PARTITION
/* Ethernet config */
#define CONFIG_FEC_MXC
@@ -108,9 +87,6 @@
#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024)
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH
-
#ifdef CONFIG_CMD_NAND
/* NAND config */
@@ -153,53 +129,22 @@
* U-Boot configuration
*/
-/* Console boot messages */
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* Tag config */
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
/* Board startup config */
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MISC_INIT_R
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* Device tree support */
-#define CONFIG_OF_LIBFDT
-
-#define CONFIG_LOADADDR 0x12000000
-#define CONFIG_SYS_TEXT_BASE 0x17800000
-
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
PHYS_SDRAM_SIZE - (12 << 20))
-#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTCOMMAND "run bootubi_scr"
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
-
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_CMDLINE_EDITING
#define CONFIG_PREBOOT
-#define CONFIG_SYS_CBSIZE 256
-
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* MTD/UBI/UBIFS config */
#define CONFIG_LZO
@@ -219,10 +164,6 @@
"512k(res2),512k(res3),-(ubi1)"
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
-#define CONFIG_CMD_CACHE
-#endif
-
/*
* Environment configuration
*/
diff --git a/include/configs/platinum_picon.h b/include/configs/platinum_picon.h
index 4590df5a9e9f68574ea7bbb0bcc294c66c13a9d4..f5b476f462e1c19275a52e48c2a5a6f4eade8059 100644
--- a/include/configs/platinum_picon.h
+++ b/include/configs/platinum_picon.h
@@ -12,8 +12,6 @@
#define CONFIG_PLATINUM_PROJECT "picon"
#define CONFIG_PLATINUM_CPU "imx6dl"
-#define CONFIG_MX6
-
#include <configs/platinum.h>
#define CONFIG_FEC_XCV_TYPE RMII
diff --git a/include/configs/platinum_titanium.h b/include/configs/platinum_titanium.h
index 678965505f630ee2fb375bec66c3f11ee7c50c2d..9bca10fdf91553a243b4329b75d7057d544c41c1 100644
--- a/include/configs/platinum_titanium.h
+++ b/include/configs/platinum_titanium.h
@@ -12,8 +12,6 @@
#define CONFIG_PLATINUM_PROJECT "titanium"
#define CONFIG_PLATINUM_CPU "imx6q"
-#define CONFIG_MX6
-
#define PHYS_SDRAM_SIZE (512 << 20)
#define CONFIG_SYS_NAND_MAX_CHIPS 1
diff --git a/include/configs/secomx6quq7.h b/include/configs/secomx6quq7.h
index 46ffb7a31c924c9866337dc277e1a216bcb13ad5..72b13a63ac2e78710f6399c55c0de3f3eef89d8c 100644
--- a/include/configs/secomx6quq7.h
+++ b/include/configs/secomx6quq7.h
@@ -10,63 +10,28 @@
#define __CONFIG_H
#include "mx6_common.h"
-#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
-#include <linux/sizes.h>
-
-#define CONFIG_SYS_GENERIC_BOARD
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
+
#define CONFIG_BOARD_REVISION_TAG
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART2_BASE
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
/* Command definition */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_IMLS
-
#define CONFIG_CMD_BMODE
#define CONFIG_CMD_SETEXPR
-#define CONFIG_BOOTDELAY 3
-
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
-#define CONFIG_LOADADDR 0x12000000
-#define CONFIG_SYS_TEXT_BASE 0x17800000
/* MMC Configuration */
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-
/* Ethernet Configuration */
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
@@ -112,25 +77,14 @@
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "SECO MX6Q uQ7 U-Boot > "
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE 256
-
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
-#define CONFIG_CMDLINE_EDITING
-
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
@@ -145,9 +99,7 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH
-
+/* Environment organization */
#define CONFIG_ENV_SIZE (8 * 1024)
#if defined(CONFIG_ENV_IS_IN_MMC)
@@ -156,11 +108,4 @@
#define CONFIG_DYNAMIC_MMC_DEVNO
#endif
-#define CONFIG_OF_LIBFDT
-#define CONFIG_CMD_BOOTZ
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-#define CONFIG_CMD_CACHE
-#endif
-
#endif /* __CONFIG_H */
diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index b7ad7dfe07ae9364c70efa3db03f2167802c24ed..13a6e06b5d6c87a79ccbd9bff4aad1a675e7e88d 100644
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -10,35 +10,15 @@
#define __TBS2910_CONFIG_H
#include "mx6_common.h"
-#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
/* General configuration */
-#define CONFIG_MX6
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_MACH_TYPE 3980
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-#define CONFIG_SYS_GENERIC_BOARD
-
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_MXC_GPIO
-#define CONFIG_CMD_GPIO
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "Matrix U-Boot> "
-#define CONFIG_BOOTDELAY 3
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
@@ -58,9 +38,7 @@
#define CONFIG_SYS_MEMTEST_END \
(CONFIG_SYS_MEMTEST_START + 500 * 1024 * 1024)
-#define CONFIG_SYS_TEXT_BASE 0x80000000
#define CONFIG_SYS_BOOTMAPSZ 0x6C000000
-#define CONFIG_SYS_LOAD_ADDR 0x10800000
/* Serial console */
#define CONFIG_MXC_UART
@@ -72,38 +50,19 @@
#define CONFIG_CONS_INDEX 1
/* *** Command definition *** */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_IMLS
-
#define CONFIG_CMD_BMODE
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_MEMTEST
#define CONFIG_CMD_TIME
/* Filesystems / image support */
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
-#define CONFIG_CMD_FS_GENERIC
-
-#define CONFIG_OF_LIBFDT
-#define CONFIG_CMD_BOOTZ
-#define CONFIG_SUPPORT_RAW_INITRD
#define CONFIG_FIT
/* MMC */
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_USDHC_NUM 3
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
-
-#define CONFIG_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
#define CONFIG_SUPPORT_EMMC_BOOT
-#define CONFIG_BOUNCE_BUFFER
/* Ethernet */
#define CONFIG_FEC_MXC
@@ -216,13 +175,7 @@
#define CONFIG_MXC_OCOTP
#endif
-#ifndef CONFIG_SYS_DCACHE_OFF
-#define CONFIG_CMD_CACHE
-#endif
-
-/* Flash and environment organization */
-#define CONFIG_SYS_NO_FLASH
-
+/* Environment organization */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 2
#define CONFIG_SYS_MMC_ENV_PART 1
diff --git a/include/configs/titanium.h b/include/configs/titanium.h
index 320d76cac607292e05e35ead46409101fb7ff5de..7490fa8bed32ace047549a42c2d51c2462045789 100644
--- a/include/configs/titanium.h
+++ b/include/configs/titanium.h
@@ -14,28 +14,17 @@
#define __CONFIG_H
#include "mx6_common.h"
-#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
-#define CONFIG_MX6
#define CONFIG_MX6Q
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define MACH_TYPE_TITANIUM 3769
#define CONFIG_MACH_TYPE MACH_TYPE_TITANIUM
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MISC_INIT_R
-#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
@@ -48,19 +37,9 @@
#define CONFIG_SYS_I2C_SPEED 100000
/* MMC Configs */
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 1
-#define CONFIG_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
@@ -76,7 +55,6 @@
/* USB Configs */
#define CONFIG_CMD_USB
-#define CONFIG_CMD_FAT
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MX6
#define CONFIG_USB_STORAGE
@@ -87,21 +65,6 @@
/* Miscellaneous commands */
#define CONFIG_CMD_BMODE
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/* Command definition */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_IMLS
-
-#define CONFIG_BOOTDELAY 3
-
-#define CONFIG_LOADADDR 0x12000000
-#define CONFIG_SYS_TEXT_BASE 0x17800000
-
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (500 << 20))
@@ -180,22 +143,11 @@
#define CONFIG_BOOTCOMMAND "run nand_ubifs"
/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "Titanium > "
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
-
-#define CONFIG_SYS_CBSIZE 256
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
@@ -211,9 +163,6 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH
-
/* Enable NAND support */
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NAND_TRIMFFS
@@ -260,11 +209,4 @@
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
-#define CONFIG_OF_LIBFDT
-#define CONFIG_CMD_BOOTZ
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-#define CONFIG_CMD_CACHE
-#endif
-
#endif /* __CONFIG_H */
diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h
index 66962aa86f86fc86e1cae645d1e9ea05384a0b21..4c93c9bbb97c126196294123e344e00d23638068 100644
--- a/include/configs/tqma6.h
+++ b/include/configs/tqma6.h
@@ -9,8 +9,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MX6
-
/* SPL */
/* #if defined(CONFIG_SPL_BUILD) */
@@ -25,9 +23,6 @@
/* #endif */
#include "mx6_common.h"
-#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
-#include <linux/sizes.h>
#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
#define PHYS_SDRAM_SIZE (512u * SZ_1M)
@@ -35,19 +30,9 @@
#define PHYS_SDRAM_SIZE (1024u * SZ_1M)
#endif
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_SYS_GENERIC_BOARD
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
/* SPI */
@@ -95,15 +80,8 @@
#define TQMA6_PFUZE100_I2C_BUS 2
/* MMC Configs */
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_BOUNCE_BUFFER
-
/* USB Configs */
#define CONFIG_CMD_USB
#define CONFIG_USB_EHCI
@@ -119,13 +97,6 @@
#define CONFIG_MXC_OCOTP
#define CONFIG_CMD_FUSE
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
-#define CONFIG_DOS_PARTITION
-
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
@@ -142,23 +113,10 @@
#define CONFIG_TFTP_BLOCKSIZE 4096
#define CONFIG_NFS_READ_SIZE 4096
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
/* Command definition */
-#include <config_cmd_default.h>
-
#define CONFIG_CMD_BMODE
-#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_ITEST
#define CONFIG_CMD_SETEXPR
-#undef CONFIG_CMD_IMLS
-
-#define CONFIG_BOOTDELAY 3
-
-#define CONFIG_LOADADDR 0x12000000
/* place code in last 4 MiB of RAM */
#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
@@ -411,23 +369,10 @@
"panicboot=echo No boot device !!! reset\0" \
TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS \
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE 512
-
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define CONFIG_CMDLINE_EDITING
#define CONFIG_STACKSIZE (128u * SZ_1K)
/* Physical Memory Map */
@@ -443,18 +388,11 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH
-
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE
-#ifndef CONFIG_SYS_DCACHE_OFF
-#define CONFIG_CMD_CACHE
-#endif
-
/*
* All the defines above are for the TQMa6 SoM
*
diff --git a/include/configs/udoo.h b/include/configs/udoo.h
index b4a62453625bbffd1a5ebc50a681497e943d08ed..fce2b9b3e66bddaed52188e9d0014368dc607829 100644
--- a/include/configs/udoo.h
+++ b/include/configs/udoo.h
@@ -10,29 +10,14 @@
#define __CONFIG_H
#include "mx6_common.h"
-#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
-#include <linux/sizes.h>
-
-#define CONFIG_MX6
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
#define MACH_TYPE_UDOO 4800
#define CONFIG_MACH_TYPE MACH_TYPE_UDOO
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-#define CONFIG_SYS_GENERIC_BOARD
-
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M)
#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART2_BASE
@@ -65,39 +50,16 @@
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9031
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
/* Command definition */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_IMLS
-
#define CONFIG_CMD_BMODE
#define CONFIG_CMD_SETEXPR
-#define CONFIG_BOOTDELAY 3
-
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
-#define CONFIG_LOADADDR 0x12000000
-#define CONFIG_SYS_TEXT_BASE 0x17800000
/* MMC Configuration */
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-
#define CONFIG_DEFAULT_FDT_FILE "imx6q-udoo.dtb"
#define CONFIG_EXTRA_ENV_SETTINGS \
@@ -188,20 +150,8 @@
"fi; " \
"else run netboot; fi"
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE 256
-
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-#define CONFIG_CMDLINE_EDITING
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
@@ -216,20 +166,11 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH
-
+/* Environment organization */
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_OF_LIBFDT
-#define CONFIG_CMD_BOOTZ
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-#define CONFIG_CMD_CACHE
-#endif
-
#endif /* __CONFIG_H * */
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index b2c36148ba8c8071794281c97e073e2a73aa6cc4..69590ad884d12623b86873a124b2cf096f35aec5 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -10,53 +10,29 @@
#define __CONFIG_H
#include "mx6_common.h"
-#include <asm/arch/imx-regs.h>
-#include <asm/imx-common/gpio.h>
-#include <linux/sizes.h>
-#define CONFIG_MX6
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#include "imx6_spl.h"
#define MACH_TYPE_WANDBOARD 4412
#define CONFIG_MACH_TYPE MACH_TYPE_WANDBOARD
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
-#define CONFIG_SYS_GENERIC_BOARD
-
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
/* Command definition */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_IMLS
-
#define CONFIG_CMD_BMODE
#define CONFIG_CMD_SETEXPR
-#define CONFIG_BOOTDELAY 5
-
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
-#define CONFIG_LOADADDR 0x12000000
-#define CONFIG_SYS_TEXT_BASE 0x17800000
/* I2C Configs */
#define CONFIG_CMD_I2C
@@ -66,19 +42,9 @@
#define CONFIG_SYS_I2C_SPEED 100000
/* MMC Configuration */
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-
/* USB Configs */
#define CONFIG_CMD_USB
#define CONFIG_USB_EHCI
@@ -125,20 +91,15 @@
#define CONFIG_MXC_OCOTP
#endif
-#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
-#define CONFIG_DEFAULT_FDT_FILE "imx6dl-wandboard.dtb"
-#elif defined(CONFIG_MX6Q)
-#define CONFIG_DEFAULT_FDT_FILE "imx6q-wandboard.dtb"
-#endif
-
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=zImage\0" \
"console=ttymxc0\0" \
"splashpos=m,m\0" \
+ "fdtfile=undefined\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
- "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
"fdt_addr=0x18000000\0" \
"boot_fdt=try\0" \
"ip_dyn=yes\0" \
@@ -192,7 +153,7 @@
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
- "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
@@ -220,7 +181,7 @@
"fi; " \
"${get_cmd} ${image}; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
- "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdtfile}; then " \
"bootz ${loadaddr} - ${fdt_addr}; " \
"else " \
"if test ${boot_fdt} = try; then " \
@@ -231,9 +192,17 @@
"fi; " \
"else " \
"bootz; " \
- "fi;\0"
+ "fi;\0" \
+ "findfdt="\
+ "if test $board_rev = MX6Q ; then " \
+ "setenv fdtfile imx6q-wandboard.dtb; fi; " \
+ "if test $board_rev = MX6DL ; then " \
+ "setenv fdtfile imx6dl-wandboard.dtb; fi; " \
+ "if test $fdtfile = undefined; then " \
+ "echo WARNING: Could not determine dtb to use; fi; \0" \
#define CONFIG_BOOTCOMMAND \
+ "run findfdt; " \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
@@ -245,18 +214,6 @@
"fi; " \
"else run netboot; fi"
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-#define CONFIG_CMDLINE_EDITING
-
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
@@ -270,20 +227,11 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH
-
+/* Environment organization */
#define CONFIG_ENV_SIZE (8 * 1024)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
-#define CONFIG_OF_LIBFDT
-#define CONFIG_CMD_BOOTZ
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-#define CONFIG_CMD_CACHE
-#endif
-
#endif /* __CONFIG_H * */
diff --git a/include/configs/warp.h b/include/configs/warp.h
index 2eb429e5ddd143518a7d0f47ccb70fff2578354e..26739489551762602d92c5f9026ab81bec16a3c7 100644
--- a/include/configs/warp.h
+++ b/include/configs/warp.h
@@ -13,84 +13,34 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#include <asm/arch/imx-regs.h>
-#include <linux/sizes.h>
#include "mx6_common.h"
-#define CONFIG_MX6
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_SYS_GENERIC_BOARD
-
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_REVISION_TAG
-
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) /* Increase due to DFU */
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
/* MMC Configs */
-#define CONFIG_FSL_ESDHC
-#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT
#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
-#define CONFIG_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
-#define CONFIG_BOUNCE_BUFFER
-#define CONFIG_CMD_EXT2
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 115200
-
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH
-
/* Command definition */
-#include <config_cmd_default.h>
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
-#define CONFIG_BOOTDELAY 3
-
-#define CONFIG_LOADADDR 0x82000000
-#define CONFIG_SYS_TEXT_BASE 0x87800000
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE 256
-
/* Watchdog */
#define CONFIG_HW_WATCHDOG
#define CONFIG_IMX_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000 /* 30s */
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_256M)
-#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-
-#define CONFIG_CMDLINE_EDITING
#define CONFIG_STACKSIZE SZ_128K
/* Physical Memory Map */
@@ -115,13 +65,6 @@
/* VDD voltage 1.65 - 1.95 */
#define CONFIG_SYS_SD_VOLTAGE 0x00000080
-#define CONFIG_OF_LIBFDT
-#define CONFIG_CMD_BOOTZ
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-#define CONFIG_CMD_CACHE
-#endif
-
/* USB Configs */
#define CONFIG_CMD_USB
#ifdef CONFIG_CMD_USB
diff --git a/include/imx_thermal.h b/include/imx_thermal.h
index be1365288e5da5316932cd9e062515dc522f8831..8ce333cd56a0cff20a9a6fe07d85807416b7dcbc 100644
--- a/include/imx_thermal.h
+++ b/include/imx_thermal.h
@@ -8,6 +8,12 @@
#ifndef _IMX_THERMAL_H_
#define _IMX_THERMAL_H_
+/* CPU Temperature Grades */
+#define TEMP_COMMERCIAL 0
+#define TEMP_EXTCOMMERCIAL 1
+#define TEMP_INDUSTRIAL 2
+#define TEMP_AUTOMOTIVE 3
+
struct imx_thermal_plat {
void *regs;
int fuse_bank;
diff --git a/include/power/pfuze100_pmic.h b/include/power/pfuze100_pmic.h
index 8e7a22d020f648cc3e88da48b8b9aee1708734b1..57b9ca94afc1204378e62dc009ce0ad27932ad0f 100644
--- a/include/power/pfuze100_pmic.h
+++ b/include/power/pfuze100_pmic.h
@@ -18,7 +18,7 @@ enum {
PFUZE100_SW1ABSTBY = 0x21,
PFUZE100_SW1ABOFF = 0x22,
PFUZE100_SW1ABMODE = 0x23,
- PUZE_100_SW1ABCONF = 0x24,
+ PFUZE100_SW1ABCONF = 0x24,
PFUZE100_SW1CVOL = 0x2e,
PFUZE100_SW1CSTBY = 0x2f,
PFUZE100_SW1COFF = 0x30,