diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 946023093df65cbea2e3c04259982050ea46b047..76916dd351309701bee1f78094be51cf66fd55ca 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -438,6 +438,8 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
+dtb-$(CONFIG_ARCH_MX8M) += imx8mq-nitrogen8m.dtb
+
dtb-$(CONFIG_RCAR_GEN3) += \
r8a7795-h3ulcb.dtb \
r8a7795-salvator-x.dtb \
diff --git a/arch/arm/dts/imx8mq-nitrogen8m.dts b/arch/arm/dts/imx8mq-nitrogen8m.dts
new file mode 100644
index 0000000000000000000000000000000000000000..bf62ccccd0f2daeb740322d3ae03827dd880533b
--- /dev/null
+++ b/arch/arm/dts/imx8mq-nitrogen8m.dts
@@ -0,0 +1,1254 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2018 Boundary Devices
+ */
+
+/dts-v1/;
+
+/* First 128KB is for PSCI ATF. */
+/memreserve/ 0x40000000 0x00020000;
+
+#include "fsl-imx8mq.dtsi"
+
+#if 0
+#define MIPI_ON_DCSS
+#endif
+
+#if 0
+#define RM68200
+#endif
+
+#if 1
+#define HDMI_STATUS "okay"
+#else
+#define HDMI_STATUS "disabled"
+#endif
+
+#if 0
+#define MIPI_DSI_STATUS "okay"
+#else
+#define MIPI_DSI_STATUS "disabled"
+#endif
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog>;
+
+ iomuxc_pinctrl: iomuxc-pinctrlgrp {
+ };
+};
+
+&iomuxc_pinctrl {
+ pinctrl_bt_rfkill: bt-rfkillgrp {
+ fsl,pins = <
+#define GP_BT_RFKILL_RESET <&gpio3 19 GPIO_ACTIVE_LOW>
+ MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19
+ >;
+ };
+
+ pinctrl_csi1: csi1grp {
+ fsl,pins = <
+#define GP_CSI1_MIPI_PWDN <&gpio3 3 GPIO_ACTIVE_HIGH>
+ MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x61
+#define GP_CSI1_MIPI_RESET <&gpio3 17 GPIO_ACTIVE_HIGH>
+ MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x61
+ >;
+ };
+
+ pinctrl_csi2: csi2grp {
+ fsl,pins = <
+#define GP_CSI2_MIPI_PWDN <&gpio3 2 GPIO_ACTIVE_HIGH>
+ MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x61
+#define GP_CSI2_MIPI_RESET <&gpio2 19 GPIO_ACTIVE_HIGH>
+ MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x61
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ /* J17 */
+ MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x19 /* Pin 1 */
+ MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x19 /* Pin 3 */
+ MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x19 /* Pin 5 */
+ MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x19 /* Pin 7 */
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
+ MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+#define GP_FEC1_RESET <&gpio1 9 GPIO_ACTIVE_LOW>
+ MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
+#define GPIRQ_FEC1_PHY <&gpio1 11 IRQ_TYPE_LEVEL_LOW>
+ MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59
+ >;
+ };
+
+ pinctrl_gpio_keys: gpio_keysgrp {
+ fsl,pins = <
+#define GP_GPIOKEY_POWER <&gpio1 7 GPIO_ACTIVE_LOW>
+ MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
+ >;
+ };
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ /* J17 connector, odd */
+ MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* Pin 19 */
+ MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 /* Pin 21 */
+ MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x19 /* Pin 23 */
+ MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* Pin 25 */
+ MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* Pin 27 */
+ MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* Pin 29 */
+ MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19 /* Pin 31 */
+ MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19 /* Pin 33 */
+ MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19 /* Pin 35 */
+ MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x19 /* Pin 39 */
+ MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 /* Pin 41 */
+ MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* Pin 43 */
+ MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 /* Pin 45 */
+ MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 /* Pin 47 */
+ MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* Pin 49 */
+ MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* Pin 51 */
+
+ /* J17 connector, even */
+ MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 /* Pin 44 */
+ MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 /* Pin 48 */
+ MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* Pin 50 */
+ MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* Pin 54 */
+ MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* Pin 56 */
+
+ /* J18 connector, odd */
+ MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* Pin 41 */
+ MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* Pin 43 */
+ MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* Pin 45 */
+ MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* Pin 47 */
+ MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* Pin 49 */
+ MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* Pin 53 */
+ MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x19 /* Pin 55 */
+
+ /* J18 connector, even */
+ MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 /* Pin 32 */
+ MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x19 /* Pin 36 */
+ MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19 /* Pin 38 */
+ MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 /* Pin 40 */
+ MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 /* Pin 42 */
+ MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* Pin 44 */
+ MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* Pin 46 */
+
+ /* J13 Pin 2, WL_WAKE */
+ MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0xd6
+ /* J13 Pin 4, WL_IRQ, not needed for Silex */
+ MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0xd6
+ /* J13 pin 9, unused */
+ MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
+ /* J13 Pin 41, BT_CLK_REQ */
+ MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0xd6
+ /* J13 Pin 42, BT_HOST_WAKE */
+ MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0xd6
+ /* Causes a POR_B */
+ MX8MQ_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x19
+
+ /* Clock for both CSI1 and CSI2 */
+ MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x59
+ /* test points */
+ MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc1 /* TP87 */
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c1_pca9546: i2c1-pca9546grp {
+ fsl,pins = <
+#define GP_I2C1_PCA9546_RESET <&gpio1 8 GPIO_ACTIVE_LOW>
+ MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49
+ >;
+ };
+
+ pinctrl_i2c1d_rv4162: i2c1d-rv4162grp {
+ fsl,pins = <
+#define GPIRQ_RV4162 <&gpio1 6 IRQ_TYPE_LEVEL_LOW>
+ MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x49
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c4_touch: i2c4-touchgrp {
+ fsl,pins = <
+#define GPIRQ_GT911 <&gpio3 12 IRQ_TYPE_LEVEL_HIGH>
+#define GP_GT911_IRQ <&gpio3 12 GPIO_ACTIVE_HIGH>
+ MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x49
+ /* driver writes levels, instead of active/inactive */
+#define GP_GT911_RESET <&gpio3 13 GPIO_ACTIVE_HIGH>
+ MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x49
+ >;
+ };
+
+ pinctrl_i2c4_sn65dsi83: i2c4-sn65dsi83 {
+ fsl,pins = <
+#define GPIRQ_I2C4_SN65DSI83 <&gpio1 1 IRQ_TYPE_LEVEL_LOW>
+ MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x16
+#define GP_I2C4_SN65DSI83_EN <&gpio3 15 GPIO_ACTIVE_HIGH>
+ MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x26
+ >;
+ };
+
+ pinctrl_pcie0: pcie0grp {
+ fsl,pins = <
+#define GP_PCIE0_RESET <&gpio5 7 GPIO_ACTIVE_LOW>
+ MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x16
+#define GP_PCIE0_DISABLE <&gpio5 6 GPIO_ACTIVE_LOW>
+ MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16
+ >;
+ };
+
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x16
+ >;
+ };
+
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0x16
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT 0x16
+ >;
+ };
+
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT 0x16
+ >;
+ };
+
+ pinctrl_reg_arm_dram: reg-arm-dram {
+ fsl,pins = <
+#define GP_ARM_DRAM_VSEL <&gpio3 24 GPIO_ACTIVE_HIGH>
+ MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16
+ >;
+ };
+
+ pinctrl_reg_dram_1p1v: reg-dram-1p1v {
+ fsl,pins = <
+#define GP_DRAM_1P1_VSEL <&gpio2 11 GPIO_ACTIVE_HIGH>
+ MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x16
+ >;
+ };
+
+ pinctrl_reg_soc_gpu_vpu: reg-soc-gpu-vpu {
+ fsl,pins = <
+#define GP_SOC_GPU_VPU_VSEL <&gpio2 20 GPIO_ACTIVE_HIGH>
+ MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x16
+ >;
+ };
+
+ pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp {
+ fsl,pins = <
+#define GP_REG_USB_OTG_VBUS <&gpio1 12 GPIO_ACTIVE_HIGH>
+ MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x16
+ >;
+ };
+
+ pinctrl_reg_wlan_vmmc: reg-wlan-vmmcgrp {
+ fsl,pins = <
+#define GP_REG_WLAN_VMMC <&gpio3 20 GPIO_ACTIVE_HIGH>
+ MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x16
+ >;
+ };
+
+ pinctrl_sai1: sai1grp {
+ fsl,pins = <
+ /* wm8960 */
+ MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6
+ MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6
+ MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6
+ MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6
+ MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6
+ >;
+ };
+
+ pinctrl_sai2: sai2grp {
+ fsl,pins = <
+ /* J17 */
+ MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 /* Pin 22 */
+ MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0xd6 /* Pin 24 */
+ MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 /* Pin 26 */
+ MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 /* Pin 28 */
+ MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0xd6 /* Pin 30 */
+ MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 /* Pin 32 */
+ MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 /* Pin 34 */
+ >;
+ };
+
+ pinctrl_sai3: sai3grp {
+ fsl,pins = <
+ /* Bluetooth PCM */
+ MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
+ MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
+ MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
+ MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45
+ MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45
+ MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x45
+ MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x45
+ MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x45
+ MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x45
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x45
+ MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x45
+ >;
+ };
+
+ pinctrl_usb3_0: usb3-0grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x16
+ >;
+ };
+
+ pinctrl_usb3_1: usb3-1grp {
+ fsl,pins = <
+#define GP_USB3_1_HUB_RESET <&gpio1 14 GPIO_ACTIVE_LOW>
+ MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
+#if 0
+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
+#else
+#define GP_EMMC_RESET <&gpio2 10 GPIO_ACTIVE_LOW>
+ MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
+#endif
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
+ /* Bluetooth slow clock */
+ MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x03
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
+ >;
+ };
+};
+
+/ {
+ model = "Boundary Devices i.MX8MQ Nitrogen8M";
+ compatible = "boundary,imx8mq-nitrogen8m", "fsl,imx8mq";
+
+ chosen {
+ bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
+#if 0
+ stdout-path = &uart1;
+#endif
+ };
+
+#if 0
+ backlight_mipi_dsi: backlight_mipi_dsi {
+ brightness-levels = <0 1 2 3 4 5 6 7 8 9 10>;
+ compatible = "pwm-backlight";
+ default-brightness-level = <8>;
+ display = <&fb_mipi_dsi>;
+ pwms = <&pwm3 0 30000>; /* 33.3 Khz */
+ };
+#endif
+
+ bt-rfkill {
+ compatible = "net,rfkill-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_bt_rfkill>;
+ name = "bt-rfkill";
+ type = <2>; /* Bluetooth */
+ reset-gpios = GP_BT_RFKILL_RESET;
+ status = "okay";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ power {
+ label = "Power Button";
+ gpios = GP_GPIOKEY_POWER;
+ linux,code = <KEY_POWER>;
+ gpio-key,wakeup;
+ };
+ };
+
+ mipi_mclk: mipi_mclk {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <22000000>;
+ clock-output-names = "mipi_mclk";
+#if 0
+ pwms = <&pwm1 0 45>; /* 1 / 45 ns = 22 MHz */
+#endif
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usbotg_vbus>;
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = GP_REG_USB_OTG_VBUS;
+ enable-active-high;
+ };
+
+ reg_vref_0v9: regulator-vref-0v9 {
+ compatible = "regulator-fixed";
+ regulator-name = "vref-1v";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ };
+
+ reg_vref_1v8: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "1P8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ reg_vref_5v: regulator-vref-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vref-5v";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_wlan_vmmc: regulator-wlan-vmmc {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_wlan_vmmc>;
+ regulator-name = "reg_wlan_vmmc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = GP_REG_WLAN_VMMC;
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+#if 0
+ sound-wm8960 {
+ compatible = "fsl,imx-audio-wm8960";
+ model = "wm8960-audio";
+ cpu-dai = <&sai1>;
+ codec-master;
+ audio-codec = <&wm8960>;
+ audio-routing =
+ "Headphone Jack", "HP_L",
+ "Headphone Jack", "HP_R",
+ "Ext Spk", "SPK_LP",
+ "Ext Spk", "SPK_LN",
+ "Ext Spk", "SPK_RP",
+ "Ext Spk", "SPK_RN",
+ "LINPUT1", "Main MIC",
+ "Main MIC", "MICB";
+ /* JD2: hp detect high for headphone*/
+ hp-det = <2 0>;
+ };
+
+ sound-hdmi {
+ compatible = "fsl,imx-audio-cdnhdmi";
+ model = "imx-audio-hdmi";
+ audio-cpu = <&sai4>;
+ protocol = <1>;
+ status = HDMI_STATUS;
+ };
+#endif
+};
+
+&A53_0 {
+ operating-points = <
+ /* kHz uV */
+ 1500000 1000000
+ 1300000 1000000
+ 1000000 900000
+ 800000 900000
+ >;
+};
+
+&clk {
+ assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>;
+ assigned-clock-rates = <786432000>, <722534400>;
+};
+
+#if 0
+&csi1_bridge {
+ fsl,mipi-mode;
+ fsl,two-8bit-sensor-mode;
+ status = "okay";
+
+ port {
+ csi1_ep: endpoint {
+ remote-endpoint = <&csi1_mipi_ep>;
+ };
+ };
+};
+
+&csi2_bridge {
+ fsl,mipi-mode;
+ fsl,two-8bit-sensor-mode;
+ status = "okay";
+
+ port {
+ csi2_ep: endpoint {
+ remote-endpoint = <&csi2_mipi_ep>;
+ };
+ };
+};
+
+&dcss {
+#ifdef MIPI_ON_DCSS
+ status = MIPI_DSI_STATUS;
+ disp-dev = "mipi_disp";
+
+ clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
+ <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
+ <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
+ <&clk IMX8MQ_CLK_DC_PIXEL_DIV>,
+ <&clk IMX8MQ_CLK_DUMMY>,
+ <&clk IMX8MQ_CLK_DISP_DTRC_DIV>;
+ clock-names = "apb", "axi", "rtrm", "pix_div", "pix_out", "dtrc";
+
+ assigned-clocks = <&clk IMX8MQ_CLK_DC_PIXEL_SRC>,
+ <&clk IMX8MQ_CLK_DISP_AXI_SRC>,
+ <&clk IMX8MQ_CLK_DISP_RTRM_SRC>,
+ <&clk IMX8MQ_CLK_DISP_RTRM_PRE_DIV>,
+ <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
+ <&clk IMX8MQ_VIDEO_PLL1>;
+ assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
+ <&clk IMX8MQ_SYS1_PLL_800M>,
+ <&clk IMX8MQ_SYS1_PLL_800M>,
+ <&clk IMX8MQ_VIDEO_PLL1_OUT>,
+ <&clk IMX8MQ_CLK_25M>;
+ assigned-clock-rates = <600000000>,
+ <800000000>,
+ <400000000>,
+ <400000000>,
+ <0>,
+ <599999999>;
+
+ dcss_disp0: port@0 {
+ reg = <0>;
+
+ dcss_disp0_mipi_dsi: mipi_dsi {
+ remote-endpoint = <&mipi_dsi_in>;
+ };
+ };
+#else
+ status = HDMI_STATUS;
+ disp-dev = "hdmi_disp";
+#endif
+};
+
+&ecspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ status = "okay";
+};
+#endif
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+#if 0
+ phy-reset-gpios = GP_FEC1_RESET;
+#endif
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <4>;
+ interrupts-extended = GPIRQ_FEC1_PHY;
+ };
+ };
+};
+
+#if 0
+&gpu {
+ status = "okay";
+};
+
+&hdmi {
+ status = HDMI_STATUS;
+};
+
+&hdmi_cec {
+ status = HDMI_STATUS;
+};
+#endif
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ i2cmux@70 {
+ compatible = "pca9546";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_pca9546>;
+ reg = <0x70>;
+ reset-gpios = GP_I2C1_PCA9546_RESET;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c1a: i2c1@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1b: i2c1@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1c: i2c1@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ i2c1d: i2c1@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&i2c1a {
+ reg_arm_dram: fan53555@60 {
+ compatible = "fcs,fan53555";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_arm_dram>;
+ reg = <0x60>;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ vsel-gpios = GP_ARM_DRAM_VSEL;
+ };
+};
+
+&i2c1b {
+ reg_dram_1p1v: fan53555@60 {
+ compatible = "fcs,fan53555";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_dram_1p1v>;
+ reg = <0x60>;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ vsel-gpios = GP_DRAM_1P1_VSEL;
+ };
+};
+
+&i2c1c {
+ reg_soc_gpu_vpu: fan53555@60 {
+ compatible = "fcs,fan53555";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>;
+ reg = <0x60>;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ vsel-gpios = GP_SOC_GPU_VPU_VSEL;
+ };
+};
+
+&i2c1d {
+ rtc@68 {
+ compatible = "microcrystal,rv4162";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1d_rv4162>;
+ reg = <0x68>;
+ interrupts-extended = GPIRQ_RV4162;
+ wakeup-source;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ ov5640-mipi1@3c {
+ compatible = "ovti,ov5640_mipi";
+ reg = <0x3c>;
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_csi1>;
+ clocks = <&mipi_mclk>;
+ clock-names = "csi_mclk";
+ csi_id = <0>;
+ pwn-gpios = GP_CSI1_MIPI_PWDN;
+ rst-gpios = GP_CSI1_MIPI_RESET;
+ mclk = <22000000>;
+ mclk_source = <0>;
+
+#if 0
+ port {
+ ov5640_mipi1_ep: endpoint {
+ remote-endpoint = <&mipi1_sensor_ep>;
+ };
+ };
+#endif
+ };
+
+ pcie-clock@6a {
+ compatible = "idt,9FGV0241AKILF";
+ /* TODO */
+ reg = <0x6a>;
+ };
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "okay";
+
+#if 0
+ ov5640-mipi2@3c {
+ compatible = "ovti,ov5640_mipi";
+ reg = <0x3c>;
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_csi2>;
+ clocks = <&mipi_mclk>;
+ clock-names = "csi_mclk";
+ csi_id = <1>;
+ pwn-gpios = GP_CSI2_MIPI_PWDN;
+ rst-gpios = GP_CSI2_MIPI_RESET;
+ mclk = <22000000>;
+ mclk_source = <0>;
+ port {
+ ov5640_mipi2_ep: endpoint {
+ remote-endpoint = <&mipi2_sensor_ep>;
+ };
+ };
+ };
+#endif
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ touchscreen@14 {
+ compatible = "goodix,gt9271";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4_touch>;
+ reg = <0x14>;
+ esd-recovery-timeout-ms = <2000>;
+ interrupts-extended = GPIRQ_GT911;
+ irq-gpios = GP_GT911_IRQ;
+ reset-gpios = GP_GT911_RESET;
+ };
+
+ wm8960: codec@1a {
+ compatible = "wlf,wm8960";
+ reg = <0x1a>;
+ clocks = <&clk IMX8MQ_CLK_SAI1_ROOT>;
+ clock-names = "mclk";
+ wlf,shared-lrclk;
+ };
+
+#if 0
+ mipi_to_lvds@2c {
+ compatible = "ti,sn65dsi83";
+ display = <&fb_mipi_dsi>;
+ clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF_DIV>;
+ clock-names = "mipi_clk";
+ enable-gpios = GP_I2C4_SN65DSI83_EN;
+ interrupts-extended = GPIRQ_I2C4_SN65DSI83;
+ dsi-lanes = <4>;
+ lvds-24bpp;
+ jeida;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4_sn65dsi83>;
+ reg = <0x2c>;
+ };
+#endif
+};
+
+&lcdif {
+#if 0
+#ifndef MIPI_ON_DCSS
+ status = "okay";
+
+ assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL_SRC>,
+ <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
+ <&clk IMX8MQ_VIDEO_PLL1>;
+ assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
+ <&clk IMX8MQ_CLK_25M>;
+ assigned-clock-rate = <120000000>,
+ <0>,
+ <599999999>;
+ max-res = <1920>, <1920>;
+
+ port@0 {
+ lcdif_mipi_dsi: mipi-dsi-endpoint {
+ remote-endpoint = <&mipi_dsi_in>;
+ };
+ };
+#endif
+#endif
+};
+
+#if 0
+&mipi_csi_1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ port {
+ mipi1_sensor_ep: endpoint1 {
+ remote-endpoint = <&ov5640_mipi1_ep>;
+ data-lanes = <1 2>;
+ };
+
+ csi1_mipi_ep: endpoint2 {
+ remote-endpoint = <&csi1_ep>;
+ };
+ };
+};
+
+&mipi_csi_2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ port {
+ mipi2_sensor_ep: endpoint1 {
+ remote-endpoint = <&ov5640_mipi2_ep>;
+ data-lanes = <1 2>;
+ };
+
+ csi2_mipi_ep: endpoint2 {
+ remote-endpoint = <&csi2_ep>;
+ };
+ };
+};
+
+&mipi_dsi_phy {
+ status = MIPI_DSI_STATUS;
+};
+
+&mipi_dsi {
+ status = MIPI_DSI_STATUS;
+#ifndef MIPI_ON_DCSS
+ as_bridge;
+ sync-pol = <1>;
+#endif
+ assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF_SRC>,
+ <&clk IMX8MQ_CLK_DSI_CORE_SRC>,
+ <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
+ <&clk IMX8MQ_VIDEO_PLL1>;
+ assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>,
+ <&clk IMX8MQ_SYS1_PLL_266M>,
+ <&clk IMX8MQ_CLK_25M>;
+ assigned-clock-rates = <24000000>,
+ <266000000>,
+ <0>,
+ <599999999>;
+
+ port@1 {
+ mipi_dsi_in: endpoint {
+#ifdef MIPI_ON_DCSS
+ remote-endpoint = <&dcss_disp0_mipi_dsi>;
+#else
+ remote-endpoint = <&lcdif_mipi_dsi>;
+#endif
+ };
+ };
+};
+
+&mipi_dsi_bridge {
+ status = MIPI_DSI_STATUS;
+
+ fb_mipi_dsi: panel@0 {
+ compatible = "panel,simple";
+ reg = <0>;
+ bits-per-color = <8>;
+ bus-format = "rgb888";
+ dsi-format = "rgb888";
+ power-supply = <®_vref_5v>;
+#ifdef RM68200
+#include "panel-osd050t3236.dtsi"
+#else
+#include "panel-ltk080a60a004t.dtsi"
+#endif
+
+ port {
+ panel1_in: endpoint {
+ remote-endpoint = <&mipi_dsi_bridge_out>;
+ };
+ };
+ };
+
+ port@1 {
+ mipi_dsi_bridge_out: endpoint {
+ remote-endpoint = <&panel1_in>;
+ };
+ };
+};
+#endif
+
+#if 0
+&mu {
+ status = "okay";
+};
+
+&pcie0 {
+#if 1
+ clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
+ <&clk IMX8MQ_CLK_PCIE1_AUX_CG>,
+ <&clk IMX8MQ_CLK_PCIE1_PHY_CG>,
+ <&clk IMX8MQ_CLK_CLK2_CG>;
+ clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_ext_src";
+ ext_osc = <0>;
+#else
+ ext_osc = <1>;
+#endif
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0>;
+ /* TODO check clock */
+ disable-gpio = GP_PCIE0_DISABLE;
+ reset-gpio = GP_PCIE0_RESET;
+ status = "okay";
+};
+#endif
+
+#if 0
+&pcie1 {
+ /* TODO check clock */
+ ext_osc = <1>;
+ hard-wired = <1>;
+ status = "disabled";
+};
+
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "okay";
+};
+#endif
+
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2>;
+ status = "okay";
+};
+
+#if 0
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+ status = "okay";
+};
+
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+ status = "okay";
+};
+#endif
+
+#if 0
+&rpmsg{
+ /*
+ * 64K for one rpmsg instance:
+ * --0xb8000000~0xb800ffff: pingpong
+ */
+ vdev-nums = <1>;
+ reg = <0x0 0xb8000000 0x0 0x10000>;
+ status = "okay";
+};
+
+&sai1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai1>;
+ assigned-clocks = <&clk IMX8MQ_CLK_SAI1_SRC>,
+ <&clk IMX8MQ_CLK_SAI1_DIV>;
+ assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <0>, <12288000>;
+ status = "okay";
+};
+
+&sai2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai2>;
+ status = "okay";
+};
+
+&sai3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai3>;
+ status = "okay";
+};
+
+&sai4 {
+ assigned-clocks = <&clk IMX8MQ_CLK_SAI4_SRC>,
+ <&clk IMX8MQ_CLK_SAI4_DIV>;
+ assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
+ assigned-clock-rates = <0>, <24576000>;
+ status = "okay";
+};
+#endif
+
+#if 0
+&uart1 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>;
+ assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ assigned-clocks = <&clk IMX8MQ_CLK_UART2_SRC>;
+ assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>;
+ assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ assigned-clocks = <&clk IMX8MQ_CLK_UART4_SRC>;
+ assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
+ status = "okay";
+};
+#endif
+
+&usb3_phy0 {
+ status = "okay";
+};
+
+#if 1
+&usb3_0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb3_0>;
+ status = "okay";
+};
+
+&usb_dwc3_0 {
+#if 0
+ status = "okay";
+#endif
+ dr_mode = "otg";
+ vbus-supply = <®_usb_otg_vbus>;
+};
+#endif
+
+&usb3_phy1 {
+ status = "okay";
+};
+
+&usb3_1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb3_1>;
+ reset-gpios = GP_USB3_1_HUB_RESET;
+ status = "okay";
+};
+
+&usb_dwc3_1 {
+#if 0
+ status = "okay";
+#endif
+ dr_mode = "host";
+};
+
+&usdhc1 {
+ bus-width = <8>;
+#if 0
+ pinctrl-names = "default";
+#else
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+#endif
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ reset-gpios = GP_EMMC_RESET;
+ non-removable;
+ vqmmc-1-8-v;
+ vmmc-supply = <®_vref_1v8>;
+ status = "okay";
+};
+
+#if 0
+&usdhc2 {
+ bus-width = <4>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ non-removable;
+ status = "okay";
+ vmmc-supply = <®_wlan_vmmc>;
+};
+
+&vpu {
+ regulator-supply = <®_vref_0v9>;
+ status = "okay";
+};
+#endif
+
+&wdog1 {
+ status = "okay";
+};
diff --git a/arch/arm/mach-imx/mx8m/Kconfig b/arch/arm/mach-imx/mx8m/Kconfig
index 3a84c2f2b09cc2d376c5b135ed6fe2e125e3ff1c..730dc668d3c5ed0dd753af34691518ee43411261 100644
--- a/arch/arm/mach-imx/mx8m/Kconfig
+++ b/arch/arm/mach-imx/mx8m/Kconfig
@@ -4,7 +4,19 @@ config MX8M
bool
select ROM_UNIFIED_SECTIONS
+choice
+ prompt "NXP i.MX8M board select"
+ optional
+
+config TARGET_NITROGEN8M
+ bool "nitrogen8m"
+ select MX8M
+ select SUPPORT_SPL
+
+endchoice
+
config SYS_SOC
default "mx8m"
+source "board/boundary/nitrogen8m/Kconfig"
endif
diff --git a/board/boundary/nitrogen8m/Kconfig b/board/boundary/nitrogen8m/Kconfig
new file mode 100644
index 0000000000000000000000000000000000000000..b8c0e2d38d561bc5eaad34f58f06688fbdaf03c2
--- /dev/null
+++ b/board/boundary/nitrogen8m/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_NITROGEN8M
+
+config SYS_BOARD
+ default "nitrogen8m"
+
+config SYS_VENDOR
+ default "boundary"
+
+config SYS_CONFIG_NAME
+ default "nitrogen8m"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/board/boundary/nitrogen8m/Makefile b/board/boundary/nitrogen8m/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..aba974492b3b25cb15f083fbd4857f17c13d483b
--- /dev/null
+++ b/board/boundary/nitrogen8m/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2016 Freescale Semiconductor
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += nitrogen8m.o mmc.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-y += ddr/ddr_init.o ddr/ddrphy_train.o ddr/helper.o
+endif
diff --git a/board/boundary/nitrogen8m/ddr/ddr.h b/board/boundary/nitrogen8m/ddr/ddr.h
new file mode 100644
index 0000000000000000000000000000000000000000..a8e4ca8c6179d642766ecc9096e79576fc2b50aa
--- /dev/null
+++ b/board/boundary/nitrogen8m/ddr/ddr.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+enum fw_type {
+ FW_1D_IMAGE,
+ FW_2D_IMAGE,
+};
+
+void ddr_init(void);
+void ddr_load_train_code(enum fw_type type);
+void lpddr4_800M_cfg_phy(void);
+
+static inline void reg32_write(unsigned long addr, u32 val)
+{
+ writel(val, addr);
+}
+
+static inline void reg32_writep(u32 *addr, u32 val)
+{
+ writel(val, addr);
+}
+
+static inline uint32_t reg32_read(unsigned long addr)
+{
+ return readl(addr);
+}
+
+static void inline dwc_ddrphy_apb_wr(unsigned long addr, u32 val)
+{
+ writel(val, addr);
+}
+
+static inline void reg32setbit(unsigned long addr, u32 bit)
+{
+ setbits_le32(addr, (1 << bit));
+}
diff --git a/board/boundary/nitrogen8m/ddr/ddr_init.c b/board/boundary/nitrogen8m/ddr/ddr_init.c
new file mode 100644
index 0000000000000000000000000000000000000000..dff466177b8dabe43ee1ef7eb45e12267046f757
--- /dev/null
+++ b/board/boundary/nitrogen8m/ddr/ddr_init.c
@@ -0,0 +1,274 @@
+/*
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include "ddr.h"
+#include "ddr_memory_map.h"
+
+#ifdef CONFIG_ENABLE_DDR_TRAINING_DEBUG
+#define ddr_printf(args...) printf(args)
+#else
+#define ddr_printf(args...)
+#endif
+
+#include "wait_ddrphy_training_complete.c"
+#ifndef SRC_DDRC_RCR_ADDR
+#define SRC_DDRC_RCR_ADDR SRC_IPS_BASE_ADDR +0x1000
+#endif
+#ifndef DDR_CSD1_BASE_ADDR
+#define DDR_CSD1_BASE_ADDR 0x40000000
+#endif
+#define SILICON_TRAIN
+#define DDR_BOOT_P1 /* default DDR boot frequency point */
+#define WR_POST_EXT_3200
+
+volatile unsigned int tmp, tmp_t, i;
+void lpddr4_800MHz_cfg_umctl2(void)
+{
+ /* Start to config, default 3200mbps */
+ /* dis_dq=1, indicates no reads or writes are issued to SDRAM */
+ reg32_write(DDRC_DBG1(0), 0x00000001);
+ /* selfref_en=1, SDRAM enter self-refresh state */
+ reg32_write(DDRC_PWRCTL(0), 0x00000001);
+ reg32_write(DDRC_MSTR(0), 0xa3080020);
+ reg32_write(DDRC_MSTR2(0), 0x00000000);
+ reg32_write(DDRC_RFSHTMG(0), 0x006100E0);
+ reg32_write(DDRC_INIT0(0), 0xC003061B);
+ reg32_write(DDRC_INIT1(0), 0x009D0000);
+ reg32_write(DDRC_INIT3(0), 0x00D4002D);
+#ifdef WR_POST_EXT_3200 // recommened to define
+ reg32_write(DDRC_INIT4(0), 0x00330008);
+#else
+ reg32_write(DDRC_INIT4(0), 0x00310008);
+#endif
+ reg32_write(DDRC_INIT6(0), 0x0066004a);
+ reg32_write(DDRC_INIT7(0), 0x0006004a);
+
+ reg32_write(DDRC_DRAMTMG0(0), 0x1A201B22);
+ reg32_write(DDRC_DRAMTMG1(0), 0x00060633);
+ reg32_write(DDRC_DRAMTMG3(0), 0x00C0C000);
+ reg32_write(DDRC_DRAMTMG4(0), 0x0F04080F);
+ reg32_write(DDRC_DRAMTMG5(0), 0x02040C0C);
+ reg32_write(DDRC_DRAMTMG6(0), 0x01010007);
+ reg32_write(DDRC_DRAMTMG7(0), 0x00000401);
+ reg32_write(DDRC_DRAMTMG12(0), 0x00020600);
+ reg32_write(DDRC_DRAMTMG13(0), 0x0C100002);
+ reg32_write(DDRC_DRAMTMG14(0), 0x000000E6);
+ reg32_write(DDRC_DRAMTMG17(0), 0x00A00050);
+
+ reg32_write(DDRC_ZQCTL0(0), 0x03200018);
+ reg32_write(DDRC_ZQCTL1(0), 0x028061A8);
+ reg32_write(DDRC_ZQCTL2(0), 0x00000000);
+
+ reg32_write(DDRC_DFITMG0(0), 0x0497820A);
+ reg32_write(DDRC_DFITMG1(0), 0x00080303);
+ reg32_write(DDRC_DFIUPD0(0), 0xE0400018);
+ reg32_write(DDRC_DFIUPD1(0), 0x00DF00E4);
+ reg32_write(DDRC_DFIUPD2(0), 0x80000000);
+ reg32_write(DDRC_DFIMISC(0), 0x00000011);
+ reg32_write(DDRC_DFITMG2(0), 0x0000170A);
+
+ reg32_write(DDRC_DBICTL(0), 0x00000001);
+ reg32_write(DDRC_DFIPHYMSTR(0), 0x00000001);
+
+ /* need be refined by ddrphy trained value */
+ reg32_write(DDRC_RANKCTL(0), 0x00000c99);
+ reg32_write(DDRC_DRAMTMG2(0), 0x070E171a);
+
+ /* address mapping */
+ /* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
+ reg32_write(DDRC_ADDRMAP0(0), 0x00000015);
+ reg32_write(DDRC_ADDRMAP3(0), 0x00000000);
+ /* addrmap_col_b10 and addrmap_col_b11 set to de-activated (5-bit width) */
+ reg32_write(DDRC_ADDRMAP4(0), 0x00001F1F);
+ /* bank interleave */
+ /* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */
+ reg32_write(DDRC_ADDRMAP1(0), 0x00080808);
+ /* addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 */
+ reg32_write(DDRC_ADDRMAP5(0), 0x07070707);
+ /* addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 */
+ reg32_write(DDRC_ADDRMAP6(0), 0x0f080707);
+ reg32_write(DDRC_ADDRMAP7(0), 0x00000f0f);
+
+ /* 667mts frequency setting */
+ reg32_write(DDRC_FREQ1_DERATEEN(0), 0x0000000);
+ reg32_write(DDRC_FREQ1_DERATEINT(0), 0x0800000);
+ reg32_write(DDRC_FREQ1_RFSHCTL0(0), 0x0210000);
+ reg32_write(DDRC_FREQ1_RFSHTMG(0), 0x014001E);
+ reg32_write(DDRC_FREQ1_INIT3(0), 0x0140009);
+ reg32_write(DDRC_FREQ1_INIT4(0), 0x00310008);
+ reg32_write(DDRC_FREQ1_INIT6(0), 0x0066004a);
+ reg32_write(DDRC_FREQ1_INIT7(0), 0x0006004a);
+ reg32_write(DDRC_FREQ1_DRAMTMG0(0), 0xB070A07);
+ reg32_write(DDRC_FREQ1_DRAMTMG1(0), 0x003040A);
+ reg32_write(DDRC_FREQ1_DRAMTMG2(0), 0x305080C);
+ reg32_write(DDRC_FREQ1_DRAMTMG3(0), 0x0505000);
+ reg32_write(DDRC_FREQ1_DRAMTMG4(0), 0x3040203);
+ reg32_write(DDRC_FREQ1_DRAMTMG5(0), 0x2030303);
+ reg32_write(DDRC_FREQ1_DRAMTMG6(0), 0x2020004);
+ reg32_write(DDRC_FREQ1_DRAMTMG7(0), 0x0000302);
+ reg32_write(DDRC_FREQ1_DRAMTMG12(0), 0x0020310);
+ reg32_write(DDRC_FREQ1_DRAMTMG13(0), 0xA100002);
+ reg32_write(DDRC_FREQ1_DRAMTMG14(0), 0x0000020);
+ reg32_write(DDRC_FREQ1_DRAMTMG17(0), 0x0220011);
+ reg32_write(DDRC_FREQ1_ZQCTL0(0), 0x0A70005);
+ reg32_write(DDRC_FREQ1_DFITMG0(0), 0x3858202);
+ reg32_write(DDRC_FREQ1_DFITMG1(0), 0x0000404);
+ reg32_write(DDRC_FREQ1_DFITMG2(0), 0x0000502);
+
+ /* performance setting */
+ dwc_ddrphy_apb_wr(DDRC_ODTCFG(0), 0x0b060908);
+ dwc_ddrphy_apb_wr(DDRC_ODTMAP(0), 0x00000000);
+ dwc_ddrphy_apb_wr(DDRC_SCHED(0), 0x29511505);
+ dwc_ddrphy_apb_wr(DDRC_SCHED1(0), 0x0000002c);
+ dwc_ddrphy_apb_wr(DDRC_PERFHPR1(0), 0x5900575b);
+ dwc_ddrphy_apb_wr(DDRC_PERFLPR1(0), 0x00000009);
+ dwc_ddrphy_apb_wr(DDRC_PERFWR1(0), 0x02005574);
+ dwc_ddrphy_apb_wr(DDRC_DBG0(0), 0x00000016);
+ dwc_ddrphy_apb_wr(DDRC_DBG1(0), 0x00000000);
+ dwc_ddrphy_apb_wr(DDRC_DBGCMD(0), 0x00000000);
+ dwc_ddrphy_apb_wr(DDRC_SWCTL(0), 0x00000001);
+ dwc_ddrphy_apb_wr(DDRC_POISONCFG(0), 0x00000011);
+ dwc_ddrphy_apb_wr(DDRC_PCCFG(0), 0x00000111);
+ dwc_ddrphy_apb_wr(DDRC_PCFGR_0(0), 0x000010f3);
+ dwc_ddrphy_apb_wr(DDRC_PCFGW_0(0), 0x000072ff);
+ dwc_ddrphy_apb_wr(DDRC_PCTRL_0(0), 0x00000001);
+ dwc_ddrphy_apb_wr(DDRC_PCFGQOS0_0(0), 0x01110d00);
+ dwc_ddrphy_apb_wr(DDRC_PCFGQOS1_0(0), 0x00620790);
+ dwc_ddrphy_apb_wr(DDRC_PCFGWQOS0_0(0), 0x00100001);
+ dwc_ddrphy_apb_wr(DDRC_PCFGWQOS1_0(0), 0x0000041f);
+ dwc_ddrphy_apb_wr(DDRC_FREQ1_DERATEEN(0), 0x00000202);
+ dwc_ddrphy_apb_wr(DDRC_FREQ1_DERATEINT(0), 0xec78f4b5);
+ dwc_ddrphy_apb_wr(DDRC_FREQ1_RFSHCTL0(0), 0x00618040);
+ dwc_ddrphy_apb_wr(DDRC_FREQ1_RFSHTMG(0), 0x00610090);
+}
+
+void ddr_init(void)
+{
+ struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
+
+ reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F00000F);
+ reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);
+ mdelay(100);
+ reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000);
+
+ /* change the clock source of dram_apb_clk_root */
+ reg32_writep(&ccm_reg->bus_root[1].target_root_clr, (0x7<<24)|(0x7<<16));
+ reg32_writep(&ccm_reg->bus_root[1].target_root_set, (0x4<<24)|(0x3<<16));
+
+ /* disable iso */
+ reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */
+ reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */
+
+ dram_pll_init(SSCG_PLL_OUT_800M);
+
+ reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
+
+ /* Configure uMCTL2's registers */
+ lpddr4_800MHz_cfg_umctl2();
+
+#ifdef DDR_BOOT_P2
+ reg32_write(DDRC_MSTR2(0), 0x2);
+#else
+#ifdef DDR_BOOT_P1
+ reg32_write(DDRC_MSTR2(0), 0x1);
+#endif
+#endif
+ /* release [1]ddr1_core_reset_n, [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n */
+ reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004);
+
+ /* release [1]ddr1_core_reset_n, [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n */
+ reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
+
+ reg32_write(DDRC_DBG1(0), 0x00000000);
+ tmp = reg32_read(DDRC_PWRCTL(0));
+ reg32_write(DDRC_PWRCTL(0), 0x000000a8);
+
+ while ((reg32_read(DDRC_STAT(0)) & 0x33f) != 0x223)
+ ;
+
+ reg32_write(DDRC_SWCTL(0), 0x00000000);
+
+ /* LPDDR4 mode */
+ reg32_write(DDRC_DDR_SS_GPR0, 0x01);
+
+#ifdef DDR_BOOT_P1
+ reg32_write(DDRC_DFIMISC(0), 0x00000110);
+#else
+ reg32_write(DDRC_DFIMISC(0), 0x00000010);
+#endif
+ /* LPDDR4 PHY config and training */
+ lpddr4_800M_cfg_phy();
+
+ reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
+
+ reg32_write(DDRC_SWCTL(0), 0x0000);
+
+ /* Set DFIMISC.dfi_init_start to 1 */
+#ifdef DDR_BOOT_P2
+ reg32_write(DDRC_DFIMISC(0), 0x00000230);
+#else
+#ifdef DDR_BOOT_P1
+ reg32_write(DDRC_DFIMISC(0), 0x00000130);
+#else
+ reg32_write(DDRC_DFIMISC(0), 0x00000030);
+#endif
+#endif
+ reg32_write(DDRC_SWCTL(0), 0x0001);
+
+ /* wait DFISTAT.dfi_init_complete to 1 */
+ while ((reg32_read(DDRC_DFISTAT(0)) & 0x1) == 0x0)
+ ;
+
+ reg32_write(DDRC_SWCTL(0), 0x0000);
+
+#ifdef DDR_BOOT_P2
+ reg32_write(DDRC_DFIMISC(0), 0x00000210);
+ /* set DFIMISC.dfi_init_complete_en again */
+ reg32_write(DDRC_DFIMISC(0), 0x00000211);
+#else
+#ifdef DDR_BOOT_P1
+ reg32_write(DDRC_DFIMISC(0), 0x00000110);
+ /* set DFIMISC.dfi_init_complete_en again */
+ reg32_write(DDRC_DFIMISC(0), 0x00000111);
+#else
+ /* clear DFIMISC.dfi_init_complete_en */
+ reg32_write(DDRC_DFIMISC(0), 0x00000010);
+ /* set DFIMISC.dfi_init_complete_en again */
+ reg32_write(DDRC_DFIMISC(0), 0x00000011);
+#endif
+#endif
+
+ reg32_write(DDRC_PWRCTL(0), 0x00000088);
+
+ tmp = reg32_read(DDRC_CRCPARSTAT(0));
+
+ /*
+ * set SWCTL.sw_done to enable quasi-dynamic register
+ * programming outside reset.
+ */
+ reg32_write(DDRC_SWCTL(0), 0x00000001);
+
+ /* wait SWSTAT.sw_done_ack to 1 */
+ while ((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0x0)
+ ;
+
+ /* wait STAT.operating_mode([1:0] for ddr3) to normal state */
+ while ((reg32_read(DDRC_STAT(0)) & 0x3) != 0x1)
+ ;
+
+ reg32_write(DDRC_PWRCTL(0), 0x00000088);
+
+ tmp = reg32_read(DDRC_CRCPARSTAT(0));
+
+ reg32_write(DDRC_PCTRL_0(0), 0x00000001);
+
+ tmp = reg32_read(DDRC_CRCPARSTAT(0));
+ reg32_write(DDRC_RFSHCTL3(0), 0x00000000);
+}
diff --git a/board/boundary/nitrogen8m/ddr/ddr_memory_map.h b/board/boundary/nitrogen8m/ddr/ddr_memory_map.h
new file mode 100644
index 0000000000000000000000000000000000000000..7386dbb0f10c310a5d72258bb52667f57720f5df
--- /dev/null
+++ b/board/boundary/nitrogen8m/ddr/ddr_memory_map.h
@@ -0,0 +1,2139 @@
+#define DDRC_DDR_SS_GPR0 0x3d000000
+
+#define DDRC_MSTR_0 0x3d400000
+#define DDRC_STAT_0 0x3d400004
+#define DDRC_MSTR1_0 0x3d400008
+#define DDRC_MRCTRL0_0 0x3d400010
+#define DDRC_MRCTRL1_0 0x3d400014
+#define DDRC_MRSTAT_0 0x3d400018
+#define DDRC_MRCTRL2_0 0x3d40001c
+#define DDRC_DERATEEN_0 0x3d400020
+#define DDRC_DERATEINT_0 0x3d400024
+#define DDRC_MSTR2_0 0x3d400028
+#define DDRC_PWRCTL_0 0x3d400030
+#define DDRC_PWRTMG_0 0x3d400034
+#define DDRC_HWLPCTL_0 0x3d400038
+#define DDRC_HWFFCCTL_0 0x3d40003c
+#define DDRC_HWFFCSTAT_0 0x3d400040
+#define DDRC_RFSHCTL0_0 0x3d400050
+#define DDRC_RFSHCTL1_0 0x3d400054
+#define DDRC_RFSHCTL2_0 0x3d400058
+#define DDRC_RFSHCTL3_0 0x3d400060
+#define DDRC_RFSHTMG_0 0x3d400064
+#define DDRC_ECCCFG0_0 0x3d400070
+#define DDRC_ECCCFG1_0 0x3d400074
+#define DDRC_ECCSTAT_0 0x3d400078
+#define DDRC_ECCCLR_0 0x3d40007c
+#define DDRC_ECCERRCNT_0 0x3d400080
+#define DDRC_ECCCADDR0_0 0x3d400084
+#define DDRC_ECCCADDR1_0 0x3d400088
+#define DDRC_ECCCSYN0_0 0x3d40008c
+#define DDRC_ECCCSYN1_0 0x3d400090
+#define DDRC_ECCCSYN2_0 0x3d400094
+#define DDRC_ECCBITMASK0_0 0x3d400098
+#define DDRC_ECCBITMASK1_0 0x3d40009c
+#define DDRC_ECCBITMASK2_0 0x3d4000a0
+#define DDRC_ECCUADDR0_0 0x3d4000a4
+#define DDRC_ECCUADDR1_0 0x3d4000a8
+#define DDRC_ECCUSYN0_0 0x3d4000ac
+#define DDRC_ECCUSYN1_0 0x3d4000b0
+#define DDRC_ECCUSYN2_0 0x3d4000b4
+#define DDRC_ECCPOISONADDR0_0 0x3d4000b8
+#define DDRC_ECCPOISONADDR1_0 0x3d4000bc
+#define DDRC_CRCPARCTL0_0 0x3d4000c0
+#define DDRC_CRCPARCTL1_0 0x3d4000c4
+#define DDRC_CRCPARCTL2_0 0x3d4000c8
+#define DDRC_CRCPARSTAT_0 0x3d4000cc
+#define DDRC_INIT0_0 0x3d4000d0
+#define DDRC_INIT1_0 0x3d4000d4
+#define DDRC_INIT2_0 0x3d4000d8
+#define DDRC_INIT3_0 0x3d4000dc
+#define DDRC_INIT4_0 0x3d4000e0
+#define DDRC_INIT5_0 0x3d4000e4
+#define DDRC_INIT6_0 0x3d4000e8
+#define DDRC_INIT7_0 0x3d4000ec
+#define DDRC_DIMMCTL_0 0x3d4000f0
+#define DDRC_RANKCTL_0 0x3d4000f4
+#define DDRC_DRAMTMG0_0 0x3d400100
+#define DDRC_DRAMTMG1_0 0x3d400104
+#define DDRC_DRAMTMG2_0 0x3d400108
+#define DDRC_DRAMTMG3_0 0x3d40010c
+#define DDRC_DRAMTMG4_0 0x3d400110
+#define DDRC_DRAMTMG5_0 0x3d400114
+#define DDRC_DRAMTMG6_0 0x3d400118
+#define DDRC_DRAMTMG7_0 0x3d40011c
+#define DDRC_DRAMTMG8_0 0x3d400120
+#define DDRC_DRAMTMG9_0 0x3d400124
+#define DDRC_DRAMTMG10_0 0x3d400128
+#define DDRC_DRAMTMG11_0 0x3d40012c
+#define DDRC_DRAMTMG12_0 0x3d400130
+#define DDRC_DRAMTMG13_0 0x3d400134
+#define DDRC_DRAMTMG14_0 0x3d400138
+#define DDRC_DRAMTMG15_0 0x3d40013C
+#define DDRC_DRAMTMG16_0 0x3d400140
+#define DDRC_DRAMTMG17_0 0x3d400144
+//
+#define DDRC_ZQCTL0_0 0x3d400180
+#define DDRC_ZQCTL1_0 0x3d400184
+#define DDRC_ZQCTL2_0 0x3d400188
+#define DDRC_ZQSTAT_0 0x3d40018c
+#define DDRC_DFITMG0_0 0x3d400190
+#define DDRC_DFITMG1_0 0x3d400194
+#define DDRC_DFILPCFG0_0 0x3d400198
+#define DDRC_DFILPCFG1_0 0x3d40019c
+#define DDRC_DFIUPD0_0 0x3d4001a0
+#define DDRC_DFIUPD1_0 0x3d4001a4
+#define DDRC_DFIUPD2_0 0x3d4001a8
+//#define DDRC_DFIUPD3(X) ( DDRC_IPS_BASE_ADDR(X) + 0x1ac) // iMX8 hasn't it
+#define DDRC_DFIMISC_0 0x3d4001b0
+#define DDRC_DFITMG2_0 0x3d4001b4
+#define DDRC_DFITMG3_0 0x3d4001b8
+#define DDRC_DFISTAT_0 0x3d4001bc
+//
+#define DDRC_DBICTL_0 0x3d4001c0
+#define DDRC_DFIPHYMSTR_0 0x3d4001c4
+#define DDRC_TRAINCTL0_0 0x3d4001d0
+#define DDRC_TRAINCTL1_0 0x3d4001d4
+#define DDRC_TRAINCTL2_0 0x3d4001d8
+#define DDRC_TRAINSTAT_0 0x3d4001dc
+#define DDRC_ADDRMAP0_0 0x3d400200
+#define DDRC_ADDRMAP1_0 0x3d400204
+#define DDRC_ADDRMAP2_0 0x3d400208
+#define DDRC_ADDRMAP3_0 0x3d40020c
+#define DDRC_ADDRMAP4_0 0x3d400210
+#define DDRC_ADDRMAP5_0 0x3d400214
+#define DDRC_ADDRMAP6_0 0x3d400218
+#define DDRC_ADDRMAP7_0 0x3d40021c
+#define DDRC_ADDRMAP8_0 0x3d400220
+#define DDRC_ADDRMAP9_0 0x3d400224
+#define DDRC_ADDRMAP10_0 0x3d400228
+#define DDRC_ADDRMAP11_0 0x3d40022c
+//
+#define DDRC_ODTCFG_0 0x3d400240
+#define DDRC_ODTMAP_0 0x3d400244
+#define DDRC_SCHED_0 0x3d400250
+#define DDRC_SCHED1_0 0x3d400254
+#define DDRC_PERFHPR1_0 0x3d40025c
+#define DDRC_PERFLPR1_0 0x3d400264
+#define DDRC_PERFWR1_0 0x3d40026c
+#define DDRC_PERFVPR1_0 0x3d400274
+//
+#define DDRC_PERFVPW1_0 0x3d400278
+//
+#define DDRC_DQMAP0_0 0x3d400280
+#define DDRC_DQMAP1_0 0x3d400284
+#define DDRC_DQMAP2_0 0x3d400288
+#define DDRC_DQMAP3_0 0x3d40028c
+#define DDRC_DQMAP4_0 0x3d400290
+#define DDRC_DQMAP5_0 0x3d400294
+#define DDRC_DBG0_0 0x3d400300
+#define DDRC_DBG1_0 0x3d400304
+#define DDRC_DBGCAM_0 0x3d400308
+#define DDRC_DBGCMD_0 0x3d40030c
+#define DDRC_DBGSTAT_0 0x3d400310
+//
+#define DDRC_SWCTL_0 0x3d400320
+#define DDRC_SWSTAT_0 0x3d400324
+#define DDRC_OCPARCFG0_0 0x3d400330
+#define DDRC_OCPARCFG1_0 0x3d400334
+#define DDRC_OCPARCFG2_0 0x3d400338
+#define DDRC_OCPARCFG3_0 0x3d40033c
+#define DDRC_OCPARSTAT0_0 0x3d400340
+#define DDRC_OCPARSTAT1_0 0x3d400344
+#define DDRC_OCPARWLOG0_0 0x3d400348
+#define DDRC_OCPARWLOG1_0 0x3d40034c
+#define DDRC_OCPARWLOG2_0 0x3d400350
+#define DDRC_OCPARAWLOG0_0 0x3d400354
+#define DDRC_OCPARAWLOG1_0 0x3d400358
+#define DDRC_OCPARRLOG0_0 0x3d40035c
+#define DDRC_OCPARRLOG1_0 0x3d400360
+#define DDRC_OCPARARLOG0_0 0x3d400364
+#define DDRC_OCPARARLOG1_0 0x3d400368
+#define DDRC_POISONCFG_0 0x3d40036C
+#define DDRC_POISONSTAT_0 0x3d400370
+#define DDRC_ADVECCINDEX_0 0x3d400003
+#define DDRC_ADVECCSTAT_0 0x3d400003
+#define DDRC_ECCPOISONPAT0_0 0x3d400003
+#define DDRC_ECCPOISONPAT1_0 0x3d400003
+#define DDRC_ECCPOISONPAT2_0 0x3d400003
+#define DDRC_HIFCTL_0 0x3d400003
+
+#define DDRC_PSTAT_0 0x3d4003fc
+#define DDRC_PCCFG_0 0x3d400400
+#define DDRC_PCFGR_0_0 0x3d400404
+#define DDRC_PCFGR_1_0 0x3d4004b4
+#define DDRC_PCFGR_2_0 0x3d400564
+#define DDRC_PCFGR_3_0 0x3d400614
+#define DDRC_PCFGW_0_0 0x3d400408
+#define DDRC_PCFGW_1_0 0x3d400408
+#define DDRC_PCFGW_2_0 0x3d400568
+#define DDRC_PCFGW_3_0 0x3d400618
+#define DDRC_PCFGC_0_0 0x3d40040c
+#define DDRC_PCFGIDMASKCH_0 0x3d400410
+#define DDRC_PCFGIDVALUECH_0 0x3d400414
+#define DDRC_PCTRL_0_0 0x3d400490
+#define DDRC_PCTRL_1_0 0x3d400540
+#define DDRC_PCTRL_2_0 0x3d4005f0
+#define DDRC_PCTRL_3_0 0x3d4006a0
+#define DDRC_PCFGQOS0_0_0 0x3d400494
+#define DDRC_PCFGQOS1_0_0 0x3d400498
+#define DDRC_PCFGWQOS0_0_0 0x3d40049c
+#define DDRC_PCFGWQOS1_0_0 0x3d4004a0
+#define DDRC_SARBASE0_0 0x3d400f04
+#define DDRC_SARSIZE0_0 0x3d400f08
+#define DDRC_SBRCTL_0 0x3d400f24
+#define DDRC_SBRSTAT_0 0x3d400f28
+#define DDRC_SBRWDATA0_0 0x3d400f2c
+#define DDRC_SBRWDATA1_0 0x3d400f30
+#define DDRC_PDCH_0 0x3d400f34
+
+/**********************/
+#define DDRC_MSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x00)
+#define DDRC_STAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x04)
+#define DDRC_MSTR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x08)
+#define DDRC_MRCTRL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x10)
+#define DDRC_MRCTRL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x14)
+#define DDRC_MRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18)
+#define DDRC_MRCTRL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c)
+#define DDRC_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x20)
+#define DDRC_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x24)
+#define DDRC_MSTR2(X) (DDRC_IPS_BASE_ADDR(X) + 0x28)
+#define DDRC_PWRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x30)
+#define DDRC_PWRTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x34)
+#define DDRC_HWLPCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x38)
+#define DDRC_HWFFCCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x3c)
+#define DDRC_HWFFCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x40)
+#define DDRC_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x50)
+#define DDRC_RFSHCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x54)
+#define DDRC_RFSHCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x58)
+#define DDRC_RFSHCTL3(X) (DDRC_IPS_BASE_ADDR(X) + 0x60)
+#define DDRC_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x64)
+#define DDRC_ECCCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x70)
+#define DDRC_ECCCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x74)
+#define DDRC_ECCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x78)
+#define DDRC_ECCCLR(X) (DDRC_IPS_BASE_ADDR(X) + 0x7c)
+#define DDRC_ECCERRCNT(X) (DDRC_IPS_BASE_ADDR(X) + 0x80)
+#define DDRC_ECCCADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0x84)
+#define DDRC_ECCCADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x88)
+#define DDRC_ECCCSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0x8c)
+#define DDRC_ECCCSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0x90)
+#define DDRC_ECCCSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0x94)
+#define DDRC_ECCBITMASK0(X) (DDRC_IPS_BASE_ADDR(X) + 0x98)
+#define DDRC_ECCBITMASK1(X) (DDRC_IPS_BASE_ADDR(X) + 0x9c)
+#define DDRC_ECCBITMASK2(X) (DDRC_IPS_BASE_ADDR(X) + 0xa0)
+#define DDRC_ECCUADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xa4)
+#define DDRC_ECCUADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xa8)
+#define DDRC_ECCUSYN0(X) (DDRC_IPS_BASE_ADDR(X) + 0xac)
+#define DDRC_ECCUSYN1(X) (DDRC_IPS_BASE_ADDR(X) + 0xb0)
+#define DDRC_ECCUSYN2(X) (DDRC_IPS_BASE_ADDR(X) + 0xb4)
+#define DDRC_ECCPOISONADDR0(X) (DDRC_IPS_BASE_ADDR(X) + 0xb8)
+#define DDRC_ECCPOISONADDR1(X) (DDRC_IPS_BASE_ADDR(X) + 0xbc)
+#define DDRC_CRCPARCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0xc0)
+#define DDRC_CRCPARCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0xc4)
+#define DDRC_CRCPARCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0xc8)
+#define DDRC_CRCPARSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xcc)
+#define DDRC_INIT0(X) (DDRC_IPS_BASE_ADDR(X) + 0xd0)
+#define DDRC_INIT1(X) (DDRC_IPS_BASE_ADDR(X) + 0xd4)
+#define DDRC_INIT2(X) (DDRC_IPS_BASE_ADDR(X) + 0xd8)
+#define DDRC_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0xdc)
+#define DDRC_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0xe0)
+#define DDRC_INIT5(X) (DDRC_IPS_BASE_ADDR(X) + 0xe4)
+#define DDRC_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0xe8)
+#define DDRC_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0xec)
+#define DDRC_DIMMCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf0)
+#define DDRC_RANKCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf4)
+#define DDRC_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x100)
+#define DDRC_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x104)
+#define DDRC_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x108)
+#define DDRC_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x10c)
+#define DDRC_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x110)
+#define DDRC_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x114)
+#define DDRC_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x118)
+#define DDRC_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x11c)
+#define DDRC_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x120)
+#define DDRC_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x124)
+#define DDRC_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x128)
+#define DDRC_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x12c)
+#define DDRC_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x130)
+#define DDRC_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x134)
+#define DDRC_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x138)
+#define DDRC_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x13C)
+#define DDRC_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x140)
+#define DDRC_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x144)
+//
+#define DDRC_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x180)
+#define DDRC_ZQCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x184)
+#define DDRC_ZQCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x188)
+#define DDRC_ZQSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x18c)
+#define DDRC_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x190)
+#define DDRC_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x194)
+#define DDRC_DFILPCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x198)
+#define DDRC_DFILPCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x19c)
+#define DDRC_DFIUPD0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a0)
+#define DDRC_DFIUPD1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a4)
+#define DDRC_DFIUPD2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1a8)
+//#define DDRC_DFIUPD3(X) ( DDRC_IPS_BASE_ADDR(X) + 0x1ac) // iMX8 hasn't it
+#define DDRC_DFIMISC(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b0)
+#define DDRC_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b4)
+#define DDRC_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x1b8)
+#define DDRC_DFISTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1bc)
+//
+#define DDRC_DBICTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c0)
+#define DDRC_DFIPHYMSTR(X) (DDRC_IPS_BASE_ADDR(X) + 0x1c4)
+#define DDRC_TRAINCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d0)
+#define DDRC_TRAINCTL1(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d4)
+#define DDRC_TRAINCTL2(X) (DDRC_IPS_BASE_ADDR(X) + 0x1d8)
+#define DDRC_TRAINSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x1dc)
+#define DDRC_ADDRMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x200)
+#define DDRC_ADDRMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x204)
+#define DDRC_ADDRMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x208)
+#define DDRC_ADDRMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20c)
+#define DDRC_ADDRMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x210)
+#define DDRC_ADDRMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x214)
+#define DDRC_ADDRMAP6(X) (DDRC_IPS_BASE_ADDR(X) + 0x218)
+#define DDRC_ADDRMAP7(X) (DDRC_IPS_BASE_ADDR(X) + 0x21c)
+#define DDRC_ADDRMAP8(X) (DDRC_IPS_BASE_ADDR(X) + 0x220)
+#define DDRC_ADDRMAP9(X) (DDRC_IPS_BASE_ADDR(X) + 0x224)
+#define DDRC_ADDRMAP10(X) (DDRC_IPS_BASE_ADDR(X) + 0x228)
+#define DDRC_ADDRMAP11(X) (DDRC_IPS_BASE_ADDR(X) + 0x22c)
+//
+#define DDRC_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x240)
+#define DDRC_ODTMAP(X) (DDRC_IPS_BASE_ADDR(X) + 0x244)
+#define DDRC_SCHED(X) (DDRC_IPS_BASE_ADDR(X) + 0x250)
+#define DDRC_SCHED1(X) (DDRC_IPS_BASE_ADDR(X) + 0x254)
+#define DDRC_PERFHPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x25c)
+#define DDRC_PERFLPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x264)
+#define DDRC_PERFWR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x26c)
+#define DDRC_PERFVPR1(X) (DDRC_IPS_BASE_ADDR(X) + 0x274)
+//
+#define DDRC_PERFVPW1(X) (DDRC_IPS_BASE_ADDR(X) + 0x278)
+//
+#define DDRC_DQMAP0(X) (DDRC_IPS_BASE_ADDR(X) + 0x280)
+#define DDRC_DQMAP1(X) (DDRC_IPS_BASE_ADDR(X) + 0x284)
+#define DDRC_DQMAP2(X) (DDRC_IPS_BASE_ADDR(X) + 0x288)
+#define DDRC_DQMAP3(X) (DDRC_IPS_BASE_ADDR(X) + 0x28c)
+#define DDRC_DQMAP4(X) (DDRC_IPS_BASE_ADDR(X) + 0x290)
+#define DDRC_DQMAP5(X) (DDRC_IPS_BASE_ADDR(X) + 0x294)
+#define DDRC_DBG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x300)
+#define DDRC_DBG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x304)
+#define DDRC_DBGCAM(X) (DDRC_IPS_BASE_ADDR(X) + 0x308)
+#define DDRC_DBGCMD(X) (DDRC_IPS_BASE_ADDR(X) + 0x30c)
+#define DDRC_DBGSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x310)
+//
+#define DDRC_SWCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x320)
+#define DDRC_SWSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x324)
+#define DDRC_OCPARCFG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x330)
+#define DDRC_OCPARCFG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x334)
+#define DDRC_OCPARCFG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x338)
+#define DDRC_OCPARCFG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x33c)
+#define DDRC_OCPARSTAT0(X) (DDRC_IPS_BASE_ADDR(X) + 0x340)
+#define DDRC_OCPARSTAT1(X) (DDRC_IPS_BASE_ADDR(X) + 0x344)
+#define DDRC_OCPARWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x348)
+#define DDRC_OCPARWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x34c)
+#define DDRC_OCPARWLOG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x350)
+#define DDRC_OCPARAWLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x354)
+#define DDRC_OCPARAWLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x358)
+#define DDRC_OCPARRLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x35c)
+#define DDRC_OCPARRLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x360)
+#define DDRC_OCPARARLOG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x364)
+#define DDRC_OCPARARLOG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x368)
+#define DDRC_POISONCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x36C)
+#define DDRC_POISONSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x370)
+#define DDRC_ADVECCINDEX(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
+#define DDRC_ADVECCSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
+#define DDRC_ECCPOISONPAT0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
+#define DDRC_ECCPOISONPAT1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
+#define DDRC_ECCPOISONPAT2(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
+#define DDRC_HIFCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0x3)
+
+#define DDRC_PSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3fc)
+#define DDRC_PCCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x400)
+#define DDRC_PCFGR_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x404)
+#define DDRC_PCFGR_1(X) (DDRC_IPS_BASE_ADDR(X) + 1*0xb0+0x404)
+#define DDRC_PCFGR_2(X) (DDRC_IPS_BASE_ADDR(X) + 2*0xb0+0x404)
+#define DDRC_PCFGR_3(X) (DDRC_IPS_BASE_ADDR(X) + 3*0xb0+0x404)
+#define DDRC_PCFGW_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x408)
+#define DDRC_PCFGW_1(X) (DDRC_IPS_BASE_ADDR(X) + 1*0xb0+0x408)
+#define DDRC_PCFGW_2(X) (DDRC_IPS_BASE_ADDR(X) + 2*0xb0+0x408)
+#define DDRC_PCFGW_3(X) (DDRC_IPS_BASE_ADDR(X) + 3*0xb0+0x408)
+#define DDRC_PCFGC_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x40c)
+#define DDRC_PCFGIDMASKCH(X) (DDRC_IPS_BASE_ADDR(X) + 0x410)
+#define DDRC_PCFGIDVALUECH(X) (DDRC_IPS_BASE_ADDR(X) + 0x414)
+#define DDRC_PCTRL_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x490)
+#define DDRC_PCTRL_1(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 1*0xb0)
+#define DDRC_PCTRL_2(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 2*0xb0)
+#define DDRC_PCTRL_3(X) (DDRC_IPS_BASE_ADDR(X) + 0x490 + 3*0xb0)
+#define DDRC_PCFGQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x494)
+#define DDRC_PCFGQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x498)
+#define DDRC_PCFGWQOS0_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x49c)
+#define DDRC_PCFGWQOS1_0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4a0)
+#define DDRC_SARBASE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf04)
+#define DDRC_SARSIZE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf08)
+#define DDRC_SBRCTL(X) (DDRC_IPS_BASE_ADDR(X) + 0xf24)
+#define DDRC_SBRSTAT(X) (DDRC_IPS_BASE_ADDR(X) + 0xf28)
+#define DDRC_SBRWDATA0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf2c)
+#define DDRC_SBRWDATA1(X) (DDRC_IPS_BASE_ADDR(X) + 0xf30)
+#define DDRC_PDCH(X) (DDRC_IPS_BASE_ADDR(X) + 0xf34)
+/*
+#define DDRC_PCFGW_0_0_ADDR ((vuint8_t*)&(DDRC_PCFGW_0(0)))
+#define DDRC_PCFGW_0_1_ADDR ((vuint8_t*)&(DDRC_PCFGW_0(1)))
+#define DDRC_PCFGW_0_2_ADDR ((vuint8_t*)&(DDRC_PCFGW_0(2)))
+#define DDRC_PCFGW_0_3_ADDR ((vuint8_t*)&(DDRC_PCFGW_0(3)))
+
+#define DDRC_MRCTRL1_0_ADDR ((vuint8_t*)&(DDRC_MRCTRL1(0)))
+#define DDRC_MRCTRL1_1_ADDR ((vuint8_t*)&(DDRC_MRCTRL1(1)))
+#define DDRC_MRCTRL1_2_ADDR ((vuint8_t*)&(DDRC_MRCTRL1(2)))
+#define DDRC_FREQ1_MRCTRL1_3_ADDR ((vuint8_t*)&(DDRC_MRCTRL1(3)))
+*/
+
+// SHADOW registers
+
+#define DDRC_FREQ1_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x2020)
+#define DDRC_FREQ1_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x2024)
+#define DDRC_FREQ1_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2050)
+#define DDRC_FREQ1_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2064)
+#define DDRC_FREQ1_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x20dc)
+#define DDRC_FREQ1_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e0)
+#define DDRC_FREQ1_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x20e8)
+#define DDRC_FREQ1_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x20ec)
+#define DDRC_FREQ1_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2100)
+#define DDRC_FREQ1_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2104)
+#define DDRC_FREQ1_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x2108)
+#define DDRC_FREQ1_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x210c)
+#define DDRC_FREQ1_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x2110)
+#define DDRC_FREQ1_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x2114)
+#define DDRC_FREQ1_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x2118)
+#define DDRC_FREQ1_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x211c)
+#define DDRC_FREQ1_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x2120)
+#define DDRC_FREQ1_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x2124)
+#define DDRC_FREQ1_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x2128)
+#define DDRC_FREQ1_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x212c)
+#define DDRC_FREQ1_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x2130)
+#define DDRC_FREQ1_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x2134)
+#define DDRC_FREQ1_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x2138)
+#define DDRC_FREQ1_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x213C)
+#define DDRC_FREQ1_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x2140)
+#define DDRC_FREQ1_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x2144)
+#define DDRC_FREQ1_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2180)
+#define DDRC_FREQ1_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190)
+#define DDRC_FREQ1_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194)
+#define DDRC_FREQ1_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4)
+#define DDRC_FREQ1_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8)
+#define DDRC_FREQ1_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240)
+
+#define DDRC_FREQ2_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x3020)
+#define DDRC_FREQ2_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x3024)
+#define DDRC_FREQ2_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3050)
+#define DDRC_FREQ2_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3064)
+#define DDRC_FREQ2_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x30dc)
+#define DDRC_FREQ2_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e0)
+#define DDRC_FREQ2_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x30e8)
+#define DDRC_FREQ2_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x30ec)
+#define DDRC_FREQ2_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3100)
+#define DDRC_FREQ2_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3104)
+#define DDRC_FREQ2_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x3108)
+#define DDRC_FREQ2_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x310c)
+#define DDRC_FREQ2_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x3110)
+#define DDRC_FREQ2_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x3114)
+#define DDRC_FREQ2_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x3118)
+#define DDRC_FREQ2_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x311c)
+#define DDRC_FREQ2_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x3120)
+#define DDRC_FREQ2_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x3124)
+#define DDRC_FREQ2_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x3128)
+#define DDRC_FREQ2_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x312c)
+#define DDRC_FREQ2_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x3130)
+#define DDRC_FREQ2_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x3134)
+#define DDRC_FREQ2_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x3138)
+#define DDRC_FREQ2_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x313C)
+#define DDRC_FREQ2_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x3140)
+#define DDRC_FREQ2_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x3144)
+#define DDRC_FREQ2_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3180)
+#define DDRC_FREQ2_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x3190)
+#define DDRC_FREQ2_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x3194)
+#define DDRC_FREQ2_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b4)
+#define DDRC_FREQ2_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x31b8)
+#define DDRC_FREQ2_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x3240)
+
+#define DDRC_FREQ3_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x4020)
+#define DDRC_FREQ3_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x4024)
+#define DDRC_FREQ3_RFSHCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4050)
+#define DDRC_FREQ3_RFSHTMG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4064)
+#define DDRC_FREQ3_INIT3(X) (DDRC_IPS_BASE_ADDR(X) + 0x40dc)
+#define DDRC_FREQ3_INIT4(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e0)
+#define DDRC_FREQ3_INIT6(X) (DDRC_IPS_BASE_ADDR(X) + 0x40e8)
+#define DDRC_FREQ3_INIT7(X) (DDRC_IPS_BASE_ADDR(X) + 0x40ec)
+#define DDRC_FREQ3_DRAMTMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4100)
+#define DDRC_FREQ3_DRAMTMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4104)
+#define DDRC_FREQ3_DRAMTMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x4108)
+#define DDRC_FREQ3_DRAMTMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x410c)
+#define DDRC_FREQ3_DRAMTMG4(X) (DDRC_IPS_BASE_ADDR(X) + 0x4110)
+#define DDRC_FREQ3_DRAMTMG5(X) (DDRC_IPS_BASE_ADDR(X) + 0x4114)
+#define DDRC_FREQ3_DRAMTMG6(X) (DDRC_IPS_BASE_ADDR(X) + 0x4118)
+#define DDRC_FREQ3_DRAMTMG7(X) (DDRC_IPS_BASE_ADDR(X) + 0x411c)
+#define DDRC_FREQ3_DRAMTMG8(X) (DDRC_IPS_BASE_ADDR(X) + 0x4120)
+#define DDRC_FREQ3_DRAMTMG9(X) (DDRC_IPS_BASE_ADDR(X) + 0x4124)
+#define DDRC_FREQ3_DRAMTMG10(X) (DDRC_IPS_BASE_ADDR(X) + 0x4128)
+#define DDRC_FREQ3_DRAMTMG11(X) (DDRC_IPS_BASE_ADDR(X) + 0x412c)
+#define DDRC_FREQ3_DRAMTMG12(X) (DDRC_IPS_BASE_ADDR(X) + 0x4130)
+#define DDRC_FREQ3_DRAMTMG13(X) (DDRC_IPS_BASE_ADDR(X) + 0x4134)
+#define DDRC_FREQ3_DRAMTMG14(X) (DDRC_IPS_BASE_ADDR(X) + 0x4138)
+#define DDRC_FREQ3_DRAMTMG15(X) (DDRC_IPS_BASE_ADDR(X) + 0x413C)
+#define DDRC_FREQ3_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x4140)
+#if 0
+/*todo fix*/
+#define DDRC_FREQ3_DRAMTMG16(X) (DDRC_IPS_BASE_ADDR(X) + 0x4144)
+#define DDRC_FREQ3_DRAMTMG17(X) (DDRC_IPS_BASE_ADDR(X) + 0x4140)
+#endif
+#define DDRC_FREQ3_ZQCTL0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4180)
+#define DDRC_FREQ3_DFITMG0(X) (DDRC_IPS_BASE_ADDR(X) + 0x4190)
+#define DDRC_FREQ3_DFITMG1(X) (DDRC_IPS_BASE_ADDR(X) + 0x4194)
+#define DDRC_FREQ3_DFITMG2(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b4)
+#define DDRC_FREQ3_DFITMG3(X) (DDRC_IPS_BASE_ADDR(X) + 0x41b8)
+#define DDRC_FREQ3_ODTCFG(X) (DDRC_IPS_BASE_ADDR(X) + 0x4240)
+#define DDRC_DFITMG0_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2190)
+#define DDRC_DFITMG1_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2194)
+#define DDRC_DFITMG2_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b4)
+#define DDRC_DFITMG3_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8)
+#define DDRC_ODTCFG_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240)
+
+//#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) DDRPHY1_IPS_BASE_ADDR - X*0x00030000
+//#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) 0xbc000000 + (X * 0x2000000)
+//#define DDRPHY_MEM(X) 0xbc000000 + (X * 0x2000000) + 0x50000
+#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000))
+#define DDRPHY_MEM(X) (0x3c000000 + (X * 0x2000000) + 0x50000)
+//#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) 0x3c000000 + (X * 0x2000000)
+
+#if 0
+/* todo: fix*/
+#define DDRPHY_AcsmSeq0x0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040000)
+#define DDRPHY_AcsmSeq0x1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040001)
+#define DDRPHY_AcsmSeq0x2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040002)
+#define DDRPHY_AcsmSeq0x3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040003)
+#define DDRPHY_AcsmSeq0x4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040004)
+#define DDRPHY_AcsmSeq0x5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040005)
+#define DDRPHY_AcsmSeq0x6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040006)
+#define DDRPHY_AcsmSeq0x7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040007)
+#define DDRPHY_AcsmSeq0x8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040008)
+#define DDRPHY_AcsmSeq0x9(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040009)
+#define DDRPHY_AcsmSeq0x10(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04000A)
+#define DDRPHY_AcsmSeq0x11(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04000B)
+#define DDRPHY_AcsmSeq0x12(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04000C)
+#define DDRPHY_AcsmSeq0x13(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04000D)
+#define DDRPHY_AcsmSeq0x14(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04000E)
+#define DDRPHY_AcsmSeq0x15(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04000F)
+#define DDRPHY_AcsmSeq0x16(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040010)
+#define DDRPHY_AcsmSeq0x17(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040011)
+#define DDRPHY_AcsmSeq0x18(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040012)
+#define DDRPHY_AcsmSeq0x19(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040013)
+#define DDRPHY_AcsmSeq0x20(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040014)
+#define DDRPHY_AcsmSeq0x21(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040015)
+#define DDRPHY_AcsmSeq0x22(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040016)
+#define DDRPHY_AcsmSeq0x23(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040017)
+#define DDRPHY_AcsmSeq0x24(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040018)
+#define DDRPHY_AcsmSeq0x25(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040019)
+#define DDRPHY_AcsmSeq0x26(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04001A)
+#define DDRPHY_AcsmSeq0x27(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04001B)
+#define DDRPHY_AcsmSeq0x28(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04001C)
+#define DDRPHY_AcsmSeq0x29(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04001D)
+#define DDRPHY_AcsmSeq0x30(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04001E)
+#define DDRPHY_AcsmSeq0x31(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04001F)
+
+#define DDRPHY_AcsmSeq1x0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040020)
+#define DDRPHY_AcsmSeq1x1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040021)
+#define DDRPHY_AcsmSeq1x2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040022)
+#define DDRPHY_AcsmSeq1x3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040023)
+#define DDRPHY_AcsmSeq1x4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040024)
+#define DDRPHY_AcsmSeq1x5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040025)
+#define DDRPHY_AcsmSeq1x6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040026)
+#define DDRPHY_AcsmSeq1x7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040027)
+#define DDRPHY_AcsmSeq1x8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040028)
+#define DDRPHY_AcsmSeq1x9(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040029)
+#define DDRPHY_AcsmSeq1x10(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04002A)
+#define DDRPHY_AcsmSeq1x11(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04002B)
+#define DDRPHY_AcsmSeq1x12(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04002C)
+#define DDRPHY_AcsmSeq1x13(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04002D)
+#define DDRPHY_AcsmSeq1x14(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04002E)
+#define DDRPHY_AcsmSeq1x15(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04002F)
+#define DDRPHY_AcsmSeq1x16(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040030)
+#define DDRPHY_AcsmSeq1x17(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040031)
+#define DDRPHY_AcsmSeq1x18(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040032)
+#define DDRPHY_AcsmSeq1x19(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040033)
+#define DDRPHY_AcsmSeq1x20(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040034)
+#define DDRPHY_AcsmSeq1x21(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040035)
+#define DDRPHY_AcsmSeq1x22(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040036)
+#define DDRPHY_AcsmSeq1x23(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040037)
+#define DDRPHY_AcsmSeq1x24(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040038)
+#define DDRPHY_AcsmSeq1x25(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040039)
+#define DDRPHY_AcsmSeq1x26(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04003A)
+#define DDRPHY_AcsmSeq1x27(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04003B)
+#define DDRPHY_AcsmSeq1x28(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04003C)
+#define DDRPHY_AcsmSeq1x29(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04003D)
+#define DDRPHY_AcsmSeq1x30(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04003E)
+#define DDRPHY_AcsmSeq1x31(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04003F)
+
+#define DDRPHY_AcsmSeq2x0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040040)
+#define DDRPHY_AcsmSeq2x1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040041)
+#define DDRPHY_AcsmSeq2x2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040042)
+#define DDRPHY_AcsmSeq2x3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040043)
+#define DDRPHY_AcsmSeq2x4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040044)
+#define DDRPHY_AcsmSeq2x5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040045)
+#define DDRPHY_AcsmSeq2x6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040046)
+#define DDRPHY_AcsmSeq2x7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040047)
+#define DDRPHY_AcsmSeq2x8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040048)
+#define DDRPHY_AcsmSeq2x9(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040049)
+#define DDRPHY_AcsmSeq2x10(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04004A)
+#define DDRPHY_AcsmSeq2x11(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04004B)
+#define DDRPHY_AcsmSeq2x12(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04004C)
+#define DDRPHY_AcsmSeq2x13(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04004D)
+#define DDRPHY_AcsmSeq2x14(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04004E)
+#define DDRPHY_AcsmSeq2x15(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04004F)
+#define DDRPHY_AcsmSeq2x16(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040050)
+#define DDRPHY_AcsmSeq2x17(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040051)
+#define DDRPHY_AcsmSeq2x18(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040052)
+#define DDRPHY_AcsmSeq2x19(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040053)
+#define DDRPHY_AcsmSeq2x20(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040054)
+#define DDRPHY_AcsmSeq2x21(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040055)
+#define DDRPHY_AcsmSeq2x22(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040056)
+#define DDRPHY_AcsmSeq2x23(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040057)
+#define DDRPHY_AcsmSeq2x24(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040058)
+#define DDRPHY_AcsmSeq2x25(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040059)
+#define DDRPHY_AcsmSeq2x26(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04005A)
+#define DDRPHY_AcsmSeq2x27(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04005B)
+#define DDRPHY_AcsmSeq2x28(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04005C)
+#define DDRPHY_AcsmSeq2x29(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04005D)
+#define DDRPHY_AcsmSeq2x30(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04005E)
+#define DDRPHY_AcsmSeq2x31(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04005F)
+
+#define DDRPHY_AcsmSeq3x0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040060)
+#define DDRPHY_AcsmSeq3x1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040061)
+#define DDRPHY_AcsmSeq3x2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040062)
+#define DDRPHY_AcsmSeq3x3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040063)
+#define DDRPHY_AcsmSeq3x4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040064)
+#define DDRPHY_AcsmSeq3x5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040065)
+#define DDRPHY_AcsmSeq3x6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040066)
+#define DDRPHY_AcsmSeq3x7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040067)
+#define DDRPHY_AcsmSeq3x8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040068)
+#define DDRPHY_AcsmSeq3x9(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040069)
+#define DDRPHY_AcsmSeq3x10(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04006A)
+#define DDRPHY_AcsmSeq3x11(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04006B)
+#define DDRPHY_AcsmSeq3x12(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04006C)
+#define DDRPHY_AcsmSeq3x13(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04006D)
+#define DDRPHY_AcsmSeq3x14(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04006E)
+#define DDRPHY_AcsmSeq3x15(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04006F)
+#define DDRPHY_AcsmSeq3x16(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040070)
+#define DDRPHY_AcsmSeq3x17(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040071)
+#define DDRPHY_AcsmSeq3x18(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040072)
+#define DDRPHY_AcsmSeq3x19(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040073)
+#define DDRPHY_AcsmSeq3x20(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040074)
+#define DDRPHY_AcsmSeq3x21(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040075)
+#define DDRPHY_AcsmSeq3x22(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040076)
+#define DDRPHY_AcsmSeq3x23(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040077)
+#define DDRPHY_AcsmSeq3x24(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040078)
+#define DDRPHY_AcsmSeq3x25(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040079)
+#define DDRPHY_AcsmSeq3x26(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04007A)
+#define DDRPHY_AcsmSeq3x27(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04007B)
+#define DDRPHY_AcsmSeq3x28(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04007C)
+#define DDRPHY_AcsmSeq3x29(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04007D)
+#define DDRPHY_AcsmSeq3x30(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04007E)
+#define DDRPHY_AcsmSeq3x31(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04007F)
+
+#define DDRPHY_AcsmPlayback0x0_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040080)
+#define DDRPHY_AcsmPlayback0x0_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x140080)
+#define DDRPHY_AcsmPlayback0x0_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x240080)
+#define DDRPHY_AcsmPlayback0x0_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x340080)
+
+#define DDRPHY_AcsmPlayback1x0_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040081)
+#define DDRPHY_AcsmPlayback1x0_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x140081)
+#define DDRPHY_AcsmPlayback1x0_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x240081)
+#define DDRPHY_AcsmPlayback1x0_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x340081)
+
+#define DDRPHY_AcsmPlayback0x1_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040082)
+#define DDRPHY_AcsmPlayback0x1_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x140082)
+#define DDRPHY_AcsmPlayback0x1_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x240082)
+#define DDRPHY_AcsmPlayback0x1_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x340082)
+
+#define DDRPHY_AcsmPlayback1x1_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040083)
+#define DDRPHY_AcsmPlayback1x1_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x140083)
+#define DDRPHY_AcsmPlayback1x1_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x240083)
+#define DDRPHY_AcsmPlayback1x1_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x340083)
+
+#define DDRPHY_AcsmPlayback0x2_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040084)
+#define DDRPHY_AcsmPlayback0x2_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x140084)
+#define DDRPHY_AcsmPlayback0x2_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x240084)
+#define DDRPHY_AcsmPlayback0x2_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x340084)
+
+#define DDRPHY_AcsmPlayback1x2_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040085)
+#define DDRPHY_AcsmPlayback1x2_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x140085)
+#define DDRPHY_AcsmPlayback1x2_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x240085)
+#define DDRPHY_AcsmPlayback1x2_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x340085)
+
+#define DDRPHY_AcsmPlayback0x3_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040086)
+#define DDRPHY_AcsmPlayback0x3_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x140086)
+#define DDRPHY_AcsmPlayback0x3_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x240086)
+#define DDRPHY_AcsmPlayback0x3_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x340086)
+
+#define DDRPHY_AcsmPlayback1x3_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040087)
+#define DDRPHY_AcsmPlayback1x3_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x140087)
+#define DDRPHY_AcsmPlayback1x3_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x240087)
+#define DDRPHY_AcsmPlayback1x3_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x340087)
+
+#define DDRPHY_AcsmPlayback0x4_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040088)
+#define DDRPHY_AcsmPlayback0x4_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x140088)
+#define DDRPHY_AcsmPlayback0x4_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x240088)
+#define DDRPHY_AcsmPlayback0x4_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x340088)
+
+#define DDRPHY_AcsmPlayback1x4_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x040089)
+#define DDRPHY_AcsmPlayback1x4_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x140089)
+#define DDRPHY_AcsmPlayback1x4_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x240089)
+#define DDRPHY_AcsmPlayback1x4_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x340089)
+
+#define DDRPHY_AcsmPlayback0x5_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04008A)
+#define DDRPHY_AcsmPlayback0x5_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x14008A)
+#define DDRPHY_AcsmPlayback0x5_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x24008A)
+#define DDRPHY_AcsmPlayback0x5_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x34008A)
+
+#define DDRPHY_AcsmPlayback1x5_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04008B)
+#define DDRPHY_AcsmPlayback1x5_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x14008B)
+#define DDRPHY_AcsmPlayback1x5_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x24008B)
+#define DDRPHY_AcsmPlayback1x5_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x34008B)
+
+#define DDRPHY_AcsmPlayback0x6_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04008C)
+#define DDRPHY_AcsmPlayback0x6_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x14008C)
+#define DDRPHY_AcsmPlayback0x6_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x24008C)
+#define DDRPHY_AcsmPlayback0x6_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x34008C)
+
+#define DDRPHY_AcsmPlayback1x6_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04008D)
+#define DDRPHY_AcsmPlayback1x6_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x14008D)
+#define DDRPHY_AcsmPlayback1x6_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x24008D)
+#define DDRPHY_AcsmPlayback1x6_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x34008D)
+
+#define DDRPHY_AcsmPlayback0x7_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04008E)
+#define DDRPHY_AcsmPlayback0x7_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x14008E)
+#define DDRPHY_AcsmPlayback0x7_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x24008E)
+#define DDRPHY_AcsmPlayback0x7_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x34008E)
+
+#define DDRPHY_AcsmPlayback1x7_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x04008F)
+#define DDRPHY_AcsmPlayback1x7_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x14008F)
+#define DDRPHY_AcsmPlayback1x7_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x24008F)
+#define DDRPHY_AcsmPlayback1x7_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x34008F)
+
+#define DDRPHY_AcsmCtrl23(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400C0)
+#define DDRPHY_AcsmCkeVal(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400C2)
+#define DDRPHY_LowSpeedClockDivider(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400C8)
+#define DDRPHY_AcsmCsMapCtrl0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400D0)
+#define DDRPHY_AcsmCsMapCtrl1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400D1)
+#define DDRPHY_AcsmCsMapCtrl2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400D2)
+#define DDRPHY_AcsmCsMapCtrl3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400D3)
+#define DDRPHY_AcsmCsMapCtrl4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400D4)
+#define DDRPHY_AcsmCsMapCtrl5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400D5)
+#define DDRPHY_AcsmCsMapCtrl6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400D6)
+#define DDRPHY_AcsmCsMapCtrl7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400D7)
+#define DDRPHY_AcsmCsMapCtrl8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400D8)
+#define DDRPHY_AcsmCsMapCtrl9(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400D9)
+#define DDRPHY_AcsmCsMapCtrl10(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400DA)
+#define DDRPHY_AcsmCsMapCtrl11(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400DB)
+#define DDRPHY_AcsmCsMapCtrl12(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400DC)
+#define DDRPHY_AcsmCsMapCtrl13(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400DD)
+#define DDRPHY_AcsmCsMapCtrl14(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400DE)
+#define DDRPHY_AcsmCsMapCtrl15(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400DF)
+
+#define DDRPHY_AcsmOdtCtrl0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400E0)
+#define DDRPHY_AcsmOdtCtrl1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400E1)
+#define DDRPHY_AcsmOdtCtrl2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400E2)
+#define DDRPHY_AcsmOdtCtrl3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400E3)
+#define DDRPHY_AcsmOdtCtrl4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400E4)
+#define DDRPHY_AcsmOdtCtrl5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400E5)
+#define DDRPHY_AcsmOdtCtrl6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400E6)
+#define DDRPHY_AcsmOdtCtrl7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400E7)
+#define DDRPHY_AcsmOdtCtrl8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400E8)
+#define DDRPHY_AcsmCtrl16(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400E9)
+#define DDRPHY_AcsmCtrl18(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400EB)
+#define DDRPHY_AcsmCtrl19(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400EC)
+#define DDRPHY_AcsmCtrl20(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400ED)
+#define DDRPHY_AcsmCtrl21(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400EE)
+#define DDRPHY_AcsmCtrl22(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400EF)
+#define DDRPHY_AcsmCtrl0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400F0)
+#define DDRPHY_AcsmCtrl1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400F1)
+#define DDRPHY_AcsmCtrl2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400F2)
+#define DDRPHY_AcsmCtrl3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400F3)
+#define DDRPHY_AcsmCtrl4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400F4)
+#define DDRPHY_AcsmCtrl5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400F5)
+#define DDRPHY_AcsmCtrl6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400F6)
+#define DDRPHY_AcsmCtrl7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400F7)
+#define DDRPHY_AcsmCtrl8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400F8)
+#define DDRPHY_AcsmCtrl9(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400F9)
+#define DDRPHY_AcsmCtrl10(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400FA)
+#define DDRPHY_AcsmCtrl11(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400FB)
+#define DDRPHY_AcsmCtrl12(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400FC)
+#define DDRPHY_AcsmCtrl13(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400FD)
+#define DDRPHY_AcsmCtrl14(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400FE)
+#define DDRPHY_AcsmCtrl15(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0400FF)
+
+#define DDRPHY_MtestMuxSel(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x00001A)
+#define DDRPHY_AForceTriCont(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x000028)
+#define DDRPHY_ATxImpedance(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x000043)
+#define DDRPHY_ATestPrbsErr(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x000053)
+#define DDRPHY_ATxSlewRate(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x000055)
+#define DDRPHY_ATestPrbsErrCnt(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x000056)
+#define DDRPHY_ATxDly_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x000080)
+#define DDRPHY_ATxDly_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x100080)
+#define DDRPHY_ATxDly_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x200080)
+#define DDRPHY_ATxDly_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x300080)
+
+#define DDRPHY_MicroContMuxSel(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0D0000)
+#define DDRPHY_UctShadowRegs(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0D0004)
+#define DDRPHY_DctWriteOnly(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0D0030)
+#define DDRPHY_DctWriteProt(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0D0031)
+#define DDRPHY_UctWriteOnlyShadow(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0D0032)
+#define DDRPHY_UctDatWriteOnlyShadow(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0D0034)
+#define DDRPHY_NeverGateCsrClock(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0D0035)
+#define DDRPHY_DfiCfgRdDataValidTicks(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0D0037)
+#define DDRPHY_MicroReset(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0D0099)
+#define DDRPHY_SequencerOverride(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0D00E7)
+#define DDRPHY_DfiInitCompleteShadow(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0D00FA)
+
+#define DDRPHY_DbyteMiscMode(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010000)
+#define DDRPHY_TsmByte0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010001)
+#define DDRPHY_TrainingParam(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010002)
+#define DDRPHY_RxTrainPatternEnable(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010010)
+#define DDRPHY_TsmByte1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010011)
+#define DDRPHY_TsmByte2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010012)
+#define DDRPHY_TsmByte3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010013)
+#define DDRPHY_TsmByte4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010014)
+#define DDRPHY_TestModeConfig(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010017)
+#define DDRPHY_TsmByte5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010018)
+#define DDRPHY_MtestMuxSel(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01001A)
+#define DDRPHY_DtsmTrainModeCtrl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01001F)
+#define DDRPHY_DFIMRL_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010020)
+#define DDRPHY_DFIMRL_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110020)
+#define DDRPHY_DFIMRL_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210020)
+#define DDRPHY_DFIMRL_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310020)
+#define DDRPHY_TrainingCntrFineMax_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010022)
+#define DDRPHY_TrainingCntrFineMax_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010122)
+#define DDRPHY_TrainingCntrFineMax_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010222)
+#define DDRPHY_TrainingCntrFineMax_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010322)
+#define DDRPHY_TrainingCntrFineMax_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010422)
+#define DDRPHY_TrainingCntrFineMax_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010522)
+#define DDRPHY_TrainingCntrFineMax_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010622)
+#define DDRPHY_TrainingCntrFineMax_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010722)
+#define DDRPHY_TrainingCntrFineMax_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010822)
+#define DDRPHY_TrainingCntrFineMaxRxEn_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010023)
+#define DDRPHY_TrainingCntrFineMaxRxEn_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010123)
+
+#define DDRPHY_AsyncDbyteMode(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010024)
+#define DDRPHY_AsyncDbyteTxEn(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010026)
+#define DDRPHY_AsyncDbyteTxData(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010028)
+#define DDRPHY_AsyncDbyteRxData(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01002A)
+#define DDRPHY_VrefDAC1_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010030)
+#define DDRPHY_VrefDAC1_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010130)
+#define DDRPHY_VrefDAC1_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010230)
+#define DDRPHY_VrefDAC1_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010330)
+#define DDRPHY_VrefDAC1_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010430)
+#define DDRPHY_VrefDAC1_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010530)
+#define DDRPHY_VrefDAC1_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010630)
+#define DDRPHY_VrefDAC1_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010730)
+#define DDRPHY_VrefDAC1_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010830)
+
+#define DDRPHY_TrainingCntr_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010032)
+#define DDRPHY_TrainingCntr_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010132)
+#define DDRPHY_TrainingCntr_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010232)
+#define DDRPHY_TrainingCntr_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010332)
+#define DDRPHY_TrainingCntr_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010432)
+#define DDRPHY_TrainingCntr_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010532)
+#define DDRPHY_TrainingCntr_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010632)
+#define DDRPHY_TrainingCntr_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010732)
+#define DDRPHY_TrainingCntr_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010832)
+
+#define DDRPHY_VrefDAC0_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010040)
+#define DDRPHY_VrefDAC0_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010140)
+#define DDRPHY_VrefDAC0_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010240)
+#define DDRPHY_VrefDAC0_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010340)
+#define DDRPHY_VrefDAC0_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010440)
+#define DDRPHY_VrefDAC0_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010540)
+#define DDRPHY_VrefDAC0_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010640)
+#define DDRPHY_VrefDAC0_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010740)
+#define DDRPHY_VrefDAC0_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010840)
+
+#define DDRPHY_TxImpedanceDq_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010041)
+#define DDRPHY_TxImpedanceDq_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010141)
+#define DDRPHY_TxImpedanceDq_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110041)
+#define DDRPHY_TxImpedanceDq_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110141)
+#define DDRPHY_TxImpedanceDq_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210041)
+#define DDRPHY_TxImpedanceDq_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210141)
+#define DDRPHY_TxImpedanceDq_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310041)
+#define DDRPHY_TxImpedanceDq_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310141)
+
+#define DDRPHY_DqDqsRcvCntrl_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010043)
+#define DDRPHY_DqDqsRcvCntrl_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010143)
+#define DDRPHY_DqDqsRcvCntrl_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110043)
+#define DDRPHY_DqDqsRcvCntrl_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110143)
+#define DDRPHY_DqDqsRcvCntrl_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210043)
+#define DDRPHY_DqDqsRcvCntrl_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210143)
+#define DDRPHY_DqDqsRcvCntrl_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310043)
+#define DDRPHY_DqDqsRcvCntrl_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310143)
+
+#define DDRPHY_TxEqualizationMode_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010048)
+#define DDRPHY_TxEqualizationMode_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110048)
+#define DDRPHY_TxEqualizationMode_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210048)
+#define DDRPHY_TxEqualizationMode_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310048)
+
+#define DDRPHY_TxEqImpedanceDq_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010049)
+#define DDRPHY_TxEqImpedanceDq_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010149)
+#define DDRPHY_TxEqImpedanceDq_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110049)
+#define DDRPHY_TxEqImpedanceDq_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110149)
+#define DDRPHY_TxEqImpedanceDq_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210049)
+#define DDRPHY_TxEqImpedanceDq_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210149)
+#define DDRPHY_TxEqImpedanceDq_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310049)
+#define DDRPHY_TxEqImpedanceDq_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310149)
+
+#define DDRPHY_DqDqsRcvCntrl1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01004A)
+
+#define DDRPHY_TxEqHiImpedanceDq_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01004B)
+#define DDRPHY_TxEqHiImpedanceDq_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01014B)
+#define DDRPHY_TxEqHiImpedanceDq_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11004B)
+#define DDRPHY_TxEqHiImpedanceDq_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11014B)
+#define DDRPHY_TxEqHiImpedanceDq_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21004B)
+#define DDRPHY_TxEqHiImpedanceDq_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21014B)
+#define DDRPHY_TxEqHiImpedanceDq_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31004B)
+#define DDRPHY_TxEqHiImpedanceDq_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31014B)
+
+#define DDRPHY_DqDqsRcvCntrl2_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01004C)
+#define DDRPHY_DqDqsRcvCntrl2_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11004C)
+#define DDRPHY_DqDqsRcvCntrl2_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21004C)
+#define DDRPHY_DqDqsRcvCntrl2_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31004C)
+
+#define DDRPHY_TxOdtDrvStren_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01004D)
+#define DDRPHY_TxOdtDrvStren_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01014D)
+#define DDRPHY_TxOdtDrvStren_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11004D)
+#define DDRPHY_TxOdtDrvStren_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11014D)
+#define DDRPHY_TxOdtDrvStren_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21004D)
+#define DDRPHY_TxOdtDrvStren_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21014D)
+#define DDRPHY_TxOdtDrvStren_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31004D)
+#define DDRPHY_TxOdtDrvStren_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31014D)
+
+#define DDRPHY_RxFifoInfo(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010058)
+#define DDRPHY_RxFifoVisibility(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010059)
+#define DDRPHY_RxFifoContentsDQ3210(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01005A)
+#define DDRPHY_RxFifoContentsDQ7654(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01005B)
+#define DDRPHY_RxFifoContentsDBI(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01005C)
+
+#define DDRPHY_TxSlewRate_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01005F)
+#define DDRPHY_TxSlewRate_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01015F)
+#define DDRPHY_TxSlewRate_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11005F)
+#define DDRPHY_TxSlewRate_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11015F)
+#define DDRPHY_TxSlewRate_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21005F)
+#define DDRPHY_TxSlewRate_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21015F)
+#define DDRPHY_TxSlewRate_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31005F)
+#define DDRPHY_TxSlewRate_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31015F)
+
+#define DDRPHY_TrainingIncDecDtsmEn_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010062)
+#define DDRPHY_TrainingIncDecDtsmEn_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010162)
+#define DDRPHY_TrainingIncDecDtsmEn_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010262)
+#define DDRPHY_TrainingIncDecDtsmEn_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010362)
+#define DDRPHY_TrainingIncDecDtsmEn_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010462)
+#define DDRPHY_TrainingIncDecDtsmEn_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010562)
+#define DDRPHY_TrainingIncDecDtsmEn_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010662)
+#define DDRPHY_TrainingIncDecDtsmEn_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010762)
+#define DDRPHY_TrainingIncDecDtsmEn_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010862)
+
+#define DDRPHY_RxPBDlyTg0_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010068)
+#define DDRPHY_RxPBDlyTg0_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010168)
+#define DDRPHY_RxPBDlyTg0_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010268)
+#define DDRPHY_RxPBDlyTg0_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010368)
+#define DDRPHY_RxPBDlyTg0_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010468)
+#define DDRPHY_RxPBDlyTg0_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010568)
+#define DDRPHY_RxPBDlyTg0_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010668)
+#define DDRPHY_RxPBDlyTg0_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010768)
+#define DDRPHY_RxPBDlyTg0_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010868)
+
+#define DDRPHY_RxPBDlyTg1_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010069)
+#define DDRPHY_RxPBDlyTg1_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010169)
+#define DDRPHY_RxPBDlyTg1_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010269)
+#define DDRPHY_RxPBDlyTg1_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010369)
+#define DDRPHY_RxPBDlyTg1_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010469)
+#define DDRPHY_RxPBDlyTg1_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010569)
+#define DDRPHY_RxPBDlyTg1_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010669)
+#define DDRPHY_RxPBDlyTg1_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010769)
+#define DDRPHY_RxPBDlyTg1_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010869)
+
+#define DDRPHY_RxPBDlyTg2_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01006A)
+#define DDRPHY_RxPBDlyTg2_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01016A)
+#define DDRPHY_RxPBDlyTg2_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01026A)
+#define DDRPHY_RxPBDlyTg2_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01036A)
+#define DDRPHY_RxPBDlyTg2_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01046A)
+#define DDRPHY_RxPBDlyTg2_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01056A)
+#define DDRPHY_RxPBDlyTg2_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01066A)
+#define DDRPHY_RxPBDlyTg2_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01076A)
+#define DDRPHY_RxPBDlyTg2_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01086A)
+
+#define DDRPHY_RxPBDlyTg3_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01006B)
+#define DDRPHY_RxPBDlyTg3_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01016B)
+#define DDRPHY_RxPBDlyTg3_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01026B)
+#define DDRPHY_RxPBDlyTg3_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01036B)
+#define DDRPHY_RxPBDlyTg3_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01046B)
+#define DDRPHY_RxPBDlyTg3_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01056B)
+#define DDRPHY_RxPBDlyTg3_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01066B)
+#define DDRPHY_RxPBDlyTg3_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01076B)
+#define DDRPHY_RxPBDlyTg3_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01086B)
+
+#define DDRPHY_RxEnDlyTg0_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010080)
+#define DDRPHY_RxEnDlyTg0_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010180)
+#define DDRPHY_RxEnDlyTg0_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110080)
+#define DDRPHY_RxEnDlyTg0_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110180)
+#define DDRPHY_RxEnDlyTg0_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210080)
+#define DDRPHY_RxEnDlyTg0_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210180)
+#define DDRPHY_RxEnDlyTg0_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310080)
+#define DDRPHY_RxEnDlyTg0_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310180)
+
+#define DDRPHY_RxEnDlyTg1_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010081)
+#define DDRPHY_RxEnDlyTg1_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010181)
+#define DDRPHY_RxEnDlyTg1_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110081)
+#define DDRPHY_RxEnDlyTg1_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110181)
+#define DDRPHY_RxEnDlyTg1_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210081)
+#define DDRPHY_RxEnDlyTg1_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210181)
+#define DDRPHY_RxEnDlyTg1_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310081)
+#define DDRPHY_RxEnDlyTg1_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310181)
+
+#define DDRPHY_RxEnDlyTg2_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010082)
+#define DDRPHY_RxEnDlyTg2_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010182)
+#define DDRPHY_RxEnDlyTg2_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110082)
+#define DDRPHY_RxEnDlyTg2_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110182)
+#define DDRPHY_RxEnDlyTg2_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210082)
+#define DDRPHY_RxEnDlyTg2_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210182)
+#define DDRPHY_RxEnDlyTg2_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310082)
+#define DDRPHY_RxEnDlyTg2_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310182)
+
+#define DDRPHY_RxEnDlyTg3_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010083)
+#define DDRPHY_RxEnDlyTg3_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x010183)
+#define DDRPHY_RxEnDlyTg3_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110083)
+#define DDRPHY_RxEnDlyTg3_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x110183)
+#define DDRPHY_RxEnDlyTg3_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210083)
+#define DDRPHY_RxEnDlyTg3_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x210183)
+#define DDRPHY_RxEnDlyTg3_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310083)
+#define DDRPHY_RxEnDlyTg3_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x310183)
+
+#define DDRPHY_RxClkDlyTg0_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01008C)
+#define DDRPHY_RxClkDlyTg0_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01018C)
+#define DDRPHY_RxClkDlyTg0_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11008C)
+#define DDRPHY_RxClkDlyTg0_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11018C)
+#define DDRPHY_RxClkDlyTg0_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21008C)
+#define DDRPHY_RxClkDlyTg0_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21018C)
+#define DDRPHY_RxClkDlyTg0_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31008C)
+#define DDRPHY_RxClkDlyTg0_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31018C)
+
+#define DDRPHY_RxClkDlyTg1_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01008D)
+#define DDRPHY_RxClkDlyTg1_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01018D)
+#define DDRPHY_RxClkDlyTg1_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11008D)
+#define DDRPHY_RxClkDlyTg1_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11018D)
+#define DDRPHY_RxClkDlyTg1_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21008D)
+#define DDRPHY_RxClkDlyTg1_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21018D)
+#define DDRPHY_RxClkDlyTg1_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31008D)
+#define DDRPHY_RxClkDlyTg1_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31018D)
+
+#define DDRPHY_RxClkDlyTg2_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01008E)
+#define DDRPHY_RxClkDlyTg2_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01018E)
+#define DDRPHY_RxClkDlyTg2_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11008E)
+#define DDRPHY_RxClkDlyTg2_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11018E)
+#define DDRPHY_RxClkDlyTg2_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21008E)
+#define DDRPHY_RxClkDlyTg2_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21018E)
+#define DDRPHY_RxClkDlyTg2_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31008E)
+#define DDRPHY_RxClkDlyTg2_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31018E)
+
+#define DDRPHY_RxClkDlyTg3_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01008F)
+#define DDRPHY_RxClkDlyTg3_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x01018F)
+#define DDRPHY_RxClkDlyTg3_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11008F)
+#define DDRPHY_RxClkDlyTg3_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x11018F)
+#define DDRPHY_RxClkDlyTg3_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21008F)
+#define DDRPHY_RxClkDlyTg3_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x21018F)
+#define DDRPHY_RxClkDlyTg3_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31008F)
+#define DDRPHY_RxClkDlyTg3_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x31018F)
+
+#define DDRPHY_Dq0LnSel(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100A0)
+#define DDRPHY_Dq1LnSel(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100A1)
+#define DDRPHY_Dq2LnSel(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100A2)
+#define DDRPHY_Dq3LnSel(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100A3)
+#define DDRPHY_Dq4LnSel(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100A4)
+#define DDRPHY_Dq5LnSel(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100A5)
+#define DDRPHY_Dq6LnSel(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100A6)
+#define DDRPHY_Dq7LnSel(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100A7)
+#define DDRPHY_PptCtlStatic(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100AA)
+#define DDRPHY_PptCtlDyn(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100AB)
+#define DDRPHY_PptInfo(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100AC)
+#define DDRPHY_PptRxEnEvnt(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100AD)
+#define DDRPHY_PptDqsCntInvTrnTg0_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100AE)
+#define DDRPHY_PptDqsCntInvTrnTg0_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1100AE)
+#define DDRPHY_PptDqsCntInvTrnTg0_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2100AE)
+#define DDRPHY_PptDqsCntInvTrnTg0_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3100AE)
+
+#define DDRPHY_PptDqsCntInvTrnTg1_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100AF)
+#define DDRPHY_PptDqsCntInvTrnTg1_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1100AF)
+#define DDRPHY_PptDqsCntInvTrnTg1_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2100AF)
+#define DDRPHY_PptDqsCntInvTrnTg1_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3100AF)
+
+#define DDRPHY_DtsmBlankingCtrl_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100B1)
+
+#define DDRPHY_Tsm0_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100B2)
+#define DDRPHY_Tsm0_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0101B2)
+#define DDRPHY_Tsm0_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0102B2)
+#define DDRPHY_Tsm0_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0103B2)
+#define DDRPHY_Tsm0_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0104B2)
+#define DDRPHY_Tsm0_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0105B2)
+#define DDRPHY_Tsm0_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0106B2)
+#define DDRPHY_Tsm0_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0107B2)
+#define DDRPHY_Tsm0_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0108B2)
+
+#define DDRPHY_Tsm1_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100B3)
+#define DDRPHY_Tsm1_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0101B3)
+#define DDRPHY_Tsm1_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0102B3)
+#define DDRPHY_Tsm1_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0103B3)
+#define DDRPHY_Tsm1_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0104B3)
+#define DDRPHY_Tsm1_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0105B3)
+#define DDRPHY_Tsm1_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0106B3)
+#define DDRPHY_Tsm1_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0107B3)
+#define DDRPHY_Tsm1_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0108B3)
+
+#define DDRPHY_Tsm2_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100B4)
+#define DDRPHY_Tsm2_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0101B4)
+#define DDRPHY_Tsm2_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0102B4)
+#define DDRPHY_Tsm2_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0103B4)
+#define DDRPHY_Tsm2_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0104B4)
+#define DDRPHY_Tsm2_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0105B4)
+#define DDRPHY_Tsm2_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0106B4)
+#define DDRPHY_Tsm2_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0107B4)
+#define DDRPHY_Tsm2_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0108B4)
+
+#define DDRPHY_Tsm3_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100B5)
+#define DDRPHY_TxChkDataSelects_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100B6)
+#define DDRPHY_DtsmUpThldXingInd_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100B7)
+#define DDRPHY_DtsmLoThldXingInd_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100B8)
+#define DDRPHY_DbyteAllDtsmCtrl0_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100B9)
+#define DDRPHY_DbyteAllDtsmCtrl1_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100BA)
+#define DDRPHY_DbyteAllDtsmCtrl2_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100BB)
+
+#define DDRPHY_TxDqDlyTg0_00(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100C0)
+#define DDRPHY_TxDqDlyTg0_01(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0101C0)
+#define DDRPHY_TxDqDlyTg0_02(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0102C0)
+#define DDRPHY_TxDqDlyTg0_03(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0103C0)
+#define DDRPHY_TxDqDlyTg0_04(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0104C0)
+#define DDRPHY_TxDqDlyTg0_05(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0105C0)
+#define DDRPHY_TxDqDlyTg0_06(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0106C0)
+#define DDRPHY_TxDqDlyTg0_07(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0107C0)
+#define DDRPHY_TxDqDlyTg0_08(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0108C0)
+#define DDRPHY_TxDqDlyTg0_10(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1100C0)
+#define DDRPHY_TxDqDlyTg0_11(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1101C0)
+#define DDRPHY_TxDqDlyTg0_12(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1102C0)
+#define DDRPHY_TxDqDlyTg0_13(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1103C0)
+#define DDRPHY_TxDqDlyTg0_14(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1104C0)
+#define DDRPHY_TxDqDlyTg0_15(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1105C0)
+#define DDRPHY_TxDqDlyTg0_16(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1106C0)
+#define DDRPHY_TxDqDlyTg0_17(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1107C0)
+#define DDRPHY_TxDqDlyTg0_18(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1108C0)
+#define DDRPHY_TxDqDlyTg0_20(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2100C0)
+#define DDRPHY_TxDqDlyTg0_21(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2101C0)
+#define DDRPHY_TxDqDlyTg0_22(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2102C0)
+#define DDRPHY_TxDqDlyTg0_23(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2103C0)
+#define DDRPHY_TxDqDlyTg0_24(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2104C0)
+#define DDRPHY_TxDqDlyTg0_25(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2105C0)
+#define DDRPHY_TxDqDlyTg0_26(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2106C0)
+#define DDRPHY_TxDqDlyTg0_27(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2107C0)
+#define DDRPHY_TxDqDlyTg0_28(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2108C0)
+#define DDRPHY_TxDqDlyTg0_30(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3100C0)
+#define DDRPHY_TxDqDlyTg0_31(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3101C0)
+#define DDRPHY_TxDqDlyTg0_32(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3102C0)
+#define DDRPHY_TxDqDlyTg0_33(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3103C0)
+#define DDRPHY_TxDqDlyTg0_34(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3104C0)
+#define DDRPHY_TxDqDlyTg0_35(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3105C0)
+#define DDRPHY_TxDqDlyTg0_36(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3106C0)
+#define DDRPHY_TxDqDlyTg0_37(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3107C0)
+#define DDRPHY_TxDqDlyTg0_38(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3108C0)
+
+#define DDRPHY_TxDqDlyTg1_00(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100C1)
+#define DDRPHY_TxDqDlyTg1_01(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0101C1)
+#define DDRPHY_TxDqDlyTg1_02(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0102C1)
+#define DDRPHY_TxDqDlyTg1_03(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0103C1)
+#define DDRPHY_TxDqDlyTg1_04(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0104C1)
+#define DDRPHY_TxDqDlyTg1_05(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0105C1)
+#define DDRPHY_TxDqDlyTg1_06(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0106C1)
+#define DDRPHY_TxDqDlyTg1_07(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0107C1)
+#define DDRPHY_TxDqDlyTg1_08(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0108C1)
+#define DDRPHY_TxDqDlyTg1_10(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1100C1)
+#define DDRPHY_TxDqDlyTg1_11(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1101C1)
+#define DDRPHY_TxDqDlyTg1_12(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1102C1)
+#define DDRPHY_TxDqDlyTg1_13(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1103C1)
+#define DDRPHY_TxDqDlyTg1_14(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1104C1)
+#define DDRPHY_TxDqDlyTg1_15(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1105C1)
+#define DDRPHY_TxDqDlyTg1_16(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1106C1)
+#define DDRPHY_TxDqDlyTg1_17(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1107C1)
+#define DDRPHY_TxDqDlyTg1_18(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1108C1)
+#define DDRPHY_TxDqDlyTg1_20(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2100C1)
+#define DDRPHY_TxDqDlyTg1_21(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2101C1)
+#define DDRPHY_TxDqDlyTg1_22(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2102C1)
+#define DDRPHY_TxDqDlyTg1_23(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2103C1)
+#define DDRPHY_TxDqDlyTg1_24(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2104C1)
+#define DDRPHY_TxDqDlyTg1_25(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2105C1)
+#define DDRPHY_TxDqDlyTg1_26(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2106C1)
+#define DDRPHY_TxDqDlyTg1_27(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2107C1)
+#define DDRPHY_TxDqDlyTg1_28(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2108C1)
+#define DDRPHY_TxDqDlyTg1_30(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3100C1)
+#define DDRPHY_TxDqDlyTg1_31(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3101C1)
+#define DDRPHY_TxDqDlyTg1_32(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3102C1)
+#define DDRPHY_TxDqDlyTg1_33(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3103C1)
+#define DDRPHY_TxDqDlyTg1_34(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3104C1)
+#define DDRPHY_TxDqDlyTg1_35(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3105C1)
+#define DDRPHY_TxDqDlyTg1_36(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3106C1)
+#define DDRPHY_TxDqDlyTg1_37(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3107C1)
+#define DDRPHY_TxDqDlyTg1_38(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3108C1)
+
+#define DDRPHY_TxDqDlyTg2_00(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100C2)
+#define DDRPHY_TxDqDlyTg2_01(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0101C2)
+#define DDRPHY_TxDqDlyTg2_02(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0102C2)
+#define DDRPHY_TxDqDlyTg2_03(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0103C2)
+#define DDRPHY_TxDqDlyTg2_04(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0104C2)
+#define DDRPHY_TxDqDlyTg2_05(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0105C2)
+#define DDRPHY_TxDqDlyTg2_06(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0106C2)
+#define DDRPHY_TxDqDlyTg2_07(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0107C2)
+#define DDRPHY_TxDqDlyTg2_08(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0108C2)
+#define DDRPHY_TxDqDlyTg2_10(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1100C2)
+#define DDRPHY_TxDqDlyTg2_11(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1101C2)
+#define DDRPHY_TxDqDlyTg2_12(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1102C2)
+#define DDRPHY_TxDqDlyTg2_13(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1103C2)
+#define DDRPHY_TxDqDlyTg2_14(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1104C2)
+#define DDRPHY_TxDqDlyTg2_15(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1105C2)
+#define DDRPHY_TxDqDlyTg2_16(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1106C2)
+#define DDRPHY_TxDqDlyTg2_17(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1107C2)
+#define DDRPHY_TxDqDlyTg2_18(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1108C2)
+#define DDRPHY_TxDqDlyTg2_20(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2100C2)
+#define DDRPHY_TxDqDlyTg2_21(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2101C2)
+#define DDRPHY_TxDqDlyTg2_22(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2102C2)
+#define DDRPHY_TxDqDlyTg2_23(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2103C2)
+#define DDRPHY_TxDqDlyTg2_24(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2104C2)
+#define DDRPHY_TxDqDlyTg2_25(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2105C2)
+#define DDRPHY_TxDqDlyTg2_26(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2106C2)
+#define DDRPHY_TxDqDlyTg2_27(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2107C2)
+#define DDRPHY_TxDqDlyTg2_28(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2108C2)
+#define DDRPHY_TxDqDlyTg2_30(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3100C2)
+#define DDRPHY_TxDqDlyTg2_31(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3101C2)
+#define DDRPHY_TxDqDlyTg2_32(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3102C2)
+#define DDRPHY_TxDqDlyTg2_33(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3103C2)
+#define DDRPHY_TxDqDlyTg2_34(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3104C2)
+#define DDRPHY_TxDqDlyTg2_35(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3105C2)
+#define DDRPHY_TxDqDlyTg2_36(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3106C2)
+#define DDRPHY_TxDqDlyTg2_37(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3107C2)
+#define DDRPHY_TxDqDlyTg2_38(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3108C2)
+
+#define DDRPHY_TxDqDlyTg3_00(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100C3)
+#define DDRPHY_TxDqDlyTg3_01(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0101C3)
+#define DDRPHY_TxDqDlyTg3_02(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0102C3)
+#define DDRPHY_TxDqDlyTg3_03(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0103C3)
+#define DDRPHY_TxDqDlyTg3_04(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0104C3)
+#define DDRPHY_TxDqDlyTg3_05(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0105C3)
+#define DDRPHY_TxDqDlyTg3_06(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0106C3)
+#define DDRPHY_TxDqDlyTg3_07(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0107C3)
+#define DDRPHY_TxDqDlyTg3_08(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0108C3)
+#define DDRPHY_TxDqDlyTg3_10(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1100C3)
+#define DDRPHY_TxDqDlyTg3_11(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1101C3)
+#define DDRPHY_TxDqDlyTg3_12(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1102C3)
+#define DDRPHY_TxDqDlyTg3_13(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1103C3)
+#define DDRPHY_TxDqDlyTg3_14(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1104C3)
+#define DDRPHY_TxDqDlyTg3_15(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1105C3)
+#define DDRPHY_TxDqDlyTg3_16(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1106C3)
+#define DDRPHY_TxDqDlyTg3_17(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1107C3)
+#define DDRPHY_TxDqDlyTg3_18(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1108C3)
+#define DDRPHY_TxDqDlyTg3_20(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2100C3)
+#define DDRPHY_TxDqDlyTg3_21(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2101C3)
+#define DDRPHY_TxDqDlyTg3_22(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2102C3)
+#define DDRPHY_TxDqDlyTg3_23(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2103C3)
+#define DDRPHY_TxDqDlyTg3_24(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2104C3)
+#define DDRPHY_TxDqDlyTg3_25(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2105C3)
+#define DDRPHY_TxDqDlyTg3_26(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2106C3)
+#define DDRPHY_TxDqDlyTg3_27(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2107C3)
+#define DDRPHY_TxDqDlyTg3_28(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2108C3)
+#define DDRPHY_TxDqDlyTg3_30(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3100C3)
+#define DDRPHY_TxDqDlyTg3_31(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3101C3)
+#define DDRPHY_TxDqDlyTg3_32(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3102C3)
+#define DDRPHY_TxDqDlyTg3_33(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3103C3)
+#define DDRPHY_TxDqDlyTg3_34(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3104C3)
+#define DDRPHY_TxDqDlyTg3_35(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3105C3)
+#define DDRPHY_TxDqDlyTg3_36(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3106C3)
+#define DDRPHY_TxDqDlyTg3_37(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3107C3)
+#define DDRPHY_TxDqDlyTg3_38(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3108C3)
+
+#define DDRPHY_TxDqsDlyTg0_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100D0)
+#define DDRPHY_TxDqsDlyTg0_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0101D0)
+#define DDRPHY_TxDqsDlyTg0_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1100D0)
+#define DDRPHY_TxDqsDlyTg0_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1101D0)
+#define DDRPHY_TxDqsDlyTg0_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2100D0)
+#define DDRPHY_TxDqsDlyTg0_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2101D0)
+#define DDRPHY_TxDqsDlyTg0_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3100D0)
+#define DDRPHY_TxDqsDlyTg0_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3101D0)
+
+#define DDRPHY_TxDqsDlyTg1_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100D1)
+#define DDRPHY_TxDqsDlyTg1_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0101D1)
+#define DDRPHY_TxDqsDlyTg1_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1100D1)
+#define DDRPHY_TxDqsDlyTg1_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1101D1)
+#define DDRPHY_TxDqsDlyTg1_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2100D1)
+#define DDRPHY_TxDqsDlyTg1_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2101D1)
+#define DDRPHY_TxDqsDlyTg1_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3100D1)
+#define DDRPHY_TxDqsDlyTg1_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3101D1)
+
+#define DDRPHY_TxDqsDlyTg2_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100D2)
+#define DDRPHY_TxDqsDlyTg2_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0101D2)
+#define DDRPHY_TxDqsDlyTg2_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1100D2)
+#define DDRPHY_TxDqsDlyTg2_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1101D2)
+#define DDRPHY_TxDqsDlyTg2_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2100D2)
+#define DDRPHY_TxDqsDlyTg2_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2101D2)
+#define DDRPHY_TxDqsDlyTg2_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3100D2)
+#define DDRPHY_TxDqsDlyTg2_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3101D2)
+
+#define DDRPHY_TxDqsDlyTg3_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0100D3)
+#define DDRPHY_TxDqsDlyTg3_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0101D3)
+#define DDRPHY_TxDqsDlyTg3_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1100D3)
+#define DDRPHY_TxDqsDlyTg3_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1101D3)
+#define DDRPHY_TxDqsDlyTg3_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2100D3)
+#define DDRPHY_TxDqsDlyTg3_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2101D3)
+#define DDRPHY_TxDqsDlyTg3_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3100D3)
+#define DDRPHY_TxDqsDlyTg3_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3101D3)
+
+#define DDRPHY_DctShadowRegs(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0C0004)
+#define DDRPHY_DctWriteOnlyShadow(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0C0030)
+#define DDRPHY_UctWriteOnly(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0C0032)
+#define DDRPHY_UctWriteProt(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0C0033)
+#define DDRPHY_UctDatWriteOnly(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0C0034)
+#define DDRPHY_UctDatWriteProt(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0C0035)
+#define DDRPHY_UctlErr(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0C0036)
+#define DDRPHY_UcclkHclkEnables(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0C0080)
+#define DDRPHY_CurPstate0b(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0C0081)
+#define DDRPHY_ClrWakeupSticky(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0C0095)
+#define DDRPHY_WakeupMask(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0C0096)
+#define DDRPHY_CUSTPUBREV(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0C00ED)
+#define DDRPHY_PUBREV(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0C00EE)
+
+#define DDRPHY_PreSequenceReg0b0s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090000)
+#define DDRPHY_SequenceReg0b71s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090100)
+#define DDRPHY_PreSequenceReg0b0s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090001)
+
+#define DDRPHY_Seq0BGPR1_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090201)
+#define DDRPHY_Seq0BGPR1_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x190201)
+#define DDRPHY_Seq0BGPR1_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x290201)
+#define DDRPHY_Seq0BGPR1_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x390201)
+
+#define DDRPHY_SequenceReg0b72s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090101)
+#define DDRPHY_PreSequenceReg0b0s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090002)
+
+#define DDRPHY_Seq0BGPR2_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090202)
+#define DDRPHY_Seq0BGPR2_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x190202)
+#define DDRPHY_Seq0BGPR2_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x290202)
+#define DDRPHY_Seq0BGPR2_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x390202)
+
+#define DDRPHY_SequenceReg0b72s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090102)
+#define DDRPHY_PreSequenceReg0b1s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090003)
+
+#define DDRPHY_Seq0BGPR3_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090203)
+#define DDRPHY_Seq0BGPR3_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x190203)
+#define DDRPHY_Seq0BGPR3_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x290203)
+#define DDRPHY_Seq0BGPR3_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x390203)
+
+#define DDRPHY_SequenceReg0b72s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090103)
+#define DDRPHY_PreSequenceReg0b1s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090004)
+
+#define DDRPHY_Seq0BGPR4_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090204)
+#define DDRPHY_Seq0BGPR4_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x190204)
+#define DDRPHY_Seq0BGPR4_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x290204)
+#define DDRPHY_Seq0BGPR4_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x390204)
+
+#define DDRPHY_SequenceReg0b73s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090104)
+#define DDRPHY_PreSequenceReg0b1s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090005)
+
+#define DDRPHY_Seq0BGPR5_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090205)
+#define DDRPHY_Seq0BGPR5_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x190205)
+#define DDRPHY_Seq0BGPR5_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x290205)
+#define DDRPHY_Seq0BGPR5_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x390205)
+
+#define DDRPHY_SequenceReg0b73s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090105)
+#define DDRPHY_PostSequenceReg0b0s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090006)
+
+#define DDRPHY_Seq0BGPR6_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090206)
+#define DDRPHY_Seq0BGPR6_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x190206)
+#define DDRPHY_Seq0BGPR6_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x290206)
+#define DDRPHY_Seq0BGPR6_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x390206)
+
+#define DDRPHY_SequenceReg0b73s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090106)
+#define DDRPHY_PostSequenceReg0b0s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090007)
+
+#define DDRPHY_Seq0BGPR7_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090207)
+#define DDRPHY_Seq0BGPR7_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x190207)
+#define DDRPHY_Seq0BGPR7_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x290207)
+#define DDRPHY_Seq0BGPR7_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x390207)
+
+#define DDRPHY_SequenceReg0b74s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090107)
+#define DDRPHY_PostSequenceReg0b0s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090008)
+
+#define DDRPHY_Seq0BGPR8_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090208)
+#define DDRPHY_Seq0BGPR8_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x190208)
+#define DDRPHY_Seq0BGPR8_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x290208)
+#define DDRPHY_Seq0BGPR8_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x390208)
+
+#define DDRPHY_SequenceReg0b74s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090108)
+#define DDRPHY_PostSequenceReg0b1s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090009)
+#define DDRPHY_SequenceReg0b74s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090109)
+#define DDRPHY_PostSequenceReg0b1s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09000A)
+#define DDRPHY_SequenceReg0b75s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09010A)
+#define DDRPHY_PostSequenceReg0b1s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09000B)
+#define DDRPHY_SequenceReg0b75s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09010B)
+
+#define DDRPHY_Seq0BDisableFlag0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09000C)
+#define DDRPHY_SequenceReg0b75s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09010C)
+#define DDRPHY_Seq0BDisableFlag1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09000D)
+#define DDRPHY_SequenceReg0b76s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09010D)
+#define DDRPHY_Seq0BDisableFlag2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09000E)
+#define DDRPHY_SequenceReg0b76s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09010E)
+#define DDRPHY_Seq0BDisableFlag3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09000F)
+#define DDRPHY_SequenceReg0b76s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09010F)
+#define DDRPHY_Seq0BDisableFlag4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090010)
+#define DDRPHY_SequenceReg0b77s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090110)
+#define DDRPHY_Seq0BDisableFlag5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090011)
+#define DDRPHY_SequenceReg0b77s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090111)
+#define DDRPHY_Seq0BDisableFlag6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090012)
+#define DDRPHY_SequenceReg0b77s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090112)
+#define DDRPHY_Seq0BDisableFlag7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090013)
+#define DDRPHY_SequenceReg0b78s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090113)
+#define DDRPHY_SequenceReg0b78s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090114)
+#define DDRPHY_SequenceReg0b78s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090115)
+#define DDRPHY_SequenceReg0b79s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090116)
+#define DDRPHY_StartVector0b0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090017)
+#define DDRPHY_SequenceReg0b79s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090117)
+#define DDRPHY_StartVector0b1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090018)
+#define DDRPHY_SequenceReg0b79s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090118)
+
+#define DDRPHY_StartVector0b2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090019)
+#define DDRPHY_SequenceReg0b80s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090119)
+#define DDRPHY_StartVector0b3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09001A)
+#define DDRPHY_SequenceReg0b80s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09011A)
+#define DDRPHY_StartVector0b4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09001B)
+#define DDRPHY_SequenceReg0b80s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09011B)
+#define DDRPHY_StartVector0b5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09001C)
+#define DDRPHY_SequenceReg0b81s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09011C)
+#define DDRPHY_StartVector0b6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09001D)
+#define DDRPHY_SequenceReg0b81s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09011D)
+#define DDRPHY_StartVector0b7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09001E)
+#define DDRPHY_SequenceReg0b81s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09011E)
+#define DDRPHY_StartVector0b8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09001F)
+#define DDRPHY_SequenceReg0b82s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09011F)
+#define DDRPHY_StartVector0b9(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090020)
+#define DDRPHY_SequenceReg0b82s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090120)
+#define DDRPHY_StartVector0b10(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090021)
+#define DDRPHY_SequenceReg0b82s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090121)
+#define DDRPHY_StartVector0b11(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090022)
+#define DDRPHY_SequenceReg0b83s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090122)
+#define DDRPHY_StartVector0b12(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090023)
+#define DDRPHY_SequenceReg0b83s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090123)
+#define DDRPHY_StartVector0b13(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090024)
+#define DDRPHY_SequenceReg0b83s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090124)
+#define DDRPHY_StartVector0b14(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090025)
+#define DDRPHY_SequenceReg0b84s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090125)
+#define DDRPHY_StartVector0b15(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090026)
+#define DDRPHY_SequenceReg0b84s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090126)
+
+#define DDRPHY_Seq0bWaitCondSel(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090027)
+#define DDRPHY_SequenceReg0b84s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090127)
+#define DDRPHY_PhyInLP3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090028)
+
+#define DDRPHY_SequenceReg0b85s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090128)
+#define DDRPHY_SequenceReg0b0s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090029)
+#define DDRPHY_SequenceReg0b85s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090129)
+#define DDRPHY_SequenceReg0b0s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09002a)
+#define DDRPHY_SequenceReg0b85s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09012a)
+#define DDRPHY_SequenceReg0b0s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09002b)
+#define DDRPHY_SequenceReg0b86s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09012b)
+#define DDRPHY_SequenceReg0b1s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09002c)
+#define DDRPHY_SequenceReg0b86s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09012c)
+#define DDRPHY_SequenceReg0b1s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09002d)
+#define DDRPHY_SequenceReg0b86s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09012d)
+#define DDRPHY_SequenceReg0b1s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09002e)
+#define DDRPHY_SequenceReg0b87s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09012e)
+#define DDRPHY_SequenceReg0b2s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09002f)
+#define DDRPHY_SequenceReg0b87s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09012f)
+#define DDRPHY_SequenceReg0b2s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090030)
+#define DDRPHY_SequenceReg0b87s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090130)
+#define DDRPHY_SequenceReg0b2s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090031)
+#define DDRPHY_SequenceReg0b88s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090131)
+#define DDRPHY_SequenceReg0b3s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090032)
+#define DDRPHY_SequenceReg0b88s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090132)
+#define DDRPHY_SequenceReg0b3s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090033)
+#define DDRPHY_SequenceReg0b88s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090133)
+#define DDRPHY_SequenceReg0b3s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090034)
+#define DDRPHY_SequenceReg0b89s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090134)
+#define DDRPHY_SequenceReg0b4s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090035)
+#define DDRPHY_SequenceReg0b89s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090135)
+#define DDRPHY_SequenceReg0b4s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090036)
+#define DDRPHY_SequenceReg0b89s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090136)
+#define DDRPHY_SequenceReg0b4s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090037)
+#define DDRPHY_SequenceReg0b90s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090137)
+#define DDRPHY_SequenceReg0b5s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090038)
+#define DDRPHY_SequenceReg0b90s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090138)
+#define DDRPHY_SequenceReg0b5s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090039)
+#define DDRPHY_SequenceReg0b90s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090139)
+#define DDRPHY_SequenceReg0b5s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09003a)
+#define DDRPHY_SequenceReg0b91s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09013a)
+#define DDRPHY_SequenceReg0b6s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09003b)
+#define DDRPHY_SequenceReg0b91s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09013b)
+#define DDRPHY_SequenceReg0b6s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09003c)
+#define DDRPHY_SequenceReg0b91s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09013c)
+#define DDRPHY_SequenceReg0b6s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09003d)
+#define DDRPHY_SequenceReg0b92s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09013d)
+#define DDRPHY_SequenceReg0b7s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09003e)
+#define DDRPHY_SequenceReg0b92s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09013e)
+#define DDRPHY_SequenceReg0b7s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09003f)
+#define DDRPHY_SequenceReg0b92s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09013f)
+#define DDRPHY_SequenceReg0b7s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090040)
+#define DDRPHY_SequenceReg0b93s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090140)
+#define DDRPHY_SequenceReg0b8s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090041)
+#define DDRPHY_SequenceReg0b93s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090141)
+#define DDRPHY_SequenceReg0b8s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090042)
+#define DDRPHY_SequenceReg0b93s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090142)
+#define DDRPHY_SequenceReg0b8s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090043)
+#define DDRPHY_SequenceReg0b94s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090143)
+#define DDRPHY_SequenceReg0b9s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090044)
+#define DDRPHY_SequenceReg0b94s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090144)
+#define DDRPHY_SequenceReg0b9s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090045)
+#define DDRPHY_SequenceReg0b94s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090145)
+#define DDRPHY_SequenceReg0b9s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090046)
+#define DDRPHY_SequenceReg0b95s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090146)
+#define DDRPHY_SequenceReg0b10s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090047)
+#define DDRPHY_SequenceReg0b95s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090147)
+#define DDRPHY_SequenceReg0b10s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090048)
+#define DDRPHY_SequenceReg0b95s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090148)
+#define DDRPHY_SequenceReg0b10s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090049)
+#define DDRPHY_SequenceReg0b96s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090149)
+#define DDRPHY_SequenceReg0b11s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09004a)
+#define DDRPHY_SequenceReg0b96s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09014a)
+#define DDRPHY_SequenceReg0b11s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09004b)
+#define DDRPHY_SequenceReg0b96s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09014b)
+#define DDRPHY_SequenceReg0b11s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09004c)
+#define DDRPHY_SequenceReg0b97s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09014c)
+#define DDRPHY_SequenceReg0b12s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09004d)
+#define DDRPHY_SequenceReg0b97s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09014d)
+#define DDRPHY_SequenceReg0b12s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09004e)
+#define DDRPHY_SequenceReg0b97s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09014e)
+#define DDRPHY_SequenceReg0b12s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09004f)
+#define DDRPHY_SequenceReg0b98s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09014f)
+#define DDRPHY_SequenceReg0b13s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090050)
+#define DDRPHY_SequenceReg0b98s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090150)
+#define DDRPHY_SequenceReg0b13s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090051)
+#define DDRPHY_SequenceReg0b98s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090151)
+#define DDRPHY_SequenceReg0b13s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090052)
+#define DDRPHY_SequenceReg0b99s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090152)
+#define DDRPHY_SequenceReg0b14s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090053)
+#define DDRPHY_SequenceReg0b99s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090153)
+#define DDRPHY_SequenceReg0b14s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090054)
+#define DDRPHY_SequenceReg0b99s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090154)
+#define DDRPHY_SequenceReg0b14s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090055)
+#define DDRPHY_SequenceReg0b100s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090155)
+#define DDRPHY_SequenceReg0b15s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090056)
+#define DDRPHY_SequenceReg0b100s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090156)
+#define DDRPHY_SequenceReg0b15s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090057)
+#define DDRPHY_SequenceReg0b100s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090157)
+#define DDRPHY_SequenceReg0b15s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090058)
+#define DDRPHY_SequenceReg0b101s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090158)
+#define DDRPHY_SequenceReg0b16s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090059)
+#define DDRPHY_SequenceReg0b101s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090159)
+#define DDRPHY_SequenceReg0b16s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09005a)
+#define DDRPHY_SequenceReg0b101s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09015a)
+#define DDRPHY_SequenceReg0b16s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09005b)
+#define DDRPHY_SequenceReg0b102s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09015b)
+#define DDRPHY_SequenceReg0b17s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09005c)
+#define DDRPHY_SequenceReg0b102s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09015c)
+#define DDRPHY_SequenceReg0b17s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09005d)
+#define DDRPHY_SequenceReg0b102s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09015d)
+#define DDRPHY_SequenceReg0b17s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09005e)
+#define DDRPHY_SequenceReg0b103s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09015e)
+#define DDRPHY_SequenceReg0b18s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09005f)
+#define DDRPHY_SequenceReg0b103s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09015f)
+#define DDRPHY_SequenceReg0b18s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090060)
+#define DDRPHY_SequenceReg0b103s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090160)
+#define DDRPHY_SequenceReg0b18s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090061)
+#define DDRPHY_SequenceReg0b104s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090161)
+#define DDRPHY_SequenceReg0b19s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090062)
+#define DDRPHY_SequenceReg0b104s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090162)
+#define DDRPHY_SequenceReg0b19s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090063)
+#define DDRPHY_SequenceReg0b104s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090163)
+#define DDRPHY_SequenceReg0b19s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090064)
+#define DDRPHY_SequenceReg0b105s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090164)
+#define DDRPHY_SequenceReg0b20s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090065)
+#define DDRPHY_SequenceReg0b105s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090165)
+#define DDRPHY_SequenceReg0b20s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090066)
+#define DDRPHY_SequenceReg0b105s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090166)
+#define DDRPHY_SequenceReg0b20s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090067)
+#define DDRPHY_SequenceReg0b106s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090167)
+#define DDRPHY_SequenceReg0b21s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090068)
+#define DDRPHY_SequenceReg0b106s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090168)
+#define DDRPHY_SequenceReg0b21s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090069)
+#define DDRPHY_SequenceReg0b106s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090169)
+#define DDRPHY_SequenceReg0b21s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09006a)
+#define DDRPHY_SequenceReg0b107s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09016a)
+#define DDRPHY_SequenceReg0b22s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09006b)
+#define DDRPHY_SequenceReg0b107s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09016b)
+#define DDRPHY_SequenceReg0b22s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09006c)
+#define DDRPHY_SequenceReg0b107s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09016c)
+#define DDRPHY_SequenceReg0b22s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09006d)
+#define DDRPHY_SequenceReg0b108s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09016d)
+#define DDRPHY_SequenceReg0b23s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09006e)
+#define DDRPHY_SequenceReg0b108s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09016e)
+#define DDRPHY_SequenceReg0b23s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09006f)
+#define DDRPHY_SequenceReg0b108s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09016f)
+#define DDRPHY_SequenceReg0b23s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090070)
+#define DDRPHY_SequenceReg0b109s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090170)
+#define DDRPHY_SequenceReg0b24s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090071)
+#define DDRPHY_SequenceReg0b109s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090171)
+#define DDRPHY_SequenceReg0b24s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090072)
+#define DDRPHY_SequenceReg0b109s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090172)
+#define DDRPHY_SequenceReg0b24s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090073)
+#define DDRPHY_SequenceReg0b110s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090173)
+#define DDRPHY_SequenceReg0b25s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090074)
+#define DDRPHY_SequenceReg0b110s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090174)
+#define DDRPHY_SequenceReg0b25s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090075)
+#define DDRPHY_SequenceReg0b110s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090175)
+#define DDRPHY_SequenceReg0b25s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090076)
+#define DDRPHY_SequenceReg0b111s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090176)
+#define DDRPHY_SequenceReg0b26s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090077)
+#define DDRPHY_SequenceReg0b111s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090177)
+#define DDRPHY_SequenceReg0b26s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090078)
+#define DDRPHY_SequenceReg0b111s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090178)
+#define DDRPHY_SequenceReg0b26s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090079)
+#define DDRPHY_SequenceReg0b112s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090179)
+#define DDRPHY_SequenceReg0b27s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09007a)
+#define DDRPHY_SequenceReg0b112s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09017a)
+#define DDRPHY_SequenceReg0b27s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09007b)
+#define DDRPHY_SequenceReg0b112s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09017b)
+#define DDRPHY_SequenceReg0b27s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09007c)
+#define DDRPHY_SequenceReg0b113s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09017c)
+#define DDRPHY_SequenceReg0b28s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09007d)
+#define DDRPHY_SequenceReg0b113s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09017d)
+#define DDRPHY_SequenceReg0b28s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09007e)
+#define DDRPHY_SequenceReg0b113s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09017e)
+#define DDRPHY_SequenceReg0b28s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09007f)
+#define DDRPHY_SequenceReg0b114s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09017f)
+#define DDRPHY_SequenceReg0b29s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090080)
+#define DDRPHY_SequenceReg0b114s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090180)
+#define DDRPHY_SequenceReg0b29s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090081)
+#define DDRPHY_SequenceReg0b114s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090181)
+#define DDRPHY_SequenceReg0b29s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090082)
+#define DDRPHY_SequenceReg0b115s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090182)
+#define DDRPHY_SequenceReg0b30s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090083)
+#define DDRPHY_SequenceReg0b115s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090183)
+#define DDRPHY_SequenceReg0b30s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090084)
+#define DDRPHY_SequenceReg0b115s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090184)
+#define DDRPHY_SequenceReg0b30s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090085)
+#define DDRPHY_SequenceReg0b116s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090185)
+#define DDRPHY_SequenceReg0b31s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090086)
+#define DDRPHY_SequenceReg0b116s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090186)
+#define DDRPHY_SequenceReg0b31s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090087)
+#define DDRPHY_SequenceReg0b116s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090187)
+#define DDRPHY_SequenceReg0b31s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090088)
+#define DDRPHY_SequenceReg0b117s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090188)
+#define DDRPHY_SequenceReg0b32s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090089)
+#define DDRPHY_SequenceReg0b117s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090189)
+#define DDRPHY_SequenceReg0b32s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09008a)
+#define DDRPHY_SequenceReg0b117s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09018a)
+#define DDRPHY_SequenceReg0b32s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09008b)
+#define DDRPHY_SequenceReg0b118s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09018b)
+#define DDRPHY_SequenceReg0b33s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09008c)
+#define DDRPHY_SequenceReg0b118s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09018c)
+#define DDRPHY_SequenceReg0b33s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09008d)
+#define DDRPHY_SequenceReg0b118s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09018d)
+#define DDRPHY_SequenceReg0b33s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09008e)
+#define DDRPHY_SequenceReg0b119s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09018e)
+#define DDRPHY_SequenceReg0b34s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09008f)
+#define DDRPHY_SequenceReg0b119s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09018f)
+#define DDRPHY_SequenceReg0b34s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090090)
+#define DDRPHY_SequenceReg0b119s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090190)
+#define DDRPHY_SequenceReg0b34s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090091)
+#define DDRPHY_SequenceReg0b120s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090191)
+#define DDRPHY_SequenceReg0b35s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090092)
+#define DDRPHY_SequenceReg0b120s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090192)
+#define DDRPHY_SequenceReg0b35s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090093)
+#define DDRPHY_SequenceReg0b120s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090193)
+#define DDRPHY_SequenceReg0b35s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090094)
+#define DDRPHY_SequenceReg0b121s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090194)
+#define DDRPHY_SequenceReg0b36s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090095)
+#define DDRPHY_SequenceReg0b121s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090195)
+#define DDRPHY_SequenceReg0b36s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090096)
+#define DDRPHY_SequenceReg0b121s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090196)
+#define DDRPHY_SequenceReg0b36s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090097)
+#define DDRPHY_SequenceReg0b37s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090098)
+#define DDRPHY_SequenceReg0b37s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x090099)
+#define DDRPHY_SequenceReg0b37s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09009a)
+#define DDRPHY_SequenceReg0b38s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09009b)
+#define DDRPHY_SequenceReg0b38s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09009c)
+#define DDRPHY_SequenceReg0b38s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09009d)
+#define DDRPHY_SequenceReg0b39s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09009e)
+#define DDRPHY_SequenceReg0b39s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x09009f)
+#define DDRPHY_SequenceReg0b39s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900a0)
+#define DDRPHY_SequenceReg0b40s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900a1)
+#define DDRPHY_SequenceReg0b40s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900a2)
+#define DDRPHY_SequenceReg0b40s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900a3)
+#define DDRPHY_SequenceReg0b41s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900a4)
+#define DDRPHY_SequenceReg0b41s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900a5)
+#define DDRPHY_SequenceReg0b41s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900a6)
+#define DDRPHY_SequenceReg0b42s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900a7)
+#define DDRPHY_SequenceReg0b42s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900a8)
+#define DDRPHY_SequenceReg0b42s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900a9)
+#define DDRPHY_SequenceReg0b43s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900aa)
+#define DDRPHY_SequenceReg0b43s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900ab)
+#define DDRPHY_SequenceReg0b43s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900ac)
+#define DDRPHY_SequenceReg0b44s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900ad)
+#define DDRPHY_SequenceReg0b44s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900ae)
+#define DDRPHY_SequenceReg0b44s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900af)
+#define DDRPHY_SequenceReg0b45s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900b0)
+#define DDRPHY_SequenceReg0b45s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900b1)
+#define DDRPHY_SequenceReg0b45s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900b2)
+#define DDRPHY_SequenceReg0b46s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900b3)
+#define DDRPHY_SequenceReg0b46s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900b4)
+#define DDRPHY_SequenceReg0b46s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900b5)
+#define DDRPHY_SequenceReg0b47s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900b6)
+#define DDRPHY_SequenceReg0b47s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900b7)
+#define DDRPHY_SequenceReg0b47s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900b8)
+#define DDRPHY_SequenceReg0b48s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900b9)
+#define DDRPHY_SequenceReg0b48s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900ba)
+#define DDRPHY_SequenceReg0b48s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900bb)
+#define DDRPHY_SequenceReg0b49s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900bc)
+#define DDRPHY_SequenceReg0b49s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900bd)
+#define DDRPHY_SequenceReg0b49s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900be)
+#define DDRPHY_SequenceReg0b50s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900bf)
+#define DDRPHY_SequenceReg0b50s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900c0)
+#define DDRPHY_SequenceReg0b50s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900c1)
+#define DDRPHY_SequenceReg0b51s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900c2)
+#define DDRPHY_SequenceReg0b51s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900c3)
+#define DDRPHY_SequenceReg0b51s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900c4)
+#define DDRPHY_SequenceReg0b52s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900c5)
+#define DDRPHY_SequenceReg0b52s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900c6)
+#define DDRPHY_SequenceReg0b52s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900c7)
+#define DDRPHY_SequenceReg0b53s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900c8)
+#define DDRPHY_SequenceReg0b53s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900c9)
+#define DDRPHY_SequenceReg0b53s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900ca)
+#define DDRPHY_SequenceReg0b54s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900cb)
+#define DDRPHY_SequenceReg0b54s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900cc)
+#define DDRPHY_SequenceReg0b54s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900cd)
+#define DDRPHY_SequenceReg0b55s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900ce)
+#define DDRPHY_SequenceReg0b55s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900cf)
+#define DDRPHY_SequenceReg0b55s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900d0)
+#define DDRPHY_SequenceReg0b56s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900d1)
+#define DDRPHY_SequenceReg0b56s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900d2)
+#define DDRPHY_SequenceReg0b56s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900d3)
+#define DDRPHY_SequenceReg0b57s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900d4)
+#define DDRPHY_SequenceReg0b57s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900d5)
+#define DDRPHY_SequenceReg0b57s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900d6)
+#define DDRPHY_SequenceReg0b58s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900d7)
+#define DDRPHY_SequenceReg0b58s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900d8)
+#define DDRPHY_SequenceReg0b58s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900d9)
+#define DDRPHY_SequenceReg0b59s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900da)
+#define DDRPHY_SequenceReg0b59s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900db)
+#define DDRPHY_SequenceReg0b59s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900dc)
+#define DDRPHY_SequenceReg0b60s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900dd)
+#define DDRPHY_SequenceReg0b60s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900de)
+#define DDRPHY_SequenceReg0b60s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900df)
+#define DDRPHY_SequenceReg0b61s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900e0)
+#define DDRPHY_SequenceReg0b61s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900e1)
+#define DDRPHY_SequenceReg0b61s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900e2)
+#define DDRPHY_SequenceReg0b62s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900e3)
+#define DDRPHY_SequenceReg0b62s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900e4)
+#define DDRPHY_SequenceReg0b62s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900e5)
+#define DDRPHY_SequenceReg0b63s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900e6)
+#define DDRPHY_SequenceReg0b63s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900e7)
+#define DDRPHY_SequenceReg0b63s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900e8)
+#define DDRPHY_SequenceReg0b64s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900e9)
+#define DDRPHY_SequenceReg0b64s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900ea)
+#define DDRPHY_SequenceReg0b64s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900eb)
+#define DDRPHY_SequenceReg0b65s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900ec)
+#define DDRPHY_SequenceReg0b65s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900ed)
+#define DDRPHY_SequenceReg0b65s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900ee)
+#define DDRPHY_SequenceReg0b66s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900ef)
+#define DDRPHY_SequenceReg0b66s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900f0)
+#define DDRPHY_SequenceReg0b66s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900f1)
+#define DDRPHY_SequenceReg0b67s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900f2)
+#define DDRPHY_SequenceReg0b67s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900f3)
+#define DDRPHY_SequenceReg0b67s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900f4)
+#define DDRPHY_SequenceReg0b68s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900f5)
+#define DDRPHY_SequenceReg0b68s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900f6)
+#define DDRPHY_SequenceReg0b68s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900f7)
+#define DDRPHY_SequenceReg0b69s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900f8)
+#define DDRPHY_SequenceReg0b69s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900f9)
+#define DDRPHY_SequenceReg0b69s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900fa)
+#define DDRPHY_SequenceReg0b70s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900fb)
+#define DDRPHY_SequenceReg0b70s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900fc)
+#define DDRPHY_SequenceReg0b70s2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900fd)
+#define DDRPHY_SequenceReg0b71s0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900fe)
+#define DDRPHY_SequenceReg0b71s1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0900ff)
+
+#define DDRPHY_RxFifoInit(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020000)
+#define DDRPHY_MapCAA0toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020100)
+#define DDRPHY_ForceClkDisable(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020001)
+#define DDRPHY_MapCAA1toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020101)
+#define DDRPHY_ClockingCtrl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020002)
+#define DDRPHY_MapCAA2toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020102)
+#define DDRPHY_MapCAA3toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020103)
+#define DDRPHY_MapCAA4toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020104)
+#define DDRPHY_MapCAA5toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020105)
+#define DDRPHY_MapCAA6toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020106)
+#define DDRPHY_TestBumpCntrl1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020007)
+#define DDRPHY_MapCAA7toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020107)
+
+#define DDRPHY_CalUclkInfo_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020008)
+#define DDRPHY_CalUclkInfo_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x120008)
+#define DDRPHY_CalUclkInfo_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x220008)
+#define DDRPHY_CalUclkInfo_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x320008)
+
+#define DDRPHY_MapCAA8toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020108)
+#define DDRPHY_MapCAA9toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020109)
+#define DDRPHY_TestBumpCntrl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02000A)
+
+#define DDRPHY_Seq0BDLY0_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02000B)
+#define DDRPHY_Seq0BDLY0_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x12000B)
+#define DDRPHY_Seq0BDLY0_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x22000B)
+#define DDRPHY_Seq0BDLY0_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x32000B)
+
+#define DDRPHY_Seq0BDLY1_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02000C)
+#define DDRPHY_Seq0BDLY1_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x12000C)
+#define DDRPHY_Seq0BDLY1_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x22000C)
+#define DDRPHY_Seq0BDLY1_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x32000C)
+
+#define DDRPHY_Seq0BDLY2_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02000D)
+#define DDRPHY_Seq0BDLY2_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x12000D)
+#define DDRPHY_Seq0BDLY2_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x22000D)
+#define DDRPHY_Seq0BDLY2_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x32000D)
+
+#define DDRPHY_Seq0BDLY3_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02000E)
+#define DDRPHY_Seq0BDLY3_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x12000E)
+#define DDRPHY_Seq0BDLY3_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x22000E)
+#define DDRPHY_Seq0BDLY3_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x32000E)
+
+#define DDRPHY_PhyAlertStatus(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02000F)
+
+#define DDRPHY_PPTTrainSetup_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020010)
+#define DDRPHY_PPTTrainSetup_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x120010)
+#define DDRPHY_PPTTrainSetup_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x220010)
+#define DDRPHY_PPTTrainSetup_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x320010)
+
+#define DDRPHY_MapCAB0toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020110)
+
+#define DDRPHY_PPTTrainSetup2_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020011)
+#define DDRPHY_PPTTrainSetup2_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x120011)
+#define DDRPHY_PPTTrainSetup2_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x220011)
+#define DDRPHY_PPTTrainSetup2_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x320011)
+
+#define DDRPHY_MapCAB1toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020111)
+#define DDRPHY_ATestMode(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020012)
+#define DDRPHY_MapCAB2toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020112)
+
+#define DDRPHY_MapCAB3toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020113)
+#define DDRPHY_TxCalBinP(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020014)
+#define DDRPHY_MapCAB4toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020114)
+#define DDRPHY_TxCalBinN(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020015)
+#define DDRPHY_MapCAB5toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020115)
+#define DDRPHY_TxCalPOvr(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020016)
+#define DDRPHY_MapCAB6toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020116)
+#define DDRPHY_TxCalNOvr(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020017)
+#define DDRPHY_MapCAB7toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020117)
+#define DDRPHY_DfiMode(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020018)
+#define DDRPHY_MapCAB8toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020118)
+
+#define DDRPHY_TristateModeCA_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020019)
+#define DDRPHY_TristateModeCA_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x120019)
+#define DDRPHY_TristateModeCA_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x220019)
+#define DDRPHY_TristateModeCA_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x320019)
+
+#define DDRPHY_MapCAB9toDfi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020119)
+
+#define DDRPHY_MtestMuxSel(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02001A)
+#define DDRPHY_MtestPgmInfo(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02001B)
+#define DDRPHY_DynPwrDnUp(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02001C)
+#define DDRPHY_PMIEnable(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02001D)
+#define DDRPHY_PhyTID(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02001E)
+
+#define DDRPHY_HwtMRL_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020020)
+#define DDRPHY_HwtMRL_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x120020)
+#define DDRPHY_HwtMRL_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x220020)
+#define DDRPHY_HwtMRL_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x320020)
+
+#define DDRPHY_DFIPHYUPD(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020021)
+#define DDRPHY_PdaMrsWriteMode(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020022)
+#define DDRPHY_DFIGEARDOWNCTL(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020023)
+
+#define DDRPHY_DqsPreambleControl_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020024)
+#define DDRPHY_DqsPreambleControl_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x120024)
+#define DDRPHY_DqsPreambleControl_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x220024)
+#define DDRPHY_DqsPreambleControl_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x320024)
+
+#define DDRPHY_MasterX4Config(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020025)
+#define DDRPHY_WrLevBits(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020026)
+#define DDRPHY_EnableCsMulticast(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020027)
+#define DDRPHY_Acx4AnibDis(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02002c)
+
+#define DDRPHY_ImgDramMR3_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02002D)
+#define DDRPHY_ImgDramMR3_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x12002D)
+#define DDRPHY_ImgDramMR3_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x22002D)
+#define DDRPHY_ImgDramMR3_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x32002D)
+
+#define DDRPHY_ARdPtrInitVal_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02002E)
+#define DDRPHY_ARdPtrInitVal_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x12002E)
+#define DDRPHY_ARdPtrInitVal_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x22002E)
+#define DDRPHY_ARdPtrInitVal_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x32002E)
+
+#define DDRPHY_Db0LcdlCalPhDetOut(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020030)
+
+#define DDRPHY_Db1LcdlCalPhDetOut(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020031)
+#define DDRPHY_Db2LcdlCalPhDetOut(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020032)
+#define DDRPHY_Db3LcdlCalPhDetOut(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020033)
+#define DDRPHY_Db4LcdlCalPhDetOut(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020034)
+#define DDRPHY_Db5LcdlCalPhDetOut(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020035)
+#define DDRPHY_Db6LcdlCalPhDetOut(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020036)
+#define DDRPHY_Db7LcdlCalPhDetOut(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020037)
+#define DDRPHY_Db8LcdlCalPhDetOut(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020038)
+#define DDRPHY_Db9LcdlCalPhDetOut(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020039)
+#define DDRPHY_DbyteDllModeCntrl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02003A)
+#define DDRPHY_DbyteRxEnTrain(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02003B)
+#define DDRPHY_AnLcdlCalPhDetOut(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02003F)
+#define DDRPHY_CalOffsets(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020045)
+#define DDRPHY_SarInitVals(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020047)
+#define DDRPHY_CalPExtOvr(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020049)
+#define DDRPHY_CalCmpr5Ovr(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02004A)
+#define DDRPHY_CalNIntOvr(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02004B)
+#define DDRPHY_CalDrvStr0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020050)
+
+#define DDRPHY_ProcOdtCtl_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020055)
+#define DDRPHY_ProcOdtCtl_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x120055)
+#define DDRPHY_ProcOdtCtl_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x220055)
+#define DDRPHY_ProcOdtCtl_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x320055)
+
+#define DDRPHY_ProcOdtTimeCtl_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020056)
+#define DDRPHY_ProcOdtTimeCtl_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x120056)
+#define DDRPHY_ProcOdtTimeCtl_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x220056)
+#define DDRPHY_ProcOdtTimeCtl_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x320056)
+
+#define DDRPHY_MemAlertControl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02005B)
+#define DDRPHY_MemAlertControl2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02005C)
+#define DDRPHY_MemResetL(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020060)
+#define DDRPHY_PUBMODE(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02006E)
+#define DDRPHY_MiscPhyStatus(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02006F)
+#define DDRPHY_CoreLoopbackSel(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020070)
+#define DDRPHY_DllTrainParam(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020071)
+#define DDRPHY_LpCsEnA(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020072)
+#define DDRPHY_LpCsEnB(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020073)
+#define DDRPHY_LpCsEnBypass(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020074)
+#define DDRPHY_DfiCAMode(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020075)
+#define DDRPHY_HwtCACtl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020076)
+#define DDRPHY_HwtCAMode(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020077)
+#define DDRPHY_DllControl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020078)
+#define DDRPHY_PulseDllUpdatePhase(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020079)
+#define DDRPHY_HwtControlOvr0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02007A)
+#define DDRPHY_HwtControlOvr1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02007B)
+
+#define DDRPHY_DllGainCtl_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02007C)
+#define DDRPHY_DllGainCtl_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x12007C)
+#define DDRPHY_DllGainCtl_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x22007C)
+#define DDRPHY_DllGainCtl_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x32007C)
+
+#define DDRPHY_DllLockParam(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02007D)
+#define DDRPHY_HwtControlVal0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02007E)
+#define DDRPHY_HwtControlVal1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02007F)
+#define DDRPHY_AcsmGlblStart(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020081)
+#define DDRPHY_AcsmGlblSglStpCtrl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020082)
+#define DDRPHY_LcdlCalPhase(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020084)
+#define DDRPHY_LcdlCalCtrl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020085)
+#define DDRPHY_CalRate(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020088)
+#define DDRPHY_CalZap(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020089)
+#define DDRPHY_PState(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02008B)
+#define DDRPHY_CalPreDriverOverride(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02008C)
+#define DDRPHY_PllOutGateControl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02008D)
+#define DDRPHY_UcMemResetControl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02008F)
+
+#define DDRPHY_PorControl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020090)
+#define DDRPHY_CalBusy(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020097)
+#define DDRPHY_CalMisc2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x020098)
+#define DDRPHY_CalMisc(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02009A)
+#define DDRPHY_CalCmpr5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02009C)
+#define DDRPHY_CalNInt(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02009D)
+#define DDRPHY_CalPExt(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x02009E)
+#define DDRPHY_CalCmpInvert(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200A8)
+#define DDRPHY_CalCmpanaCntrl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200AE)
+
+#define DDRPHY_DfiRdDataCsDestMap_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200B0)
+#define DDRPHY_DfiRdDataCsDestMap_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1200B0)
+#define DDRPHY_DfiRdDataCsDestMap_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2200B0)
+#define DDRPHY_DfiRdDataCsDestMap_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3200B0)
+
+#define DDRPHY_VrefInGlobal_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200B2)
+#define DDRPHY_VrefInGlobal_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1200B2)
+#define DDRPHY_VrefInGlobal_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2200B2)
+#define DDRPHY_VrefInGlobal_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3200B2)
+
+#define DDRPHY_DfiWrDataCsDestMap_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200B4)
+#define DDRPHY_DfiWrDataCsDestMap_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1200B4)
+#define DDRPHY_DfiWrDataCsDestMap_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2200B4)
+#define DDRPHY_DfiWrDataCsDestMap_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3200B4)
+
+#define DDRPHY_PhyMasUpdGoodCtr(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200B5)
+#define DDRPHY_PhyCtlUpdGoodCtr(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200B6)
+#define DDRPHY_DctPhyUpdGoodCtr(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200B7)
+#define DDRPHY_PhyMasUpdFailCtr(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200B8)
+#define DDRPHY_PhyCtlUpdFailCtr(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200B9)
+#define DDRPHY_PhyCtlUpd1FailCtr(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200BA)
+#define DDRPHY_PhyPerfCtrEnable(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200BB)
+#define DDRPHY_PllPwrDn(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200C3)
+#define DDRPHY_PllReset(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200C4)
+#define DDRPHY_PllCtrl2_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200C5)
+#define DDRPHY_PllCtrl2_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1200C5)
+#define DDRPHY_PllCtrl2_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2200C5)
+#define DDRPHY_PllCtrl2_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3200C5)
+#define DDRPHY_PllCtrl0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200C6)
+#define DDRPHY_PllCtrl1_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200C7)
+#define DDRPHY_PllCtrl1_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1200C7)
+#define DDRPHY_PllCtrl1_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2200C7)
+#define DDRPHY_PllCtrl1_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3200C7)
+#define DDRPHY_PllTst(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200C8)
+#define DDRPHY_PllLockStatus(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200C9)
+#define DDRPHY_PllTestMode_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200CA)
+#define DDRPHY_PllTestMode_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1200CA)
+#define DDRPHY_PllTestMode_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2200CA)
+#define DDRPHY_PllTestMode_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3200CA)
+#define DDRPHY_PllCtrl3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200CB)
+#define DDRPHY_PllCtrl4_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200CC)
+#define DDRPHY_PllCtrl4_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1200CC)
+#define DDRPHY_PllCtrl4_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2200CC)
+#define DDRPHY_PllCtrl4_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3200CC)
+#define DDRPHY_PllEndofCal(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200CD)
+#define DDRPHY_PllStandbyEff(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200CE)
+#define DDRPHY_PllDacValOut(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200CF)
+#define DDRPHY_DlyTestSeq(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200D0)
+#define DDRPHY_DlyTestRingSelDb(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200D1)
+#define DDRPHY_DlyTestRingSelAc(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200D2)
+#define DDRPHY_DlyTestCntDfiClkIV(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200D3)
+#define DDRPHY_DlyTestCntDfiClk(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200D4)
+#define DDRPHY_DlyTestCntRingOscDb0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200D5)
+#define DDRPHY_DlyTestCntRingOscDb1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200D6)
+#define DDRPHY_DlyTestCntRingOscDb2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200D7)
+#define DDRPHY_DlyTestCntRingOscDb3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200D8)
+#define DDRPHY_DlyTestCntRingOscDb4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200D9)
+#define DDRPHY_DlyTestCntRingOscDb5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200DA)
+#define DDRPHY_DlyTestCntRingOscDb6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200DB)
+#define DDRPHY_DlyTestCntRingOscDb7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200DC)
+#define DDRPHY_DlyTestCntRingOscDb8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200DD)
+#define DDRPHY_DlyTestCntRingOscDb9(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200DE)
+#define DDRPHY_DlyTestCntRingOscAc(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200DF)
+#define DDRPHY_MstLcdlDbgCntl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200E0)
+#define DDRPHY_MstLcdl0DbgRes(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200E1)
+#define DDRPHY_MstLcdl1DbgRes(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200E2)
+#define DDRPHY_CUSTPHYREV(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200ED)
+#define DDRPHY_PHYREV(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200EE)
+#define DDRPHY_LP3ExitSeq0BStartVector(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200EF)
+#define DDRPHY_DfiFreqXlat0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200F0)
+#define DDRPHY_DfiFreqXlat1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200F1)
+#define DDRPHY_DfiFreqXlat2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200F2)
+#define DDRPHY_DfiFreqXlat3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200F3)
+#define DDRPHY_DfiFreqXlat4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200F4)
+#define DDRPHY_DfiFreqXlat5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200F5)
+#define DDRPHY_DfiFreqXlat6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200F6)
+#define DDRPHY_DfiFreqXlat7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200F7)
+#define DDRPHY_TxRdPtrInit(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200F8)
+#define DDRPHY_DfiInitComplete(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200F9)
+
+#define DDRPHY_DfiFreqRatio_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x0200FA)
+#define DDRPHY_DfiFreqRatio_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x1200FA)
+#define DDRPHY_DfiFreqRatio_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x2200FA)
+#define DDRPHY_DfiFreqRatio_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x3200FA)
+
+#define DDRPHY_PPGCCtrl1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070011)
+#define DDRPHY_PpgcLane2CrcInMap0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070015)
+#define DDRPHY_PpgcLane2CrcInMap1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070016)
+
+#define DDRPHY_PrbsTapDly0_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070024)
+#define DDRPHY_PrbsTapDly0_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070124)
+#define DDRPHY_PrbsTapDly0_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070224)
+#define DDRPHY_PrbsTapDly0_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070324)
+#define DDRPHY_PrbsTapDly0_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070424)
+#define DDRPHY_PrbsTapDly0_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070524)
+#define DDRPHY_PrbsTapDly0_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070624)
+#define DDRPHY_PrbsTapDly0_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070724)
+#define DDRPHY_PrbsTapDly0_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070824)
+
+#define DDRPHY_PrbsTapDly1_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070025)
+#define DDRPHY_PrbsTapDly1_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070125)
+#define DDRPHY_PrbsTapDly1_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070225)
+#define DDRPHY_PrbsTapDly1_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070325)
+#define DDRPHY_PrbsTapDly1_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070425)
+#define DDRPHY_PrbsTapDly1_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070525)
+#define DDRPHY_PrbsTapDly1_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070625)
+#define DDRPHY_PrbsTapDly1_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070725)
+#define DDRPHY_PrbsTapDly1_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070825)
+
+#define DDRPHY_PrbsTapDly2_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070026)
+#define DDRPHY_PrbsTapDly2_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070126)
+#define DDRPHY_PrbsTapDly2_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070226)
+#define DDRPHY_PrbsTapDly2_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070326)
+#define DDRPHY_PrbsTapDly2_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070426)
+#define DDRPHY_PrbsTapDly2_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070526)
+#define DDRPHY_PrbsTapDly2_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070626)
+#define DDRPHY_PrbsTapDly2_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070726)
+#define DDRPHY_PrbsTapDly2_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070826)
+
+#define DDRPHY_PrbsTapDly3_0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070027)
+#define DDRPHY_PrbsTapDly3_1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070127)
+#define DDRPHY_PrbsTapDly3_2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070227)
+#define DDRPHY_PrbsTapDly3_3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070327)
+#define DDRPHY_PrbsTapDly3_4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070427)
+#define DDRPHY_PrbsTapDly3_5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070527)
+#define DDRPHY_PrbsTapDly3_6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070627)
+#define DDRPHY_PrbsTapDly3_7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070727)
+#define DDRPHY_PrbsTapDly3_8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070827)
+
+#define DDRPHY_GenPrbsByte0(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070030)
+#define DDRPHY_GenPrbsByte1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070031)
+#define DDRPHY_GenPrbsByte2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070032)
+#define DDRPHY_GenPrbsByte3(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070033)
+#define DDRPHY_GenPrbsByte4(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070034)
+#define DDRPHY_GenPrbsByte5(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070035)
+#define DDRPHY_GenPrbsByte6(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070036)
+#define DDRPHY_GenPrbsByte7(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070037)
+#define DDRPHY_GenPrbsByte8(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070038)
+#define DDRPHY_GenPrbsByte9(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070039)
+#define DDRPHY_GenPrbsByte10(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x07003A)
+#define DDRPHY_GenPrbsByte11(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x07003B)
+#define DDRPHY_GenPrbsByte12(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x07003C)
+#define DDRPHY_GenPrbsByte13(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x07003D)
+#define DDRPHY_GenPrbsByte14(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x07003E)
+#define DDRPHY_GenPrbsByte15(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x07003F)
+#define DDRPHY_PrbsGenCtl(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070060)
+#define DDRPHY_PrbsGenStateLo(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070061)
+#define DDRPHY_PrbsGenStateHi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070062)
+#define DDRPHY_PrbsChkStateLo(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070063)
+#define DDRPHY_PrbsChkStateHi(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070064)
+#define DDRPHY_PrbsGenCtl1(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070065)
+#define DDRPHY_PrbsGenCtl2(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4*0x070066)
+
+
+#define DRC_PERF_MON_BASE_ADDR(X) (0x3d800000 + (X * 0x2000000))
+#define DRC_PERF_MON_CNT0_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x0)
+#define DRC_PERF_MON_CNT1_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4)
+#define DRC_PERF_MON_CNT2_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x8)
+#define DRC_PERF_MON_CNT3_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0xC)
+#define DRC_PERF_MON_CNT0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x20)
+#define DRC_PERF_MON_CNT1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x24)
+#define DRC_PERF_MON_CNT2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x28)
+#define DRC_PERF_MON_CNT3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x2C)
+#define DRC_PERF_MON_MRR0_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x40)
+#define DRC_PERF_MON_MRR1_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x44)
+#define DRC_PERF_MON_MRR2_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x48)
+#define DRC_PERF_MON_MRR3_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x4C)
+#define DRC_PERF_MON_MRR4_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x50)
+#define DRC_PERF_MON_MRR5_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x54)
+#define DRC_PERF_MON_MRR6_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x58)
+#define DRC_PERF_MON_MRR7_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x5C)
+#define DRC_PERF_MON_MRR8_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x60)
+#define DRC_PERF_MON_MRR9_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x64)
+#define DRC_PERF_MON_MRR10_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x68)
+#define DRC_PERF_MON_MRR11_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x6C)
+#define DRC_PERF_MON_MRR12_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x70)
+#define DRC_PERF_MON_MRR13_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x74)
+#define DRC_PERF_MON_MRR14_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x78)
+#define DRC_PERF_MON_MRR15_DAT(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x7C)
+#endif
diff --git a/board/boundary/nitrogen8m/ddr/ddrphy_train.c b/board/boundary/nitrogen8m/ddr/ddrphy_train.c
new file mode 100644
index 0000000000000000000000000000000000000000..0c61fe3767e5a838d5ef35e8e743abe685a0b6a4
--- /dev/null
+++ b/board/boundary/nitrogen8m/ddr/ddrphy_train.c
@@ -0,0 +1,1146 @@
+/*
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include "ddr_memory_map.h"
+#include "ddr.h"
+#include "lpddr4_dvfs.h"
+
+extern void wait_ddrphy_training_complete(void);
+
+void sscgpll_bypass_enable(unsigned int reg_addr)
+{
+ unsigned int read_data;
+ read_data = reg32_read(reg_addr);
+ reg32_write(reg_addr, read_data | 0x00000010);
+ read_data = reg32_read(reg_addr);
+ reg32_write(reg_addr, read_data | 0x00000020);
+}
+
+void sscgpll_bypass_disable(unsigned int reg_addr)
+{
+ unsigned int read_data;
+ read_data = reg32_read(reg_addr);
+ reg32_write(reg_addr, read_data & 0xffffffdf);
+ read_data = reg32_read(reg_addr);
+ reg32_write(reg_addr, read_data & 0xffffffef);
+}
+
+unsigned int wait_pll_lock(unsigned int reg_addr)
+{
+ unsigned int pll_lock;
+ pll_lock = reg32_read(reg_addr) >> 31;
+ return pll_lock;
+}
+
+void ddr_pll_config_freq(unsigned int freq)
+{
+ unsigned int ddr_pll_lock = 0x0;
+ sscgpll_bypass_enable(HW_DRAM_PLL_CFG0_ADDR);
+ switch (freq) {
+ case 800:
+ reg32_write(HW_DRAM_PLL_CFG2_ADDR, 0x00ece580);
+ break;
+ case 700:
+ reg32_write(HW_DRAM_PLL_CFG2_ADDR, 0x00ec4580);
+ break;
+ case 667:
+ reg32_write(HW_DRAM_PLL_CFG2_ADDR, 0x00ece480);
+ break;
+ case 400:
+ reg32_write(HW_DRAM_PLL_CFG2_ADDR, 0x00ec6984);
+ break;
+ case 167:
+ reg32_write(HW_DRAM_PLL_CFG2_ADDR, 0x00f5a406);
+ break;
+ case 100:
+ reg32_write(HW_DRAM_PLL_CFG2_ADDR, 0x015dea96);
+ break;
+ default:
+ printf("Input freq=%d error.\n",freq);
+ }
+
+ sscgpll_bypass_disable(HW_DRAM_PLL_CFG0_ADDR);
+ while (ddr_pll_lock != 0x1) {
+ ddr_pll_lock = wait_pll_lock(HW_DRAM_PLL_CFG0_ADDR);
+ }
+}
+
+void dwc_ddrphy_phyinit_userCustom_E_setDfiClk(int pstate)
+{
+ struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
+
+ if (pstate == 0x1) {
+ reg32_writep(&ccm_reg->bus_root[1].target_root_clr, (0x7<<24)|(0x7<<16));
+ reg32_writep(&ccm_reg->bus_root[1].target_root_set, (0x4<<24)|(0x4<<16)); /* to source 4 --800MHz/5 */
+ ddr_pll_config_freq(167);
+ } else {
+ ddr_pll_config_freq(800);
+ reg32_writep(&ccm_reg->bus_root[1].target_root_clr, (0x7<<24)|(0x7<<16));
+ reg32_writep(&ccm_reg->bus_root[1].target_root_set, (0x4<<24)|(0x3<<16)); /* to source 4 --800MHz/4 */
+ }
+}
+
+void lpddr4_800M_cfg_phy(void)
+{
+ printf("start to config phy: p0=3200mts, p1=667mts with 1D2D training\n");
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20110, 0x02); /* MapCAB0toDFI */
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20111, 0x03); /* MapCAB1toDFI */
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20112, 0x04); /* MapCAB2toDFI */
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20113, 0x05); /* MapCAB3toDFI */
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20114, 0x00); /* MapCAB4toDFI */
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20115, 0x01); /* MapCAB5toDFI */
+
+ /* Initialize PHY Configuration */
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1005f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1015f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1105f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1115f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1205f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1215f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1305f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1315f, 0x1ff);
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11005f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11015f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11105f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11115f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11205f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11215f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11305f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11315f, 0x1ff);
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21005f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21015f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21105f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21115f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21205f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21215f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21305f, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21315f, 0x1ff);
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x55, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1055, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2055, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x3055, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4055, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5055, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x6055, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x7055, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x8055, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9055, 0x1ff);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200c5, 0x19);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200c5, 0x7);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200c5, 0x7);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2002e, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12002e, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22002e, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90204, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x190204, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x290204, 0x0);
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20024, 0xe3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120024, 0xa3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220024, 0xa3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x2);
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20056, 0x3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120056, 0xa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220056, 0xa);
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1004d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1014d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1104d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1114d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1204d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1214d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1304d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1314d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11004d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11014d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11104d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11114d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11204d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11214d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11304d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11314d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21004d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21014d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21104d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21114d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21204d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21214d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21304d, 0xe00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x21314d, 0xe00);
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10049, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10149, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11049, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11149, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12049, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12149, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13049, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13149, 0xfbe);
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110049, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110149, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111049, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111149, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112049, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112149, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113049, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113149, 0xfbe);
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210049, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210149, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211049, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211149, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212049, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212149, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213049, 0xfbe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213149, 0xfbe);
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x43, 0x63);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1043, 0x63);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2043, 0x63);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x3043, 0x63);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4043, 0x63);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5043, 0x63);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x6043, 0x63);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x7043, 0x63);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x8043, 0x63);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9043, 0x63);
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20018, 0x3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20075, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20050, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20008, 0x320);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120008, 0xa7);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220008, 0x19);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20088, 0x9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200b2, 0x104);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200b2, 0x104);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200b2, 0x104);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x210143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x211143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x212143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213043, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x213143, 0x5a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200fa, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x1200fa, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2200fa, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20019, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120019, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x220019, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f0, 0x600);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f1, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f2, 0x4444);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f3, 0x8888);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f4, 0x5655);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f5, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f6, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x200f7, 0xf000);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20025, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2002d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12002d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22002d, 0x0);
+
+ /* Load the 1D IMEM image */
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ ddr_load_train_code(FW_1D_IMAGE);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+
+ /* Set the PHY input clocks for pstate 0 */
+ dwc_ddrphy_phyinit_userCustom_E_setDfiClk (0);
+ /* Load the 1D DMEM image and write the 1D Message Block parameters for the training firmware */
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ printf("config to do 3200 1d training.\n");
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003, 0xc80);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005, ((LPDDR4_PHY_RON<<8) | LPDDR4_PHY_RTT));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006, LPDDR4_PHY_VREF_VALUE);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008, 0x131f);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009, LPDDR4_HDT_CTL_3200_1D);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012, 0x310);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019, 0x2dd4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a, (((LPDDR4_RON) << 3) | 0x3));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e, LPDDR4_MR22_RANK0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f, 0x2dd4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020, (((LPDDR4_RON) << 3) | 0x3));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024, LPDDR4_MR22_RANK1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b, 0x1000);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c, 0x3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032, 0xd400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035, (0x0800|LPDDR4_VREF_VALUE_CA));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037, (LPDDR4_MR22_RANK0 << 8));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038, 0xd400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, (LPDDR4_MR22_RANK1 << 8));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, (LPDDR4_MR22_RANK1 << 8));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54040, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54041, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54042, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54043, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54044, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
+
+ /* wait for train complete */
+ wait_ddrphy_training_complete();
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+
+ /* Load the 2D IMEM image */
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ ddr_load_train_code(FW_2D_IMAGE);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+
+ /* 3200 mts 2D training */
+ printf("config to do 3200 2d training.\n");
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003, 0xc80);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006, LPDDR4_PHY_VREF_VALUE);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008, 0x61);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009, LPDDR4_HDT_CTL_2D);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010, LPDDR4_2D_WEIGHT);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012, 0x310);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024, 0x5);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019, 0x2dd4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a, (((LPDDR4_RON) << 3) | 0x3));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e, LPDDR4_MR22_RANK0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f, 0x2dd4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020, (((LPDDR4_RON) << 3) | 0x3));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024, LPDDR4_MR22_RANK1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b, 0x1000);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c, 0x3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032, 0xd400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035, (0x0800|LPDDR4_VREF_VALUE_CA));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037, (LPDDR4_MR22_RANK0 << 8));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038, 0xd400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b, (0x0800|LPDDR4_VREF_VALUE_CA));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, (LPDDR4_MR22_RANK1 << 8));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54040, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54041, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54042, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54043, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54044, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
+
+ /* wait for train complete */
+ wait_ddrphy_training_complete();
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+
+ /* Step (E) Set the PHY input clocks for pstate 1 */
+ dwc_ddrphy_phyinit_userCustom_E_setDfiClk (1);
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ ddr_load_train_code(FW_1D_IMAGE);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+
+ printf("pstate=1: set dfi clk done done\n");
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54001, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003, 0x29c);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006, LPDDR4_PHY_VREF_VALUE);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54007, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008, 0x121f);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009, 0xc8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400c, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54011, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012, 0x310);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54013, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54014, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54015, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54016, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54017, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54018, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019, 0x914);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a, (((LPDDR4_RON) << 3) | 0x1));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e, 0x6);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f, 0x914);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020, (((LPDDR4_RON) << 3) | 0x1));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54023, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024, LPDDR4_MR22_RANK1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54025, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54026, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54027, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54028, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54029, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b, 0x1000);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c, 0x3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54030, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54031, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032, 0x1400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035, (0x0800|LPDDR4_VREF_VALUE_CA));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037, 0x600);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038, 0x1400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b, (0x0800|LPDDR4_VREF_VALUE_CA));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d, (LPDDR4_MR22_RANK1 << 8));
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54040, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54041, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54042, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54043, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0);
+
+ /* wait for train complete */
+ wait_ddrphy_training_complete();
+
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+
+ /* (I) Load PHY Init Engine Image */
+ printf("Load 201711 PIE\n");
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90000, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90001, 0x400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90002, 0x10e);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90003, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90004, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90005, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90029, 0xb);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002a, 0x480);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002b, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002c, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002d, 0x448);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002e, 0x139);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9002f, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90030, 0x478);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90031, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90032, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90033, 0xe8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90034, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90035, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90036, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90037, 0x139);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90038, 0xb);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90039, 0x7c0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003a, 0x139);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003b, 0x44);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003c, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003d, 0x159);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003e, 0x14f);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9003f, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90040, 0x159);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90041, 0x47);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90042, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90043, 0x149);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90044, 0x4f);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90045, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90046, 0x179);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90047, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90048, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90049, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004b, 0x7c8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004c, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004e, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9004f, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90050, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90051, 0x45a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90052, 0x9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90053, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90054, 0x448);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90055, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90056, 0x40);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90057, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90058, 0x179);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90059, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005a, 0x618);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005b, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005c, 0x40c0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005d, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005e, 0x149);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9005f, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90060, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90061, 0x48);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90062, 0x4040);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90063, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90064, 0x149);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90065, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90066, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90067, 0x48);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90068, 0x40);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90069, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006a, 0x149);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006b, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006c, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006d, 0x18);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9006f, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90070, 0x78);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90071, 0x549);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90072, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90073, 0x159);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90074, 0xd49);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90075, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90076, 0x159);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90077, 0x94a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90078, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90079, 0x159);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007a, 0x441);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007b, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007c, 0x149);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007d, 0x42);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007e, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9007f, 0x149);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90080, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90081, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90082, 0x149);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90083, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90084, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90085, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90086, 0xa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90087, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90088, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90089, 0x9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008a, 0x3c0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008b, 0x149);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008c, 0x9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008d, 0x3c0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008e, 0x159);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9008f, 0x18);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90090, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90091, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90092, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90093, 0x3c0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90094, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90095, 0x18);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90096, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90097, 0x48);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90098, 0x18);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90099, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009a, 0x58);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009b, 0xa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009c, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009d, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009e, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9009f, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a0, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a1, 0x5);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a2, 0x7c0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a3, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a4, 0xd);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a5, 0x7c0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a6, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a7, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a8, 0x7c0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900a9, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40000, 0x811);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40020, 0x880);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40040, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40060, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40001, 0x4008);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40021, 0x83);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40041, 0x4f);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40061, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40002, 0x4040);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40022, 0x83);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40042, 0x51);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40062, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40003, 0x811);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40023, 0x880);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40043, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40063, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40004, 0x720);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40024, 0xf);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40044, 0x1740);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40064, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40005, 0x16);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40025, 0x83);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40045, 0x4b);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40065, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40006, 0x716);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40026, 0xf);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40046, 0x2001);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40066, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40007, 0x716);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40027, 0xf);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40047, 0x2800);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40067, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40008, 0x716);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40028, 0xf);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40048, 0xf00);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40068, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40009, 0x720);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40029, 0xf);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40049, 0x1400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40069, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000a, 0xe08);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002a, 0xc15);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000b, 0x623);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002b, 0x15);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004b, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006b, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000c, 0x4028);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002c, 0x80);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004c, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006c, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000d, 0xe08);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002d, 0xc1a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000e, 0x623);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002e, 0x1a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4000f, 0x4040);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4002f, 0x80);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4004f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4006f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40010, 0x2604);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40030, 0x15);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40050, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40070, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40011, 0x708);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40031, 0x5);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40051, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40071, 0x2002);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40012, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40032, 0x80);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40052, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40072, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40013, 0x2604);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40033, 0x1a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40053, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40073, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40014, 0x708);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40034, 0xa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40054, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40074, 0x2002);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40015, 0x4040);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40035, 0x80);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40055, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40075, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40016, 0x60a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40036, 0x15);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40056, 0x1200);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40076, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40017, 0x61a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40037, 0x15);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40057, 0x1300);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40077, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40018, 0x60a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40038, 0x1a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40058, 0x1200);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40078, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40019, 0x642);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40039, 0x1a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40059, 0x1300);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40079, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4001a, 0x4808);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4003a, 0x880);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4005a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x4007a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900aa, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ab, 0x790);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ac, 0x11a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ad, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ae, 0x7aa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900af, 0x2a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b0, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b1, 0x7b2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b2, 0x2a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b3, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b4, 0x7c8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b5, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b6, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b7, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b8, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900b9, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ba, 0x2a8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bb, 0x129);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bc, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bd, 0x370);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900be, 0x129);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900bf, 0xa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c0, 0x3c8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c1, 0x1a9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c2, 0xc);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c3, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c4, 0x199);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c5, 0x14);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c6, 0x790);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c7, 0x11a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c8, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900c9, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ca, 0x18);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cb, 0xe);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cc, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cd, 0x199);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ce, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900cf, 0x8568);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d0, 0x108);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d1, 0x18);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d2, 0x790);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d3, 0x16a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d4, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d5, 0x1d8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d6, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d7, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d8, 0x8558);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900d9, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900da, 0x70);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900db, 0x788);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900dc, 0x16a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900dd, 0x1ff8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900de, 0x85a8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900df, 0x1e8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e0, 0x50);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e1, 0x798);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e2, 0x16a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e3, 0x60);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e4, 0x7a0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e5, 0x16a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e6, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e7, 0x8310);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e8, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900e9, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ea, 0xa310);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900eb, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ec, 0xa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ed, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ee, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ef, 0x6e);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f0, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f1, 0x68);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f2, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f3, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f4, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f5, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f6, 0x8310);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f7, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f8, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900f9, 0xa310);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fa, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fb, 0x1ff8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fc, 0x85a8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fd, 0x1e8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900fe, 0x68);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x900ff, 0x798);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90100, 0x16a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90101, 0x78);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90102, 0x7a0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90103, 0x16a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90104, 0x68);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90105, 0x790);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90106, 0x16a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90107, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90108, 0x8b10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90109, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010a, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010b, 0xab10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010c, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010d, 0xa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010e, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9010f, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90110, 0x58);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90111, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90112, 0x68);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90113, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90114, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90115, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90116, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90117, 0x8b10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90118, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90119, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011a, 0xab10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011b, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011c, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011d, 0x1d8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011e, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9011f, 0x80);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90120, 0x790);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90121, 0x16a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90122, 0x18);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90123, 0x7aa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90124, 0x6a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90125, 0xa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90126, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90127, 0x1e9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90128, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90129, 0x8080);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012a, 0x108);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012b, 0xf);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012c, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012d, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012e, 0xc);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9012f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90130, 0x68);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90131, 0x9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90132, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90133, 0x1a9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90134, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90135, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90136, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90137, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90138, 0x8080);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90139, 0x108);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013a, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013b, 0x7aa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013c, 0x6a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013e, 0x8568);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9013f, 0x108);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90140, 0xb7);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90141, 0x790);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90142, 0x16a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90143, 0x1f);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90144, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90145, 0x68);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90146, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90147, 0x8558);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90148, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90149, 0xf);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014a, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014b, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014c, 0xc);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014d, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014e, 0x68);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9014f, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90150, 0x408);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90151, 0x169);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90152, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90153, 0x8558);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90154, 0x168);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90155, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90156, 0x3c8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90157, 0x1a9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90158, 0x3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90159, 0x370);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015a, 0x129);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015b, 0x20);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015c, 0x2aa);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015d, 0x9);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9015f, 0x400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90160, 0x10e);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90161, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90162, 0xe8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90163, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90164, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90165, 0x8140);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90166, 0x10c);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90167, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90168, 0x8138);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90169, 0x10c);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016a, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016b, 0x7c8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016c, 0x101);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016d, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016e, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9016f, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90170, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90171, 0x448);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90172, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90173, 0xf);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90174, 0x7c0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90175, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90176, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90177, 0xe8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90178, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90179, 0x47);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017a, 0x630);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017b, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017c, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017d, 0x618);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017e, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9017f, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90180, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90181, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90182, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90183, 0x7c8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90184, 0x109);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90185, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90186, 0x8140);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90187, 0x10c);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90188, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90189, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018a, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018b, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018c, 0x4);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018d, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018e, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9018f, 0x7c8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90190, 0x101);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90006, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90007, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90008, 0x8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90009, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000a, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000b, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd00e7, 0x400);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90017, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9001f, 0x2b);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90026, 0x6c);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d0, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d1, 0x101);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d2, 0x105);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d3, 0x107);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d4, 0x10f);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d5, 0x202);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d6, 0x20a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400d7, 0x20b);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2003a, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000b, 0x64);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000c, 0xc8);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000d, 0x7d0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2000e, 0x2c);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000b, 0x14);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000c, 0x29);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000d, 0x1a1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12000e, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000b, 0x3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000c, 0x6);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000d, 0x3e);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x22000e, 0x10);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000c, 0x0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000d, 0x173);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000e, 0x60);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x9000f, 0x6110);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90010, 0x2152);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90011, 0xdfbd);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90012, 0x60);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x90013, 0x6152);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20010, 0x5a);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20011, 0x3);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40080, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40081, 0x12);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40082, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40083, 0x12);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40084, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x40085, 0x12);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x140080, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x140081, 0x12);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x140082, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x140083, 0x12);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x140084, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x140085, 0x12);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x240080, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x240081, 0x12);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x240082, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x240083, 0x12);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x240084, 0xe0);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x240085, 0x12);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x400fd, 0xf);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10011, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10012, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10013, 0x180);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10018, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x10002, 0x6209);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x100b2, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x101b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x102b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x103b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x104b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x105b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x106b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x107b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x108b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11011, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11012, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11013, 0x180);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11018, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x11002, 0x6209);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x110b2, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x111b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x112b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x113b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x114b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x115b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x116b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x117b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x118b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12011, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12012, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12013, 0x180);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12018, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x12002, 0x6209);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x120b2, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x121b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x122b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x123b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x124b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x125b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x126b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x127b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x128b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13011, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13012, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13013, 0x180);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13018, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x13002, 0x6209);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x130b2, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x131b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x132b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x133b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x134b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x135b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x136b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x137b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x138b4, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20089, 0x1);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20088, 0x19);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xc0080, 0x2);
+ dwc_ddrphy_apb_wr(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1);
+}
diff --git a/board/boundary/nitrogen8m/ddr/helper.c b/board/boundary/nitrogen8m/ddr/helper.c
new file mode 100644
index 0000000000000000000000000000000000000000..c9a02e0ccb0ff68d180b90c1b393cccfef4f30aa
--- /dev/null
+++ b/board/boundary/nitrogen8m/ddr/helper.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/sections.h>
+#include "ddr_memory_map.h"
+
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define IMEM_LEN 32768//23400 //byte
+#define DMEM_LEN 16384//1720 //byte
+#define IMEM_2D_OFFSET 49152
+
+#define IMEM_OFFSET_ADDR 0x00050000
+#define DMEM_OFFSET_ADDR 0x00054000
+#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
+
+/* We need PHY iMEM PHY is 32KB padded */
+void ddr_load_train_code(enum fw_type type)
+{
+ u32 tmp32, i;
+ u32 error = 0;
+ unsigned long pr_to32, pr_from32;
+ unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
+ unsigned long imem_start = (unsigned long)&_end + fw_offset;
+ unsigned long dmem_start = imem_start + IMEM_LEN;
+
+ pr_from32 = imem_start;
+ pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
+ for(i = 0x0; i < IMEM_LEN; ){
+ tmp32 = readl(pr_from32);
+ writew(tmp32 & 0x0000ffff, pr_to32);
+ pr_to32 += 4;
+ writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
+ pr_to32 += 4;
+ pr_from32 += 4;
+ i += 4;
+ }
+
+ pr_from32 = dmem_start;
+ pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
+ for(i = 0x0; i < DMEM_LEN;){
+ tmp32 = readl(pr_from32);
+ writew(tmp32 & 0x0000ffff, pr_to32);
+ pr_to32 += 4;
+ writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
+ pr_to32 += 4;
+ pr_from32 += 4;
+ i += 4;
+ }
+
+ printf("check ddr4_pmu_train_imem code\n");
+ pr_from32 = imem_start;
+ pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
+ for(i = 0x0; i < IMEM_LEN;){
+ tmp32 = (readw(pr_to32) & 0x0000ffff);
+ pr_to32 += 4;
+ tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
+
+ if(tmp32 != readl(pr_from32)){
+ printf("%lx %lx\n", pr_from32, pr_to32);
+ error++;
+ }
+ pr_from32 += 4;
+ pr_to32 += 4;
+ i += 4;
+ }
+ if(error){
+ printf("check ddr4_pmu_train_imem code fail=%d\n",error);
+ }else{
+ printf("check ddr4_pmu_train_imem code pass\n");
+ }
+
+ printf("check ddr4_pmu_train_dmem code\n");
+ pr_from32 = dmem_start;
+ pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
+ for(i = 0x0; i < DMEM_LEN;){
+ tmp32 = (readw(pr_to32) & 0x0000ffff);
+ pr_to32 += 4;
+ tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
+ if(tmp32 != readl(pr_from32)){
+ printf("%lx %lx\n", pr_from32, pr_to32);
+ error++;
+ }
+ pr_from32 += 4;
+ pr_to32 += 4;
+ i += 4;
+ }
+
+ if(error){
+ printf("check ddr4_pmu_train_dmem code fail=%d",error);
+ }else{
+ printf("check ddr4_pmu_train_dmem code pass\n");
+ }
+}
diff --git a/board/boundary/nitrogen8m/ddr/lpddr4_dvfs.h b/board/boundary/nitrogen8m/ddr/lpddr4_dvfs.h
new file mode 100644
index 0000000000000000000000000000000000000000..5a45d99a6becfde39f1faef82da824caa5837a82
--- /dev/null
+++ b/board/boundary/nitrogen8m/ddr/lpddr4_dvfs.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __LPDDR4_DVFS_H__
+#define __LPDDR4_DVFS_H__
+#include "ddr_memory_map.h"
+
+#define DFILP_SPT
+
+#define ANAMIX_PLL_BASE_ADDR 0x30360000
+#define HW_DRAM_PLL_CFG0_ADDR (ANAMIX_PLL_BASE_ADDR + 0x60)
+#define HW_DRAM_PLL_CFG1_ADDR (ANAMIX_PLL_BASE_ADDR + 0x64)
+#define HW_DRAM_PLL_CFG2_ADDR (ANAMIX_PLL_BASE_ADDR + 0x68)
+
+#define LPDDR4_HDT_CTL_2D 0xC8 /* stage completion */
+#define LPDDR4_HDT_CTL_3200_1D 0xC8 /* stage completion */
+#define LPDDR4_HDT_CTL_400_1D 0xC8 /* stage completion */
+#define LPDDR4_HDT_CTL_100_1D 0xC8 /* stage completion */
+
+/* 2D share & weight */
+#define LPDDR4_2D_WEIGHT 0x1f7f
+#define LPDDR4_2D_SHARE 1
+#define LPDDR4_CATRAIN_3200_1d 0
+#define LPDDR4_CATRAIN_400 0
+#define LPDDR4_CATRAIN_100 0
+#define LPDDR4_CATRAIN_3200_2d 0
+
+#define WR_POST_EXT_3200 /* recommened to define */
+
+/* lpddr4 phy training config */
+/* for LPDDR4 Rtt */
+#define LPDDR4_RTT40 6
+#define LPDDR4_RTT48 5
+#define LPDDR4_RTT60 4
+#define LPDDR4_RTT80 3
+#define LPDDR4_RTT120 2
+#define LPDDR4_RTT240 1
+#define LPDDR4_RTT_DIS 0
+
+/* for LPDDR4 Ron */
+#define LPDDR4_RON34 7
+#define LPDDR4_RON40 6
+#define LPDDR4_RON48 5
+#define LPDDR4_RON60 4
+#define LPDDR4_RON80 3
+
+#define LPDDR4_PHY_ADDR_RON60 0x1
+#define LPDDR4_PHY_ADDR_RON40 0x3
+#define LPDDR4_PHY_ADDR_RON30 0x7
+#define LPDDR4_PHY_ADDR_RON24 0xf
+#define LPDDR4_PHY_ADDR_RON20 0x1f
+
+/* for read channel */
+#define LPDDR4_RON LPDDR4_RON40 /* MR3[5:3] */
+#define LPDDR4_PHY_RTT 30
+#define LPDDR4_PHY_VREF_VALUE 17
+
+/* for write channel */
+#define LPDDR4_PHY_RON 30
+#define LPDDR4_PHY_ADDR_RON LPDDR4_PHY_ADDR_RON40
+#define LPDDR4_RTT_DQ LPDDR4_RTT40 /* MR11[2:0] */
+#define LPDDR4_RTT_CA LPDDR4_RTT40 /* MR11[6:4] */
+#define LPDDR4_RTT_CA_BANK0 LPDDR4_RTT40 /* MR11[6:4] */
+#define LPDDR4_RTT_CA_BANK1 LPDDR4_RTT40 /* LPDDR4_RTT_DIS//MR11[6:4] */
+#define LPDDR4_VREF_VALUE_CA ((1<<6)|(0xd)) /*((0<<6)|(0xe)) MR12 */
+#define LPDDR4_VREF_VALUE_DQ_RANK0 ((1<<6)|(0xd)) /* MR14 */
+#define LPDDR4_VREF_VALUE_DQ_RANK1 ((1<<6)|(0xd)) /* MR14 */
+#define LPDDR4_MR22_RANK0 ((0<<5)|(1<<4)|(0<<3)|(LPDDR4_RTT40)) /* MR22: OP[5:3]ODTD-CA,CS,CK */
+#define LPDDR4_MR22_RANK1 ((0<<5)|(1<<4)|(0<<3)|(LPDDR4_RTT40)) /* MR22: OP[5:3]ODTD-CA,CS,CK */
+#define LPDDR4_MR3_PU_CAL 1 /* MR3[0] */
+
+#define LPDDR4_2D_WEIGHT 0x1f7f
+#define LPDDR4_2D_SHARE 1
+
+#endif /*__LPDDR4_DVFS_H__ */
diff --git a/board/boundary/nitrogen8m/ddr/wait_ddrphy_training_complete.c b/board/boundary/nitrogen8m/ddr/wait_ddrphy_training_complete.c
new file mode 100644
index 0000000000000000000000000000000000000000..0b42e58bd1d0881f9ddd203285e9097eb9717111
--- /dev/null
+++ b/board/boundary/nitrogen8m/ddr/wait_ddrphy_training_complete.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+static inline void poll_pmu_message_ready(void)
+{
+ unsigned int reg;
+
+ do {
+ reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004);
+ } while (reg & 0x1);
+}
+
+static inline void ack_pmu_message_recieve(void)
+{
+ unsigned int reg;
+
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x0);
+
+ do {
+ reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004);
+ } while (!(reg & 0x1));
+
+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x1);
+}
+
+static inline unsigned int get_mail(void)
+{
+ unsigned int reg;
+
+ poll_pmu_message_ready();
+
+ reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032);
+
+ ack_pmu_message_recieve();
+
+ return reg;
+}
+
+static inline unsigned int get_stream_message(void)
+{
+ unsigned int reg, reg2;
+
+ poll_pmu_message_ready();
+
+ reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032);
+
+ reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0034);
+
+ reg2 = (reg2 << 16) | reg;
+
+ ack_pmu_message_recieve();
+
+ return reg2;
+}
+
+static inline void decode_major_message(unsigned int mail)
+{
+ ddr_printf("[PMU Major message = 0x%08x]\n", mail);
+}
+
+static inline void decode_streaming_message(void)
+{
+ unsigned int string_index, arg __maybe_unused;
+ int i = 0;
+
+ string_index = get_stream_message();
+ ddr_printf(" PMU String index = 0x%08x\n", string_index);
+ while (i < (string_index & 0xffff)){
+ arg = get_stream_message();
+ ddr_printf(" arg[%d] = 0x%08x\n", i, arg);
+ i++;
+ }
+
+ ddr_printf("\n");
+}
+
+void wait_ddrphy_training_complete(void)
+{
+ unsigned int mail;
+ while (1) {
+ mail = get_mail();
+ decode_major_message(mail);
+ if (mail == 0x08) {
+ decode_streaming_message();
+ } else if (mail == 0x07) {
+ printf("Training PASS\n");
+ break;
+ } else if (mail == 0xff) {
+ printf("Training FAILED\n");
+ break;
+ }
+ }
+}
diff --git a/board/boundary/nitrogen8m/mmc.c b/board/boundary/nitrogen8m/mmc.c
new file mode 100644
index 0000000000000000000000000000000000000000..fcb35fce30db3389483698210a5a23b5a2d47e4e
--- /dev/null
+++ b/board/boundary/nitrogen8m/mmc.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+#include <stdbool.h>
+
+/* This should be defined for each board */
+__weak int mmc_map_to_kernel_blk(int dev_no)
+{
+ return dev_no;
+}
+
+void board_late_mmc_env_init(void)
+{
+ env_set_ulong("mmcdev", 0);
+
+ /* Set mmcblk env */
+ env_set("mmcroot", "/dev/mmcblk0p2 rootwait rw");
+ run_command("mmc dev 0", 0);
+}
diff --git a/board/boundary/nitrogen8m/nitrogen8m.c b/board/boundary/nitrogen8m/nitrogen8m.c
new file mode 100644
index 0000000000000000000000000000000000000000..f1b42defabfd761d0e066816fa95b7bd25f2cd9e
--- /dev/null
+++ b/board/boundary/nitrogen8m/nitrogen8m.c
@@ -0,0 +1,506 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <asm/arch/mx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/video.h>
+#include <video_fb.h>
+#include <spl.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include <dm.h>
+#include <usb.h>
+#include <dwc3-uboot.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define QSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS)
+
+#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+
+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define WEAK_PULLUP (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+static iomux_v3_cfg_t const init_pads[] = {
+#if 0
+ IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+#else
+ IMX8MQ_PAD_GPIO1_IO02__GPIO1_IO2 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+#endif
+ IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+
+#define GP_ARM_DRAM_VSEL IMX_GPIO_NR(3, 24)
+ IMX8MQ_PAD_SAI5_RXD3__GPIO3_IO24 | MUX_PAD_CTRL(0x16),
+#define GP_DRAM_1P1_VSEL IMX_GPIO_NR(2, 11)
+ IMX8MQ_PAD_SD1_STROBE__GPIO2_IO11 | MUX_PAD_CTRL(0x16),
+#define GP_SOC_GPU_VPU_VSEL IMX_GPIO_NR(2, 20)
+ IMX8MQ_PAD_SD2_WP__GPIO2_IO20 | MUX_PAD_CTRL(0x16),
+
+#define GP_FASTBOOT_KEY IMX_GPIO_NR(1, 7)
+ IMX8MQ_PAD_GPIO1_IO07__GPIO1_IO7 | MUX_PAD_CTRL(WEAK_PULLUP),
+
+#define GP_I2C1_PCA9546_RESET IMX_GPIO_NR(1, 8)
+ IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(0x49),
+
+#define GP_I2C4_SN65DSI83_EN IMX_GPIO_NR(3, 15)
+ IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 | MUX_PAD_CTRL(WEAK_PULLUP),
+
+#define GP_EMMC_RESET IMX_GPIO_NR(2, 10)
+ IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(0x41),
+
+#define GP_CSI1_MIPI_PWDN IMX_GPIO_NR(3, 3)
+ IMX8MQ_PAD_NAND_CE2_B__GPIO3_IO3 | MUX_PAD_CTRL(0x61),
+#define GP_CSI1_MIPI_RESET IMX_GPIO_NR(3, 17)
+ IMX8MQ_PAD_NAND_WE_B__GPIO3_IO17 | MUX_PAD_CTRL(0x61),
+
+#define GP_CSI2_MIPI_PWDN IMX_GPIO_NR(3, 2)
+ IMX8MQ_PAD_NAND_CE1_B__GPIO3_IO2 | MUX_PAD_CTRL(0x61),
+#define GP_CSI2_MIPI_RESET IMX_GPIO_NR(2, 19)
+ IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 |MUX_PAD_CTRL(0x61),
+};
+
+int board_early_init_f(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+ imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
+ set_wdog_reset(wdog);
+
+ gpio_direction_output(GP_ARM_DRAM_VSEL, 0);
+ gpio_direction_output(GP_DRAM_1P1_VSEL, 0);
+ gpio_direction_output(GP_SOC_GPU_VPU_VSEL, 0);
+ gpio_direction_output(GP_EMMC_RESET, 1);
+ gpio_direction_output(GP_I2C1_PCA9546_RESET, 0);
+ gpio_direction_output(GP_I2C4_SN65DSI83_EN, 0);
+ gpio_direction_output(GP_CSI1_MIPI_PWDN, 1);
+ gpio_direction_output(GP_CSI1_MIPI_RESET, 0);
+ gpio_direction_output(GP_CSI2_MIPI_PWDN, 1);
+ gpio_direction_output(GP_CSI2_MIPI_RESET, 0);
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_POSTCLK_INIT
+int board_postclk_init(void)
+{
+ /* TODO */
+ return 0;
+}
+#endif
+
+int dram_init(void)
+{
+ /* rom_pointer[1] contains the size of TEE occupies */
+ if (rom_pointer[1])
+ gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
+ else
+ gd->ram_size = PHYS_SDRAM_SIZE;
+
+ return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_PHY_ATHEROS
+#define WEAK_PULLDN_OUTPUT 0x91
+#define WEAK_PULLUP_OUTPUT 0xd1
+
+#define PULL_GP(a, bit) (((a >> bit) & 1) ? WEAK_PULLUP_OUTPUT : WEAK_PULLDN_OUTPUT)
+#define PULL_ENET(a, bit) 0x91
+
+#define GP_PHY_RX_CTL IMX_GPIO_NR(1, 24)
+#define GP_PHY_RXC IMX_GPIO_NR(1, 25)
+#define GP_PHY_RD0 IMX_GPIO_NR(1, 26)
+#define GP_PHY_RD1 IMX_GPIO_NR(1, 27)
+#define GP_PHY_RD2 IMX_GPIO_NR(1, 28)
+#define GP_PHY_RD3 IMX_GPIO_NR(1, 29)
+
+#ifndef STRAP_AR8035
+#define STRAP_AR8035 ((0x28 | (CONFIG_FEC_MXC_PHYADDR & 3)) | ((0x28 | ((CONFIG_FEC_MXC_PHYADDR + 1) & 3)) << 6))
+#endif
+
+#define IOMUX_PAD_CTRL(name, ctrl) NEW_PAD_CTRL(IMX8MQ_PAD_##name, ctrl)
+
+static const iomux_v3_cfg_t enet_ar8035_gpio_pads[] = {
+#define GP_RGMII_PHY_RESET IMX_GPIO_NR(1, 9)
+ IOMUX_PAD_CTRL(GPIO1_IO09__GPIO1_IO9, PAD_CTL_DSE6),
+ IOMUX_PAD_CTRL(ENET_RD0__GPIO1_IO26, PULL_GP(STRAP_AR8035, 0)),
+ IOMUX_PAD_CTRL(ENET_RD1__GPIO1_IO27, PULL_GP(STRAP_AR8035, 1)),
+ IOMUX_PAD_CTRL(ENET_RD2__GPIO1_IO28, PULL_GP(STRAP_AR8035, 2)),
+ IOMUX_PAD_CTRL(ENET_RD3__GPIO1_IO29, PULL_GP(STRAP_AR8035, 3)),
+ IOMUX_PAD_CTRL(ENET_RX_CTL__GPIO1_IO24, PULL_GP(STRAP_AR8035, 4)),
+ /* 1.8V(1)/1.5V select(0) */
+ IOMUX_PAD_CTRL(ENET_RXC__GPIO1_IO25, PULL_GP(STRAP_AR8035, 5)),
+};
+
+static const iomux_v3_cfg_t enet_ar8035_pads[] = {
+ IOMUX_PAD_CTRL(ENET_RD0__ENET_RGMII_RD0, PULL_ENET(STRAP_AR8035, 0)),
+ IOMUX_PAD_CTRL(ENET_RD1__ENET_RGMII_RD1, PULL_ENET(STRAP_AR8035, 1)),
+ IOMUX_PAD_CTRL(ENET_RD2__ENET_RGMII_RD2, PULL_ENET(STRAP_AR8035, 2)),
+ IOMUX_PAD_CTRL(ENET_RD3__ENET_RGMII_RD3, PULL_ENET(STRAP_AR8035, 3)),
+ IOMUX_PAD_CTRL(ENET_RX_CTL__ENET_RGMII_RX_CTL, PULL_ENET(STRAP_AR8035, 4)),
+ IOMUX_PAD_CTRL(ENET_RXC__ENET_RGMII_RXC, PULL_ENET(STRAP_AR8035, 5)),
+};
+
+static unsigned char strap_gpios[] = {
+ GP_PHY_RD0,
+ GP_PHY_RD1,
+ GP_PHY_RD2, /* 0 */
+ GP_PHY_RD3, /* 1 */
+ GP_PHY_RX_CTL, /* 0 */
+ GP_PHY_RXC, /* 1 with LED_1000 pulled high, yields mode 0xc (RGMII, PLLOFF,INT) */
+};
+
+static void set_strap_pins(unsigned strap)
+{
+ int i = 0;
+
+ for (i = 0; i < ARRAY_SIZE(strap_gpios); i++) {
+ gpio_direction_output(strap_gpios[i], strap & 1);
+ strap >>= 1;
+ }
+}
+
+static void setup_gpio_ar8035(void)
+{
+ set_strap_pins(STRAP_AR8035);
+ SETUP_IOMUX_PADS(enet_ar8035_gpio_pads);
+}
+
+static void setup_enet_ar8035(void)
+{
+ SETUP_IOMUX_PADS(enet_ar8035_pads);
+}
+
+static void setup_iomux_enet(void)
+{
+ gpio_direction_output(GP_RGMII_PHY_RESET, 0); /* PHY rst */
+ setup_gpio_ar8035();
+
+ /* Need delay 10ms according to KSZ9021 spec */
+ /* 1 ms minimum reset pulse for ar8035 */
+ udelay(1000 * 10);
+ gpio_set_value(GP_RGMII_PHY_RESET, 1); /* PHY reset */
+
+ /* strap hold time for AR8035, 5 fails, 6 works, so 12 should be safe */
+ udelay(24);
+
+ setup_enet_ar8035();
+}
+
+static void phy_ar8031_config(struct phy_device *phydev)
+{
+ int val;
+
+ /* Select 125MHz clk from local PLL on CLK_25M */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x0007);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+ val &= ~0x1c;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (val|0x0018));
+
+#if 0 //done in ar8031_config
+ /* introduce tx clock delay */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (val|0x0100));
+#endif
+}
+
+static void phy_ar8035_config(struct phy_device *phydev)
+{
+ int val;
+
+ /*
+ * Ar803x phy SmartEEE feature cause link status generates glitch,
+ * which cause ethernet link down/up issue, so disable SmartEEE
+ */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val & ~(1 << 8));
+
+#if 0 //done in ar8035_config
+ /* rgmii tx clock delay enable */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (val|0x0100));
+
+ phydev->supported = phydev->drv->features;
+#endif
+}
+
+#define PHY_ID_AR8031 0x004dd074
+#define PHY_ID_AR8035 0x004dd072
+
+int board_phy_config(struct phy_device *phydev)
+{
+ if (((phydev->drv->uid ^ PHY_ID_AR8031) & 0xffffffef) == 0)
+ phy_ar8031_config(phydev);
+ else if (((phydev->drv->uid ^ PHY_ID_AR8035) & 0xffffffef) == 0)
+ phy_ar8035_config(phydev);
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+
+#define IOMUXC_GPR1 (IOMUXC_GPR_BASE_ADDR + 0x04)
+
+static int setup_fec(void)
+{
+ gpio_request(GP_RGMII_PHY_RESET, "fec_rst");
+ gpio_request(GP_PHY_RD0, "fec_rd0");
+ gpio_request(GP_PHY_RD1, "fec_rd1");
+ gpio_request(GP_PHY_RD2, "fec_rd2");
+ gpio_request(GP_PHY_RD3, "fec_rd3");
+ gpio_request(GP_PHY_RX_CTL, "fec_rx_ctl");
+ gpio_request(GP_PHY_RXC, "fec_rxc");
+ setup_iomux_enet();
+
+ /* Use 125M anatop REF_CLK1 for ENET1, not from external */
+ clrsetbits_le32(IOMUXC_GPR1,
+ BIT(13) | BIT(17), 0);
+ return set_clk_enet(ENET_125MHZ);
+}
+#endif
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
+
+#define USB_PHY_CTRL0 0xF0040
+#define USB_PHY_CTRL0_REF_SSP_EN BIT(2)
+
+#define USB_PHY_CTRL1 0xF0044
+#define USB_PHY_CTRL1_RESET BIT(0)
+#define USB_PHY_CTRL1_COMMONONN BIT(1)
+#define USB_PHY_CTRL1_ATERESET BIT(3)
+#define USB_PHY_CTRL1_VDATSRCENB0 BIT(19)
+#define USB_PHY_CTRL1_VDATDETENB0 BIT(20)
+
+#define USB_PHY_CTRL2 0xF0048
+#define USB_PHY_CTRL2_TXENABLEN0 BIT(8)
+
+static struct dwc3_device dwc3_device_data = {
+ .maximum_speed = USB_SPEED_SUPER,
+ .base = USB1_BASE_ADDR,
+ .dr_mode = USB_DR_MODE_PERIPHERAL,
+ .index = 0,
+// .power_down_scale = 2,
+};
+
+int usb_gadget_handle_interrupts(void)
+{
+ dwc3_uboot_handle_interrupt(0);
+ return 0;
+}
+
+static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3)
+{
+ u32 RegData;
+
+ RegData = readl(dwc3->base + USB_PHY_CTRL1);
+ RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 |
+ USB_PHY_CTRL1_COMMONONN);
+ RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET;
+ writel(RegData, dwc3->base + USB_PHY_CTRL1);
+
+ RegData = readl(dwc3->base + USB_PHY_CTRL0);
+ RegData |= USB_PHY_CTRL0_REF_SSP_EN;
+ writel(RegData, dwc3->base + USB_PHY_CTRL0);
+
+ RegData = readl(dwc3->base + USB_PHY_CTRL2);
+ RegData |= USB_PHY_CTRL2_TXENABLEN0;
+ writel(RegData, dwc3->base + USB_PHY_CTRL2);
+
+ RegData = readl(dwc3->base + USB_PHY_CTRL1);
+ RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET);
+ writel(RegData, dwc3->base + USB_PHY_CTRL1);
+}
+#endif
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M)
+int board_usb_init(int index, enum usb_init_type init)
+{
+ int ret = 0;
+ imx8m_usb_power(index, true);
+
+ if (index == 0 && init == USB_INIT_DEVICE) {
+ dwc3_nxp_usb_phy_init(&dwc3_device_data);
+ return dwc3_uboot_init(&dwc3_device_data);
+ } else if (index == 0 && init == USB_INIT_HOST) {
+ return ret;
+ }
+
+ if (index == 1) {
+ /* Release HUB reset */
+#define GP_USB1_HUB_RESET IMX_GPIO_NR(1, 14)
+ imx_iomux_v3_setup_pad(IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 |
+ MUX_PAD_CTRL(WEAK_PULLUP));
+ gpio_request(GP_USB1_HUB_RESET, "usb1_rst");
+ gpio_direction_output(GP_USB1_HUB_RESET, 1);
+ }
+
+ return 0;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ int ret = 0;
+ if (index == 0 && init == USB_INIT_DEVICE)
+ dwc3_uboot_exit(index);
+
+ imx8m_usb_power(index, false);
+
+ return ret;
+}
+#endif
+
+int board_init(void)
+{
+#ifdef CONFIG_FEC_MXC
+ setup_fec();
+#endif
+
+ return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+ return 0;
+}
+
+#if defined(CONFIG_CMD_FASTBOOT) || defined(CONFIG_CMD_DFU)
+extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
+static void addserial_env(const char* env_var)
+{
+ unsigned char mac_address[8];
+ char serialbuf[20];
+
+ if (!env_get(env_var)) {
+ imx_get_mac_from_fuse(0, mac_address);
+ snprintf(serialbuf, sizeof(serialbuf), "%02x%02x%02x%02x%02x%02x",
+ mac_address[0], mac_address[1], mac_address[2],
+ mac_address[3], mac_address[4], mac_address[5]);
+ env_set(env_var, serialbuf);
+ }
+}
+#endif
+
+#ifdef CONFIG_CMD_BMODE
+const struct boot_mode board_boot_modes[] = {
+ /* 4 bit bus width */
+ {"emmc0", MAKE_CFGVAL(0x22, 0x20, 0x00, 0x10)},
+ {NULL, 0},
+};
+#endif
+
+static int fastboot_key_pressed(void)
+{
+ gpio_request(GP_FASTBOOT_KEY, "fastboot_key");
+ gpio_direction_input(GP_FASTBOOT_KEY);
+ return !gpio_get_value(GP_FASTBOOT_KEY);
+}
+
+void board_late_mmc_env_init(void);
+void init_usb_clk(int usbno);
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ env_set("board", "nitrogen8m");
+ env_set("soc", "imx8mq");
+ env_set("cpu", get_imx_type((get_cpu_rev() & 0xFF000) >> 12));
+ env_set("imx_cpu", get_imx_type((get_cpu_rev() & 0xFF000) >> 12));
+ env_set("uboot_defconfig", CONFIG_DEFCONFIG);
+#endif
+#if defined(CONFIG_USB_FUNCTION_FASTBOOT) || defined(CONFIG_CMD_DFU)
+ addserial_env("serial#");
+ if (fastboot_key_pressed()) {
+ printf("Starting fastboot...\n");
+ env_set("preboot", "fastboot 0");
+ }
+#endif
+#ifdef CONFIG_ENV_IS_IN_MMC
+ board_late_mmc_env_init();
+#endif
+#ifdef CONFIG_CMD_BMODE
+ add_board_boot_modes(board_boot_modes);
+#endif
+ init_usb_clk(0);
+ init_usb_clk(1);
+ return 0;
+}
+
+#if defined(CONFIG_VIDEO_IMXDCSS)
+
+struct display_info_t const displays[] = {{
+ .bus = 0, /* Unused */
+ .addr = 0, /* Unused */
+ .pixfmt = GDF_32BIT_X888RGB,
+ .detect = NULL,
+ .enable = NULL,
+#ifndef CONFIG_VIDEO_IMXDCSS_1080P
+ .mode = {
+ .name = "HDMI", /* 720P60 */
+ .refresh = 60,
+ .xres = 1280,
+ .yres = 720,
+ .pixclock = 13468, /* 74250 kHz */
+ .left_margin = 110,
+ .right_margin = 220,
+ .upper_margin = 5,
+ .lower_margin = 20,
+ .hsync_len = 40,
+ .vsync_len = 5,
+ .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ .vmode = FB_VMODE_NONINTERLACED
+ }
+#else
+ .mode = {
+ .name = "HDMI", /* 1080P60 */
+ .refresh = 60,
+ .xres = 1920,
+ .yres = 1080,
+ .pixclock = 6734, /* 148500 kHz */
+ .left_margin = 148,
+ .right_margin = 88,
+ .upper_margin = 36,
+ .lower_margin = 4,
+ .hsync_len = 44,
+ .vsync_len = 5,
+ .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+ .vmode = FB_VMODE_NONINTERLACED
+ }
+#endif
+} };
+size_t display_count = ARRAY_SIZE(displays);
+
+#endif /* CONFIG_VIDEO_IMXDCSS */
diff --git a/board/boundary/nitrogen8m/spl.c b/board/boundary/nitrogen8m/spl.c
new file mode 100644
index 0000000000000000000000000000000000000000..3efa26565864a6a9e4243e192253430d25e3161f
--- /dev/null
+++ b/board/boundary/nitrogen8m/spl.c
@@ -0,0 +1,225 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/mx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include "ddr/ddr.h"
+#include "ddr/ddr_memory_map.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_dram_init(void)
+{
+ /* ddr init */
+ ddr_init();
+}
+
+#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
+ .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
+ .gp = IMX_GPIO_NR(5, 14),
+ },
+ .sda = {
+ .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
+ .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
+ .gp = IMX_GPIO_NR(5, 15),
+ },
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+ switch (cfg->esdhc_base) {
+ case USDHC1_BASE_ADDR:
+ return 1;
+ }
+ return 0;
+}
+
+#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
+ PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+#define GP_EMMC_RESET IMX_GPIO_NR(2, 10)
+ IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC1_BASE_ADDR, 0, 8},
+};
+
+int board_mmc_init(bd_t *bis)
+{
+ int i, ret;
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-Boot device node) (Physical Port)
+ * mmc0 USDHC1
+ * mmc1 USDHC2
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
+ imx_iomux_v3_setup_multiple_pads(
+ usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ gpio_request(GP_EMMC_RESET, "usdhc1_reset");
+ gpio_direction_output(GP_EMMC_RESET, 0);
+ udelay(500);
+ gpio_direction_output(GP_EMMC_RESET, 1);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers"
+ "(%d) than supported by the board\n", i + 1);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_POWER
+#define GP_ARM_DRAM_VSEL IMX_GPIO_NR(3, 24)
+#define GP_DRAM_1P1_VSEL IMX_GPIO_NR(2, 11)
+#define GP_SOC_GPU_VPU_VSEL IMX_GPIO_NR(2, 20)
+
+#define GP_I2C1_PCA9546_RESET IMX_GPIO_NR(1, 8)
+
+#define I2C_MUX_ADDR 0x70
+#define I2C_FAN53555_ADDR 0x60
+void ddr_voltage_init(void)
+{
+ u8 val8;
+
+ gpio_set_value(GP_I2C1_PCA9546_RESET, 1);
+ gpio_set_value(GP_ARM_DRAM_VSEL, 0);
+ gpio_set_value(GP_DRAM_1P1_VSEL, 0);
+ gpio_set_value(GP_SOC_GPU_VPU_VSEL, 0);
+ printf("Setting voltages\n");
+ /*
+ * 9e (1e = 30) default .9 V
+ * 0.6V to 1.23V in 10 MV steps
+ */
+
+ /* Enable I2C1A, ARM/DRAM */
+ i2c_write(I2C_MUX_ADDR, 1, 1, NULL, 0);
+ /*
+ * .6 + .40 = 1.00
+ */
+ val8 = 0x80 + 40;
+ i2c_write(I2C_FAN53555_ADDR, 0, 1, &val8, 1);
+ i2c_write(I2C_FAN53555_ADDR, 1, 1, &val8, 1);
+
+ /* Enable I2C1B, DRAM 1.1V */
+ i2c_write(I2C_MUX_ADDR, 2, 1, NULL, 0);
+ /*
+ * .6 + .50 = 1.10
+ */
+ val8 = 0x80 + 50;
+ i2c_write(I2C_FAN53555_ADDR, 0, 1, &val8, 1);
+ i2c_write(I2C_FAN53555_ADDR, 1, 1, &val8, 1);
+
+ /* Enable I2C1C, soc/gpu/vpu */
+ i2c_write(I2C_MUX_ADDR, 4, 1, NULL, 0);
+ /*
+ * .6 + .30 = .90
+ */
+ val8 = 0x80 + 30;
+ i2c_write(I2C_FAN53555_ADDR, 0, 1, &val8, 1);
+ i2c_write(I2C_FAN53555_ADDR, 1, 1, &val8, 1);
+
+ /* Disable I2C1A-I2C1D */
+ i2c_write(I2C_MUX_ADDR, 0, 1, NULL, 0);
+}
+
+int power_init_board(void)
+{
+ /* Nitrogen8M I2C write */
+ ddr_voltage_init();
+ return 0;
+}
+#endif
+
+void spl_board_init(void)
+{
+ enable_tzc380();
+
+ /* Adjust pmic voltage to 1.0V for 800M */
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+ power_init_board();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ /* Serial download mode */
+ if (is_usb_boot()) {
+ puts("Back to ROM, SDP\n");
+ restore_boot_params();
+ }
+ puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+ /* Clear global data */
+ memset((void *)gd, 0, sizeof(gd_t));
+
+ arch_cpu_init();
+
+ board_early_init_f();
+ init_uart_clk(0);
+ timer_init();
+
+ preloader_console_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ board_init_r(NULL, 0);
+}
diff --git a/configs/nitrogen8m_defconfig b/configs/nitrogen8m_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..d1243ac1e461e8bc3bcf7a099b74f50ce7d2394a
--- /dev/null
+++ b/configs/nitrogen8m_defconfig
@@ -0,0 +1,75 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_NITROGEN8M=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0x30860000
+CONFIG_DEBUG_UART_CLOCK=25000000
+CONFIG_DEFAULT_DEVICE_TREE="imx8mq-nitrogen8m"
+CONFIG_DEBUG_UART=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,DEFCONFIG=\"nitrogen8m\""
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x40480000
+CONFIG_FASTBOOT_BUF_SIZE=0x20000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DEBUG_UART_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Boundary"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_VIDEO=y
+CONFIG_VIDEO_IMXDCSS=y
+CONFIG_VIDEO_IMX8_HDMI=y
diff --git a/include/configs/nitrogen8m.h b/include/configs/nitrogen8m.h
new file mode 100644
index 0000000000000000000000000000000000000000..66ea0fb0330588e6030373873a4a31e1f5eec079
--- /dev/null
+++ b/include/configs/nitrogen8m.h
@@ -0,0 +1,243 @@
+/*
+ * Copyright 2018 Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __NITROGEN8M_H
+#define __NITROGEN8M_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CSF_SIZE 0x2000 /* 8K region */
+#endif
+
+#define CONFIG_SPL_TEXT_BASE 0x7E1000
+#define CONFIG_SPL_MAX_SIZE (124 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+
+#ifdef CONFIG_SPL_BUILD
+/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_STACK 0x187FF0
+#define CONFIG_SPL_BSS_START_ADDR 0x00180000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x00182000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x2000 /* 8 KB */
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
+
+#undef CONFIG_DM_MMC
+#undef CONFIG_DM_PMIC
+#undef CONFIG_DM_PMIC_PFUZE100
+
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
+
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+#endif
+
+#define CONFIG_PREBOOT
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_POSTCLK_INIT
+#define CONFIG_BOARD_LATE_INIT
+
+/* Flat Device Tree Definitions */
+#define CONFIG_OF_BOARD_SETUP
+
+#undef CONFIG_CMD_EXPORTENV
+#undef CONFIG_CMD_IMPORTENV
+#undef CONFIG_CMD_IMLS
+
+/* #define CONFIG_CMD_BMODE */
+#undef CONFIG_CMD_CRC32
+#undef CONFIG_BOOTM_NETBSD
+
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_MII
+#define CONFIG_ETHPRIME "FEC"
+
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_MXC_PHYADDR 4
+#define FEC_QUIRK_ENET_MAC
+
+#define CONFIG_PHY_GIGE
+#define IMX_FEC_BASE 0x30BE0000
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+#endif
+
+/* Link Definitions */
+#define CONFIG_LOADADDR 0x40480000
+#define CONFIG_SYS_TEXT_BASE 0x40200000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_SIZE 0x1000
+#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
+#define CONFIG_SYS_MMC_ENV_PART 1 /* mmcblk0boot0 */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2*1024) + (16*1024)) * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM 0x40000000
+#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 2048
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_IMX_BOOTAUX
+
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+
+#define CONFIG_SYS_FSL_USDHC_NUM 1
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+#define CONFIG_SUPPORT_EMMC_RPMB
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_OCOTP
+#define CONFIG_CMD_FUSE
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* USB configs */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
+#define CONFIG_USB_DWC3
+#define CONFIG_USB_DWC3_GADGET
+#define CONFIG_USBD_HS
+
+#define CONFIG_USB_GADGET_MASS_STORAGE
+#define CONFIG_USB_GADGET_VBUS_DRAW 2
+#define CONFIG_USB_GADGET_DUALSPEED
+
+#endif
+
+#define CONFIG_OF_SYSTEM_SETUP
+
+/* Framebuffer */
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#define CONFIG_BMP_16BPP
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+#define CONFIG_IMX_VIDEO_SKIP
+#endif
+
+#ifndef BD_CONSOLE
+#if CONFIG_MXC_UART_BASE == UART2_BASE_ADDR
+#define BD_CONSOLE "ttymxc1"
+#elif CONFIG_MXC_UART_BASE == UART1_BASE_ADDR
+#define BD_CONSOLE "ttymxc0"
+#endif
+#endif
+
+#ifdef CONFIG_CMD_MMC
+#if (CONFIG_SYS_FSL_USDHC_NUM == 1)
+#define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0)
+#elif (CONFIG_SYS_FSL_USDHC_NUM == 2)
+#define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1)
+#else
+#define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) func(MMC, mmc, 2)
+#endif
+#else
+#define DISTRO_BOOT_DEV_MMC(func)
+#endif
+
+#ifdef CONFIG_USB_STORAGE
+#define DISTRO_BOOT_DEV_USB(func) func(USB, usb, 0)
+#else
+#define DISTRO_BOOT_DEV_USB(func)
+#endif
+
+#ifndef BOOT_TARGET_DEVICES
+#define BOOT_TARGET_DEVICES(func) \
+ DISTRO_BOOT_DEV_MMC(func) \
+ DISTRO_BOOT_DEV_USB(func)
+#endif
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "console=" BD_CONSOLE "\0" \
+ "env_dev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+ "env_part=" __stringify(CONFIG_SYS_MMC_ENV_PART) "\0" \
+ "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+ "fdt_addr=0x43000000\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "netargs=setenv bootargs console=${console},115200 root=/dev/nfs rw " \
+ "ip=dhcp nfsroot=${tftpserverip}:${nfsroot},v3,tcp\0" \
+ "netboot=run netargs; " \
+ "if test -z \"${fdt_file}\" -a -n \"${soc}\"; then " \
+ "setenv fdt_file ${soc}-${board}${boardver}.dtb; " \
+ "fi; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${loadaddr} ${tftpserverip}:Image; " \
+ "if ${get_cmd} ${fdt_addr} ${tftpserverip}:${fdt_file}; then " \
+ "booti ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi;\0" \
+ "upgradeu=setenv boot_scripts upgrade.scr; boot;" \
+ "echo Upgrade failed!; setenv boot_scripts boot.scr\0" \
+ BOOTENV
+
+#endif