diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 450e140329d3260370c2ef9393e4f1f5998fcf75..d721f460a503c64476c03c52bb9af5c612a69e60 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -488,6 +488,9 @@ config TARGET_PER
 config TARGET_RC
 	bool "rc"
 
+config TARGET_S
+	bool "s"
+
 config TARGET_YS
 	bool "ys"
 	select MX6SX
@@ -659,6 +662,7 @@ source "board/boundary/nw/Kconfig"
 source "board/boundary/oc/Kconfig"
 source "board/boundary/per/Kconfig"
 source "board/boundary/rc/Kconfig"
+source "board/boundary/s/Kconfig"
 source "board/boundary/ys/Kconfig"
 source "board/bticino/mamoj/Kconfig"
 source "board/ccv/xpress/Kconfig"
diff --git a/board/boundary/s/Kconfig b/board/boundary/s/Kconfig
new file mode 100644
index 0000000000000000000000000000000000000000..2ae2da901adcf323c9f5a194e4595a52ba4059da
--- /dev/null
+++ b/board/boundary/s/Kconfig
@@ -0,0 +1,24 @@
+if TARGET_S
+
+config SYS_CPU
+	default "armv7"
+
+config SYS_BOARD
+	default "s"
+
+config SYS_VENDOR
+	default "boundary"
+
+config SYS_SOC
+	default "mx6"
+
+config SYS_CONFIG_NAME
+	default "s"
+
+config ENV_WLMAC
+	bool
+	default	y
+
+source "board/boundary/common/Kconfig"
+
+endif
diff --git a/board/boundary/s/MAINTAINERS b/board/boundary/s/MAINTAINERS
new file mode 100644
index 0000000000000000000000000000000000000000..69f9db3b980c3d01e70087f7d729fe3fb8545849
--- /dev/null
+++ b/board/boundary/s/MAINTAINERS
@@ -0,0 +1,7 @@
+S BOARD
+M:	Troy Kisky <troy.kisky@boundarydevices.com>
+S:	Maintained
+F:	board/boundary/s/
+F:	include/configs/s.h
+F:	configs/s_defconfig
+
diff --git a/board/boundary/s/Makefile b/board/boundary/s/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..725d80ae73c795ed4b1b315e8e6849ef8f636abe
--- /dev/null
+++ b/board/boundary/s/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2012-2013, Guennadi Liakhovetski <lg@denx.de>
+# (C) Copyright 2012-2013 Freescale Semiconductor, Inc.
+# Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := s.o
diff --git a/board/boundary/s/s.c b/board/boundary/s/s.c
new file mode 100644
index 0000000000000000000000000000000000000000..758a6c7297defaec2bfe2bb90c1df5b886f7a867
--- /dev/null
+++ b/board/boundary/s/s.c
@@ -0,0 +1,429 @@
+/*
+ * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+#include <malloc.h>
+#include <asm/arch/mx6-pins.h>
+#include <linux/errno.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/fbpanel.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mxc_hdmi.h>
+#include <i2c.h>
+#include <input.h>
+#include <splash.h>
+#include <usb/ehci-ci.h>
+#include "../common/bd_common.h"
+#include "../common/padctrl.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define AUD_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+#define CSI_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define SPI_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_SPEED_MED |	\
+	PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
+#define UART_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
+	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
+	PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+#define USDHC_PAD_CTRL	(PAD_CTL_PUS_47K_UP |			\
+	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
+	PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+
+/*
+ *
+ */
+static const iomux_v3_cfg_t init_pads[] = {
+	/* AUDMUX */
+	IOMUX_PAD_CTRL(CSI0_DAT7__AUD3_RXD, AUD_PAD_CTRL),
+	IOMUX_PAD_CTRL(CSI0_DAT4__AUD3_TXC, AUD_PAD_CTRL),
+	IOMUX_PAD_CTRL(CSI0_DAT5__AUD3_TXD, AUD_PAD_CTRL),
+	IOMUX_PAD_CTRL(CSI0_DAT6__AUD3_TXFS, AUD_PAD_CTRL),
+
+	/* bt_rfkill */
+#define GP_BT_RFKILL_RESET	IMX_GPIO_NR(6, 16)
+	IOMUX_PAD_CTRL(NANDF_CS3__GPIO6_IO16, WEAK_PULLDN),
+
+	/* ECSPI1 */
+	IOMUX_PAD_CTRL(EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
+	IOMUX_PAD_CTRL(EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
+	IOMUX_PAD_CTRL(EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
+#define GP_ECSPI1_NOR_CS	IMX_GPIO_NR(3, 19)
+	IOMUX_PAD_CTRL(EIM_D19__GPIO3_IO19, WEAK_PULLUP),
+
+	/* ECSPI2 */
+	IOMUX_PAD_CTRL(EIM_OE__ECSPI2_MISO, SPI_PAD_CTRL),
+	IOMUX_PAD_CTRL(EIM_CS1__ECSPI2_MOSI, SPI_PAD_CTRL),
+	IOMUX_PAD_CTRL(EIM_CS0__ECSPI2_SCLK, SPI_PAD_CTRL),
+#define GP_ECSPI2_CS1		IMX_GPIO_NR(2, 27)
+	IOMUX_PAD_CTRL(EIM_LBA__GPIO2_IO27, WEAK_PULLUP),
+
+	/* ENET pads that don't change for PHY reset */
+	IOMUX_PAD_CTRL(ENET_MDIO__ENET_MDIO, PAD_CTRL_ENET_MDIO),
+	IOMUX_PAD_CTRL(ENET_MDC__ENET_MDC, PAD_CTRL_ENET_MDC),
+	IOMUX_PAD_CTRL(RGMII_TXC__RGMII_TXC, PAD_CTRL_ENET_TX),
+	IOMUX_PAD_CTRL(RGMII_TD0__RGMII_TD0, PAD_CTRL_ENET_TX),
+	IOMUX_PAD_CTRL(RGMII_TD1__RGMII_TD1, PAD_CTRL_ENET_TX),
+	IOMUX_PAD_CTRL(RGMII_TD2__RGMII_TD2, PAD_CTRL_ENET_TX),
+	IOMUX_PAD_CTRL(RGMII_TD3__RGMII_TD3, PAD_CTRL_ENET_TX),
+	IOMUX_PAD_CTRL(RGMII_TX_CTL__RGMII_TX_CTL, PAD_CTRL_ENET_TX),
+	IOMUX_PAD_CTRL(ENET_REF_CLK__ENET_TX_CLK, PAD_CTRL_ENET_TX),
+	/* pin 42 PHY nRST */
+#define GP_RGMII_PHY_RESET	IMX_GPIO_NR(1, 27)
+	IOMUX_PAD_CTRL(ENET_RXD0__GPIO1_IO27, WEAK_PULLDN),
+#define GPIRQ_ENET_PHY		IMX_GPIO_NR(1, 28)
+	IOMUX_PAD_CTRL(ENET_TX_EN__GPIO1_IO28, WEAK_PULLUP),
+
+	/* FLEXCAN */
+	IOMUX_PAD_CTRL(KEY_COL2__FLEXCAN1_TX, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(KEY_ROW2__FLEXCAN1_RX, WEAK_PULLUP),
+#define GP_FLEXCAN_STANDBY	IMX_GPIO_NR(1, 2)
+	IOMUX_PAD_CTRL(GPIO_2__GPIO1_IO02, WEAK_PULLUP),
+
+	/* gpio_Keys */
+#define GP_TEMP_ALARM		IMX_GPIO_NR(2, 21)
+	IOMUX_PAD_CTRL(EIM_A17__GPIO2_IO21, WEAK_PULLUP),
+#define GP_FAN_FAIL		IMX_GPIO_NR(2, 19)
+	IOMUX_PAD_CTRL(EIM_A19__GPIO2_IO19, WEAK_PULLUP),
+#define GP_AC_FAIL		IMX_GPIO_NR(2, 18)
+	IOMUX_PAD_CTRL(EIM_A20__GPIO2_IO18, WEAK_PULLUP),
+#define GP_J5_PIN33		IMX_GPIO_NR(1, 16)
+	IOMUX_PAD_CTRL(SD1_DAT0__GPIO1_IO16, WEAK_PULLUP),
+#define GP_J34_PIN6		IMX_GPIO_NR(5, 4)
+	IOMUX_PAD_CTRL(EIM_A24__GPIO5_IO04, WEAK_PULLUP),
+#define GP_J34_PIN8		IMX_GPIO_NR(6, 6)
+	IOMUX_PAD_CTRL(EIM_A23__GPIO6_IO06, WEAK_PULLUP),
+#define GP_ON_OFF		IMX_GPIO_NR(2, 7)
+	IOMUX_PAD_CTRL(NANDF_D7__GPIO2_IO07, WEAK_PULLUP),
+
+	/* gpio outputs */
+#define GP_LED_RED		IMX_GPIO_NR(4, 15)
+	IOMUX_PAD_CTRL(KEY_ROW4__GPIO4_IO15, WEAK_PULLUP_OUTPUT),
+#define GP_LED_GREEN		IMX_GPIO_NR(1, 7)
+	IOMUX_PAD_CTRL(GPIO_7__GPIO1_IO07, WEAK_PULLUP_OUTPUT),
+#define GP_LED_AMBER		IMX_GPIO_NR(1, 9)
+	IOMUX_PAD_CTRL(GPIO_9__GPIO1_IO09, WEAK_PULLUP_OUTPUT),
+#define GP_J34_DRY1		IMX_GPIO_NR(2, 16)
+	IOMUX_PAD_CTRL(EIM_A22__GPIO2_IO16, WEAK_PULLDN_OUTPUT),
+#define GP_J34_DRY2		IMX_GPIO_NR(5, 2)
+	IOMUX_PAD_CTRL(EIM_A25__GPIO5_IO02, WEAK_PULLDN_OUTPUT),
+
+	/* gpio test points */
+#define GP_TP_R201	IMX_GPIO_NR(4, 16)
+	IOMUX_PAD_CTRL(DI0_DISP_CLK__GPIO4_IO16, WEAK_PULLUP),
+
+	/* i2c1_isl1208 */
+#define GPIRQ_RTC_ISL1208	IMX_GPIO_NR(6, 7)
+	IOMUX_PAD_CTRL(NANDF_CLE__GPIO6_IO07, WEAK_PULLUP),
+
+	/* i2c1_SGTL5000 sys_mclk */
+	IOMUX_PAD_CTRL(GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
+#define GP_TDA7491P_GAIN0	IMX_GPIO_NR(3, 20)
+	IOMUX_PAD_CTRL(EIM_D20__GPIO3_IO20, WEAK_PULLDN_OUTPUT),
+#define GP_TDA7491P_GAIN1	IMX_GPIO_NR(3, 30)
+	IOMUX_PAD_CTRL(EIM_D30__GPIO3_IO30, WEAK_PULLDN_OUTPUT),
+#define GP_TDA7491P_STBY	IMX_GPIO_NR(2, 20)
+	IOMUX_PAD_CTRL(EIM_A18__GPIO2_IO20, WEAK_PULLDN_OUTPUT),
+#define GP_TDA7491P_MUTE	IMX_GPIO_NR(2, 22)
+	IOMUX_PAD_CTRL(EIM_A16__GPIO2_IO22, WEAK_PULLDN_OUTPUT),
+#define GPIRQ_MIC_DET		IMX_GPIO_NR(1, 24)
+	IOMUX_PAD_CTRL(ENET_RX_ER__GPIO1_IO24, WEAK_PULLUP),
+
+	/* i2c3, ov5642 Camera controls, J5 */
+	IOMUX_PAD_CTRL(CSI0_DAT8__IPU1_CSI0_DATA08, CSI_PAD_CTRL),
+	IOMUX_PAD_CTRL(CSI0_DAT9__IPU1_CSI0_DATA09, CSI_PAD_CTRL),
+	IOMUX_PAD_CTRL(CSI0_DAT10__IPU1_CSI0_DATA10, CSI_PAD_CTRL),
+	IOMUX_PAD_CTRL(CSI0_DAT11__IPU1_CSI0_DATA11, CSI_PAD_CTRL),
+	IOMUX_PAD_CTRL(CSI0_DAT12__IPU1_CSI0_DATA12, CSI_PAD_CTRL),
+	IOMUX_PAD_CTRL(CSI0_DAT13__IPU1_CSI0_DATA13, CSI_PAD_CTRL),
+	IOMUX_PAD_CTRL(CSI0_DAT14__IPU1_CSI0_DATA14, CSI_PAD_CTRL),
+	IOMUX_PAD_CTRL(CSI0_DAT15__IPU1_CSI0_DATA15, CSI_PAD_CTRL),
+	IOMUX_PAD_CTRL(CSI0_DAT16__IPU1_CSI0_DATA16, CSI_PAD_CTRL),
+	IOMUX_PAD_CTRL(CSI0_DAT17__IPU1_CSI0_DATA17, CSI_PAD_CTRL),
+	IOMUX_PAD_CTRL(CSI0_DAT18__IPU1_CSI0_DATA18, CSI_PAD_CTRL),
+	IOMUX_PAD_CTRL(CSI0_DAT19__IPU1_CSI0_DATA19, CSI_PAD_CTRL),
+	IOMUX_PAD_CTRL(CSI0_DATA_EN__IPU1_CSI0_DATA_EN, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(CSI0_PIXCLK__IPU1_CSI0_PIXCLK, CSI_PAD_CTRL),
+	IOMUX_PAD_CTRL(CSI0_MCLK__GPIO5_IO19, WEAK_PULLUP),	/* Hsync */
+	IOMUX_PAD_CTRL(CSI0_VSYNC__GPIO5_IO21, WEAK_PULLUP),	/* Vsync */
+	IOMUX_PAD_CTRL(GPIO_3__CCM_CLKO2, OUTPUT_40OHM),	/* mclk */
+#define GP_OV5642_POWER_DOWN	IMX_GPIO_NR(3, 29)
+	IOMUX_PAD_CTRL(EIM_D29__GPIO3_IO29, WEAK_PULLUP),
+#define GP_OV5642_RESET		IMX_GPIO_NR(1, 8)
+	IOMUX_PAD_CTRL(GPIO_8__GPIO1_IO08, WEAK_PULLDN),
+
+	/* i2c3 edid enable*/
+#define GP_I2C3_EDID		IMX_GPIO_NR(2, 17)
+	IOMUX_PAD_CTRL(EIM_A21__GPIO2_IO17, WEAK_PULLDN_OUTPUT),
+
+	/* Power off */
+#define GP_POWER_OFF		IMX_GPIO_NR(7, 1)
+	IOMUX_PAD_CTRL(SD3_DAT4__GPIO7_IO01, WEAK_PULLDN_OUTPUT),	/* 0 is on */
+
+	/* PWM1 - Backlight on LVDS connector: J6 */
+#define GP_BACKLIGHT_TPS	IMX_GPIO_NR(1, 21)
+	IOMUX_PAD_CTRL(SD1_DAT3__GPIO1_IO21, WEAK_PULLDN),
+
+	/* PWM4 - Backlight on LVDS connector: J6 */
+#define GP_BACKLIGHT_LVDS	IMX_GPIO_NR(1, 18)
+	IOMUX_PAD_CTRL(SD1_CMD__GPIO1_IO18, WEAK_PULLDN),
+
+	/* reg_usbotg_vbus */
+#define GP_REG_USBOTG		IMX_GPIO_NR(3, 22)
+	IOMUX_PAD_CTRL(EIM_D22__GPIO3_IO22, WEAK_PULLDN),
+
+	/* reg_wlan_en */
+#define GP_REG_WLAN_EN		IMX_GPIO_NR(6, 15)
+	IOMUX_PAD_CTRL(NANDF_CS2__GPIO6_IO15, WEAK_PULLDN),
+
+	/* UART1 */
+	IOMUX_PAD_CTRL(SD3_DAT6__UART1_RX_DATA, UART_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DAT7__UART1_TX_DATA, UART_PAD_CTRL),
+
+	/* UART2 */
+	IOMUX_PAD_CTRL(EIM_D26__UART2_TX_DATA, UART_PAD_CTRL),
+	IOMUX_PAD_CTRL(EIM_D27__UART2_RX_DATA, UART_PAD_CTRL),
+
+	/* UART3 for wl1271 */
+	IOMUX_PAD_CTRL(EIM_D24__UART3_TX_DATA, UART_PAD_CTRL),
+	IOMUX_PAD_CTRL(EIM_D25__UART3_RX_DATA, UART_PAD_CTRL),
+	IOMUX_PAD_CTRL(EIM_D23__UART3_CTS_B, UART_PAD_CTRL),
+	IOMUX_PAD_CTRL(EIM_D31__UART3_RTS_B, UART_PAD_CTRL),
+
+	/* UART4 - J27 pins 2, 4 */
+	IOMUX_PAD_CTRL(KEY_COL0__UART4_TX_DATA, UART_PAD_CTRL),
+	IOMUX_PAD_CTRL(KEY_ROW0__UART4_RX_DATA, UART_PAD_CTRL),
+
+	/* UART5 - J32 pins 2, 4 */
+	IOMUX_PAD_CTRL(KEY_COL1__UART5_TX_DATA, UART_PAD_CTRL),
+	IOMUX_PAD_CTRL(KEY_ROW1__UART5_RX_DATA, UART_PAD_CTRL),
+
+	/* USBH1 */
+#define GP_USBH1_HUB_RESET	IMX_GPIO_NR(7, 12)
+	IOMUX_PAD_CTRL(GPIO_17__GPIO7_IO12, WEAK_PULLDN),
+
+	/* USBOTG */
+	IOMUX_PAD_CTRL(GPIO_1__USB_OTG_ID, WEAK_PULLUP),
+	IOMUX_PAD_CTRL(KEY_COL4__USB_OTG_OC, WEAK_PULLUP),
+
+	/* USDHC2 - TiWi wl1271 */
+	IOMUX_PAD_CTRL(SD2_CLK__SD2_CLK, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_CMD__SD2_CMD, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_DAT0__SD2_DATA0, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_DAT1__SD2_DATA1, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_DAT2__SD2_DATA2, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL),
+//	IOMUX_PAD_CTRL(SD1_CLK__OSC32K_32K_OUT, OUTPUT_40OHM),	/* slow clock */
+
+	/* USDHC3 - sdcard */
+	IOMUX_PAD_CTRL(SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
+#define GP_USDHC3_CD		IMX_GPIO_NR(7, 0)
+	IOMUX_PAD_CTRL(SD3_DAT5__GPIO7_IO00, WEAK_PULLUP),
+
+	/* USDHC4 - sdcard */
+	IOMUX_PAD_CTRL(SD4_CLK__SD4_CLK, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD4_CMD__SD4_CMD, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD4_DAT0__SD4_DATA0, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD4_DAT1__SD4_DATA1, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD4_DAT2__SD4_DATA2, USDHC_PAD_CTRL),
+	IOMUX_PAD_CTRL(SD4_DAT3__SD4_DATA3, USDHC_PAD_CTRL),
+#define GP_USDHC4_CD		IMX_GPIO_NR(2, 6)
+	IOMUX_PAD_CTRL(NANDF_D6__GPIO2_IO06, WEAK_PULLUP),
+
+	/* wl1271 */
+#define GPIRQ_WL1271_WL		IMX_GPIO_NR(6, 14)
+	IOMUX_PAD_CTRL(NANDF_CS1__GPIO6_IO14, WEAK_PULLDN),
+};
+
+static const struct i2c_pads_info i2c_pads[] = {
+	/* I2C1, SGTL5000 */
+	I2C_PADS_INFO_ENTRY(I2C1, EIM_D21, 3, 21, EIM_D28, 3, 28, I2C_PAD_CTRL),
+	/* I2C2 Camera, MIPI */
+	I2C_PADS_INFO_ENTRY(I2C2, KEY_COL3, 4, 12, KEY_ROW3, 4, 13, I2C_PAD_CTRL),
+	/* I2C3, J15 - RGB connector */
+	I2C_PADS_INFO_ENTRY(I2C3, GPIO_5, 1, 05, GPIO_16, 7, 11, I2C_PAD_CTRL),
+};
+#define I2C_BUS_CNT	3
+
+#ifdef CONFIG_USB_EHCI_MX6
+int board_ehci_hcd_init(int port)
+{
+	if (port) {
+		/* Reset USB hub */
+		gpio_direction_output(GP_USBH1_HUB_RESET, 0);
+		mdelay(2);
+		gpio_set_value(GP_USBH1_HUB_RESET, 1);
+	}
+	return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+	if (port)
+		return 0;
+	gpio_set_value(GP_REG_USBOTG, on);
+	return 0;
+}
+
+#endif
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg board_usdhc_cfg[] = {
+	{.esdhc_base = USDHC3_BASE_ADDR, .bus_width = 4,
+			.gp_cd = GP_USDHC3_CD},
+	{.esdhc_base = USDHC4_BASE_ADDR, .bus_width = 4,
+			.gp_cd = GP_USDHC4_CD},
+};
+#endif
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+	return (bus == 0 && cs == 0) ? GP_ECSPI1_NOR_CS : (cs >> 8) ? (cs >> 8) : -1;
+}
+
+#ifdef CONFIG_CMD_FBPANEL
+void board_enable_lvds(const struct display_info_t *di, int enable)
+{
+	gpio_set_value(GP_BACKLIGHT_TPS, enable);
+	gpio_set_value(GP_BACKLIGHT_LVDS, enable);
+}
+
+static const struct display_info_t displays[] = {
+	/* lvds */
+	VD_AUO_B101EW05(LVDS, fbp_detect_i2c, 2, 0x50),
+	VD_WXGA_J(LVDS, NULL, 0, 0),
+	/* hdmi */
+	VD_1280_720M_60(HDMI, fbp_detect_i2c, (GP_I2C3_EDID << 8 ) | 2, 0x3a),
+	VD_1920_1080M_60(HDMI, NULL, (GP_I2C3_EDID << 8 ) | 2, 0x3a),
+	VD_1024_768M_60(HDMI, NULL, (GP_I2C3_EDID << 8 ) | 2, 0x3a),
+};
+#define display_cnt	ARRAY_SIZE(displays)
+#else
+#define displays	NULL
+#define display_cnt	0
+#endif
+
+static const unsigned short gpios_out_low[] = {
+	/* Disable wl1271 */
+	GP_BT_RFKILL_RESET,
+	GP_RGMII_PHY_RESET,
+	GP_J34_DRY1,
+	GP_J34_DRY2,
+	GP_TDA7491P_GAIN0,
+	GP_TDA7491P_GAIN1,
+	GP_TDA7491P_STBY,
+	GP_TDA7491P_MUTE,
+	GP_OV5642_RESET,
+	GP_I2C3_EDID,
+	GP_POWER_OFF,
+	GP_BACKLIGHT_TPS,
+	GP_BACKLIGHT_LVDS,
+	GP_REG_USBOTG,
+	GP_REG_WLAN_EN,
+	GP_USBH1_HUB_RESET,
+};
+
+static const unsigned short gpios_out_high[] = {
+	GP_ECSPI1_NOR_CS,
+	GP_ECSPI2_CS1,
+	GP_FLEXCAN_STANDBY,
+	GP_LED_RED,
+	GP_LED_GREEN,
+	GP_LED_AMBER,
+	GP_OV5642_POWER_DOWN,
+};
+
+static const unsigned short gpios_in[] = {
+	GPIRQ_ENET_PHY,
+	GP_TEMP_ALARM,
+	GP_FAN_FAIL,
+	GP_AC_FAIL,
+	GP_J5_PIN33,
+	GP_J34_PIN6,
+	GP_J34_PIN8,
+	GP_ON_OFF,
+	GP_TP_R201,
+	GPIRQ_RTC_ISL1208,
+	GPIRQ_MIC_DET,
+	GP_USDHC3_CD,
+	GP_USDHC4_CD,
+	GPIRQ_WL1271_WL,
+};
+
+int board_early_init_f(void)
+{
+	set_gpios_in(gpios_in, ARRAY_SIZE(gpios_in));
+	set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
+	set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
+	SETUP_IOMUX_PADS(init_pads);
+	return 0;
+}
+
+void board_poweroff(void)
+{
+	gpio_set_value(GP_POWER_OFF, 1);
+	mdelay(500);
+}
+
+int board_init(void)
+{
+	common_board_init(i2c_pads, I2C_BUS_CNT, IOMUXC_GPR1_OTG_ID_GPIO1,
+			displays, display_cnt, 0);
+	return 0;
+}
+
+const struct button_key board_buttons[] = {
+	{"power",	GP_ON_OFF,	'P', 1},
+	{NULL, 0, 0, 0},
+};
+
+#ifdef CONFIG_CMD_BMODE
+const struct boot_mode board_boot_modes[] = {
+	/* 4 bit bus width */
+	{"mmc0",	MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
+	{"mmc1",	MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
+	{NULL,		0},
+};
+#endif
+
+static int _do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	board_poweroff();
+	return 0;
+}
+
+U_BOOT_CMD(
+	poweroff, 70, 0, _do_poweroff,
+	"power down board",
+	""
+);
diff --git a/board/boundary/s/s_q2g.cfg b/board/boundary/s/s_q2g.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..6dc24f07c4512f2b8e02ec5767ed9d166858d797
--- /dev/null
+++ b/board/boundary/s/s_q2g.cfg
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2013 Boundary Devices
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      spi
+
+#define __ASSEMBLY__
+#include <config.h>
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+/* NC YET */
+#define MX6_MMDC_P0_MPDGCTRL0_VAL	0x42740304
+#define MX6_MMDC_P0_MPDGCTRL1_VAL	0x026e0265
+#define MX6_MMDC_P1_MPDGCTRL0_VAL	0x02750306
+#define MX6_MMDC_P1_MPDGCTRL1_VAL	0x02720244
+#define MX6_MMDC_P0_MPRDDLCTL_VAL	0x463d4041
+#define MX6_MMDC_P1_MPRDDLCTL_VAL	0x42413c47
+#define MX6_MMDC_P0_MPWRDLCTL_VAL	0x37414441
+#define MX6_MMDC_P1_MPWRDLCTL_VAL	0x4633473b
+#define MX6_MMDC_P0_MPWLDECTRL0_VAL	0x0025001f
+#define MX6_MMDC_P0_MPWLDECTRL1_VAL	0x00290027
+#define MX6_MMDC_P1_MPWLDECTRL0_VAL	0x001f002b
+#define MX6_MMDC_P1_MPWLDECTRL1_VAL	0x000f0029
+#define WALAT	1
+
+#include "../common/mx6/ddr-setup.cfg"
+#define RANK 0
+#define BUS_WIDTH 64
+/* D2516EC4BXGGB-U */
+#include "../common/mx6/1066mhz_256mx16.cfg"
+#include "../common/mx6/clocks.cfg"
diff --git a/configs/s_defconfig b/configs/s_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..b1f9a71e886f8b9b55aa80444818bffeb6a167b2
--- /dev/null
+++ b/configs/s_defconfig
@@ -0,0 +1,72 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_TARGET_S=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/s/s_q2g.cfg,MX6Q,DDR_MB=2048,DEFCONFIG=\"s\""
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x12000000
+CONFIG_FASTBOOT_BUF_SIZE=0x26000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_FSL_ESDHC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_NETDEVICES=y
+CONFIG_FEC_MXC=y
+CONFIG_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Boundary"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_ETHER=y
+CONFIG_USB_ETH_CDC=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_SMSC95XX=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_OF_LIBFDT=y
diff --git a/include/configs/s.h b/include/configs/s.h
new file mode 100644
index 0000000000000000000000000000000000000000..02c426995c22405858646ccfeb2e209064f232df
--- /dev/null
+++ b/include/configs/s.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Boundary Devices S board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+#define CONFIG_MACH_TYPE	3769
+
+#define CONFIG_VIDEO_LOGO
+
+#define CONFIG_IMX_HDMI
+#define CONFIG_MXC_UART_BASE		UART4_BASE
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define BD_CONSOLE "ttymxc3"
+#define BD_I2C_MASK	7
+
+#include "boundary.h"
+#define CONFIG_EXTRA_ENV_SETTINGS BD_BOUNDARY_ENV_SETTINGS \
+
+#endif	       /* __CONFIG_H */