diff --git a/Makefile b/Makefile
index 394ed096f053740e398e4c86aa6f3107170aafdf..605003e3553f4a7851890bc709f87227a1f8d2cc 100644
--- a/Makefile
+++ b/Makefile
@@ -736,8 +736,12 @@ ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
ifeq ($(CONFIG_SPL_FSL_PBL),y)
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin
else
+ifneq ($(CONFIG_SECURE_BOOT), y)
+# For Secure Boot The Image needs to be signed and Header must also
+# be included. So The image has to be built explicitly
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl
endif
+endif
ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin
ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img
ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index e61d8e0fc2b3e3da10cfec92275ea4fb0da4907f..a70fb711c7bbbe579af1a148c4a43004e68cd710 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1052,6 +1052,17 @@ create_init_ram_area:
CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
+
+#elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_SECURE_BOOT)
+ /* create a temp mapping in AS = 1 for mapping CONFIG_SYS_MONITOR_BASE
+ * to L3 Address configured by PBL for ISBC code
+ */
+ create_tlb1_entry 15, \
+ 1, BOOKE_PAGESZ_1M, \
+ CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \
+ CONFIG_SYS_INIT_L3_ADDR & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \
+ 0, r6
+
#else
/*
* create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
diff --git a/arch/powerpc/cpu/mpc85xx/t1024_ids.c b/arch/powerpc/cpu/mpc85xx/t1024_ids.c
index 132689b26eb71be7cea93b74810eb7666bfb5338..8a1092ea655cf0bfd7a8780e723b56a04a70cdca 100644
--- a/arch/powerpc/cpu/mpc85xx/t1024_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/t1024_ids.c
@@ -51,11 +51,10 @@ int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
#ifdef CONFIG_SYS_DPAA_FMAN
struct liodn_id_table fman1_liodn_tbl[] = {
- SET_FMAN_RX_1G_LIODN(1, 0, 88),
+ SET_FMAN_RX_10G_TYPE2_LIODN(1, 0, 88),
SET_FMAN_RX_1G_LIODN(1, 1, 89),
SET_FMAN_RX_1G_LIODN(1, 2, 90),
SET_FMAN_RX_1G_LIODN(1, 3, 91),
- SET_FMAN_RX_10G_LIODN(1, 0, 94),
};
int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index 74c4c81887c2b66507aef51ea2d761dd2a056e71..7b43b282bb6f5014c6f13933777aeb56bcf5d993 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -214,8 +214,8 @@ static const struct serdes_config serdes3_cfg_tbl[] = {
{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
{5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
{6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}},
- {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
- {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}},
+ {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
+ {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
{9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
{10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
@@ -266,37 +266,30 @@ static const struct serdes_config serdes4_cfg_tbl[] = {
#elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
static const struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
- {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
- XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+ {1, {NONE, NONE, NONE, NONE,
XAUI_FM1_MAC10, XAUI_FM1_MAC10,
XAUI_FM1_MAC10, XAUI_FM1_MAC10} },
- {2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
- HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ {2, {NONE, NONE, NONE, NONE,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
- {4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
- HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ {4, {NONE, NONE, NONE, NONE,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
- {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
- SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ {27, {NONE, NONE, NONE, NONE,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
- {28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
- SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ {28, {NONE, NONE, NONE, NONE,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
- {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
- SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ {35, {NONE, NONE, NONE, NONE,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
- {36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
- SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ {36, {NONE, NONE, NONE, NONE,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
- {37, {NONE, NONE, QSGMII_FM1_B, NONE,
+ {37, {NONE, NONE, NONE, NONE,
NONE, NONE, QSGMII_FM1_A, NONE} },
- {38, {NONE, NONE, QSGMII_FM1_B, NONE,
+ {38, {NONE, NONE, NONE, NONE,
NONE, NONE, QSGMII_FM1_A, NONE} },
{}
};
@@ -363,45 +356,45 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{37, {NONE, NONE, QSGMII_FM2_B, NONE,
- NONE, QSGMII_FM1_A, NONE, NONE} },
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{38, {NONE, NONE, QSGMII_FM2_B, NONE,
- NONE, QSGMII_FM1_A, NONE, NONE} },
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, QSGMII_FM1_A, NONE, NONE} },
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, QSGMII_FM1_A, NONE, NONE} },
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, QSGMII_FM1_A, NONE, NONE} },
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, QSGMII_FM1_A, NONE, NONE} },
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, QSGMII_FM1_A, NONE, NONE} },
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
- NONE, QSGMII_FM1_A, NONE, NONE} },
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- NONE, NONE, NONE, NONE} },
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
- NONE, NONE, NONE, NONE} },
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- NONE, NONE, NONE, NONE} },
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- NONE, NONE, NONE, NONE} },
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- NONE, NONE, NONE, NONE} },
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
- NONE, NONE, NONE, NONE} },
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{55, {NONE, XFI_FM1_MAC10,
XFI_FM2_MAC10, NONE,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
@@ -424,51 +417,51 @@ static const struct serdes_config serdes3_cfg_tbl[] = {
{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
{5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
{6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
- {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
- {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
+ {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
+ {8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
{9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
{10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
- {11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ {11, {NONE, NONE, NONE, NONE,
PCIE2, PCIE2, PCIE2, PCIE2} },
- {12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ {12, {NONE, NONE, NONE, NONE,
PCIE2, PCIE2, PCIE2, PCIE2} },
{13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
PCIE2, PCIE2, PCIE2, PCIE2} },
{14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
PCIE2, PCIE2, PCIE2, PCIE2} },
- {15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ {15, {NONE, NONE, NONE, NONE,
SRIO1, SRIO1, SRIO1, SRIO1} },
- {16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ {16, {NONE, NONE, NONE, NONE,
SRIO1, SRIO1, SRIO1, SRIO1} },
- {17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ {17, {NONE, NONE, NONE, NONE,
SRIO1, SRIO1, SRIO1, SRIO1} },
{18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
SRIO1, SRIO1, SRIO1, SRIO1} },
{19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
SRIO1, SRIO1, SRIO1, SRIO1} },
{20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
- NONE, NONE, NONE, NONE} },
+ SRIO1, SRIO1, SRIO1, SRIO1} },
{}
};
static const struct serdes_config serdes4_cfg_tbl[] = {
/* SerDes 4 */
- {3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
- {4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
- {5, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
- {6, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
- {7, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
- {8, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
- {9, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
- {10, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
- {11, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
- {12, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
- {13, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
- {14, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
- {15, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
- {16, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
- {18, {AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA} },
+ {3, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} },
+ {4, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, PCIE4, PCIE4} },
+ {5, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
+ {6, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
+ {7, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
+ {8, {NONE, NONE, NONE, NONE, SRIO2, SRIO2, SRIO2, SRIO2} },
+ {9, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} },
+ {10, {NONE, NONE, NONE, NONE, PCIE4, PCIE4, SATA1, SATA2} },
+ {11, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} },
+ {12, {NONE, NONE, NONE, NONE, AURORA, AURORA, SATA1, SATA2} },
+ {13, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
+ {14, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
+ {15, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
+ {16, {NONE, NONE, NONE, NONE, AURORA, AURORA, SRIO2, SRIO2} },
+ {18, {NONE, NONE, NONE, NONE, AURORA, AURORA, AURORA, AURORA} },
{}
}
;
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 9d56bc17732dd547506536f2e9a6a784e03268a7..7a5487be884006ae0a5508af4a3c64b1b2aa9536 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -334,7 +334,7 @@
#elif defined(CONFIG_P1025)
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_LAWS 12
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
@@ -806,6 +806,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
+#define CONFIG_SYS_FSL_SFP_VER_3_0
#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\
defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index 811f0342935998a8fbce02e655b2d07eeb569a60..6206bee5d337b2766a3692032240b0129b5c5506 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -145,6 +145,12 @@ extern void fdt_fixup_liodn(void *blob);
FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) \
+/* enetNum is 0, 1, 2... so we + 8 for type-2 10g to get to HW Port ID */
+#define SET_FMAN_RX_10G_TYPE2_LIODN(fmNum, enetNum, liodn) \
+ SET_LIODN_ENTRY_1("fsl,fman-port-10g-rx", liodn, \
+ FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
+ CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) \
+
/*
* handle both old and new versioned SEC properties:
* "fsl,secX.Y" became "fsl,sec-vX.Y" during development
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index 8f794ef381253c6efee1bd96fe85c8083e30b93c..d57bb556927decb412a3ea271482997e012e0e1b 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -37,7 +37,9 @@
defined(CONFIG_T2080QDS) || \
defined(CONFIG_T2080RDB) || \
defined(CONFIG_T1040QDS) || \
+ defined(CONFIG_T104xD4QDS) || \
defined(CONFIG_T104xRDB) || \
+ defined(CONFIG_T104xD4RDB) || \
defined(CONFIG_PPC_T1023) || \
defined(CONFIG_PPC_T1024)
#define CONFIG_SYS_CPC_REINIT_F
@@ -46,6 +48,11 @@
#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
#endif
+#if defined(CONFIG_RAMBOOT_PBL)
+#undef CONFIG_SYS_INIT_L3_ADDR
+#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
+#endif
+
#if defined(CONFIG_C29XPCIE)
#define CONFIG_KEY_REVOCATION
#endif
@@ -68,6 +75,18 @@
#endif
#ifndef CONFIG_FIT_SIGNATURE
+/* If Boot Script is not on NOR and is required to be copied on RAM */
+#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
+#define CONFIG_BS_HDR_ADDR_RAM 0x00010000
+#define CONFIG_BS_HDR_ADDR_FLASH 0x00800000
+#define CONFIG_BS_HDR_SIZE 0x00002000
+#define CONFIG_BS_ADDR_RAM 0x00012000
+#define CONFIG_BS_ADDR_FLASH 0x00802000
+#define CONFIG_BS_SIZE 0x00001000
+
+#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
+#else
+
/* The bootscript header address is different for B4860 because the NOR
* mapping is different on B4 due to reduced NOR size.
*/
@@ -83,6 +102,8 @@
#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000
#endif
+#endif
+
#include <config_fsl_secboot.h>
#endif
diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c
index 8148e46efa6728cb9216a173bbc8f3a96c33dbfc..56e4f633483f054880332750e2ceb0198bcc8ae0 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -43,6 +43,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 1 */
/* *I*** - Covers boot page */
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+
+#if !defined(CONFIG_SECURE_BOOT)
/*
* *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
* SRAM is at 0xfff00000, it covered the 0xfffff000.
@@ -50,6 +52,19 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+ /*
+ * *I*G - L3SRAM. When L3 is used as 1M SRAM, in case of Secure Boot
+ * the physical address of the SRAM is at CONFIG_SYS_INIT_L3_ADDR,
+ * and virtual address is CONFIG_SYS_MONITOR_BASE
+ */
+
+ SET_TLB_ENTRY(1, CONFIG_SYS_MONITOR_BASE & 0xfff00000,
+ CONFIG_SYS_INIT_L3_ADDR & 0xfff00000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#endif
+
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS
index 745847cdbaa34802faffe39f64e2660db5ebd417..73b0553184e78a352f90ae00155aa995d96f3604 100644
--- a/board/freescale/corenet_ds/MAINTAINERS
+++ b/board/freescale/corenet_ds/MAINTAINERS
@@ -28,3 +28,10 @@ F: configs/P5040DS_NAND_defconfig
F: configs/P5040DS_SDCARD_defconfig
F: configs/P5040DS_SPIFLASH_defconfig
F: configs/P5040DS_SECURE_BOOT_defconfig
+
+CORENET_DS_SECURE_BOOT BOARD
+M: Aneesh Bansal <aneesh.bansal@freescale.com>
+S: Maintained
+F: configs/P3041DS_NAND_SECURE_BOOT_defconfig
+F: configs/P5020DS_NAND_SECURE_BOOT_defconfig
+F: configs/P5040DS_NAND_SECURE_BOOT_defconfig
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 3f47cfbb82aa3e9b2b547a31feaa0ea39d18f44b..61b7a91333faf1beb07f981822c8fd76325bf6a2 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -428,8 +428,13 @@ int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
+#if defined(CONFIG_P1020RDB_PD) || defined(CONFIG_P1020RDB_PC)
const char *soc_usb_compat = "fsl-usb2-dr";
- int err, usb1_off, usb2_off;
+ int usb_err, usb1_off, usb2_off;
+#endif
+#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
+ int err;
+#endif
ft_cpu_setup(blob, bd);
@@ -473,6 +478,7 @@ int ft_board_setup(void *blob, bd_t *bd)
}
#endif
+#if defined(CONFIG_P1020RDB_PD) || defined(CONFIG_P1020RDB_PC)
/* Delete USB2 node as it is muxed with eLBC */
usb1_off = fdt_node_offset_by_compatible(blob, -1,
soc_usb_compat);
@@ -488,11 +494,12 @@ int ft_board_setup(void *blob, bd_t *bd)
soc_usb_compat);
return usb2_off;
}
- err = fdt_del_node(blob, usb2_off);
- if (err < 0) {
+ usb_err = fdt_del_node(blob, usb2_off);
+ if (usb_err < 0) {
printf("WARNING: could not remove %s\n", soc_usb_compat);
- return err;
+ return usb_err;
}
+#endif
return 0;
}
diff --git a/board/freescale/t102xqds/t1024_pbi.cfg b/board/freescale/t102xqds/t1024_pbi.cfg
index 7b9e9b05f7000c3a3bd77a484ddd3e5777359d3a..98efca25a290b549ad37c8f4a1126c0c4b98547e 100644
--- a/board/freescale/t102xqds/t1024_pbi.cfg
+++ b/board/freescale/t102xqds/t1024_pbi.cfg
@@ -6,7 +6,7 @@
#Configure CPC1 as 256KB SRAM
09010100 00000000
09010104 fffc0007
-09010f00 08000000
+09010f00 081e000d
09010000 80000000
#Configure LAW for CPC1
09000cd0 00000000
diff --git a/board/freescale/t102xrdb/README b/board/freescale/t102xrdb/README
index 922450e3c7bdeac666ae5bcacfbd3448bb49ff16..7d3794a6d69139fbd3811e50d57ed2b8a453106c 100644
--- a/board/freescale/t102xrdb/README
+++ b/board/freescale/t102xrdb/README
@@ -70,6 +70,7 @@ Deep Sleep: yes no
I2C controller: 4 3
DDR: 64-bit 32-bit
IFC: 32-bit 28-bit
+Package: 23x23 19x19
T1024RDB board Overview
@@ -192,7 +193,7 @@ Software configurations and board settings
on T1024RDB:
set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
on T1023RDB:
- set SW1[1:8] = '00010110', SW2[1] = '0', SW3[4] = '0' for NOR boot
+ set SW1[1:8] = '00010111', SW2[1] = '1', SW3[4] = '0' for NOR boot
Switching between default bank0 and alternate bank4 on NOR flash
To change boot source to vbank4:
@@ -200,7 +201,7 @@ Software configurations and board settings
via software: run command 'cpld reset altbank' in u-boot.
via DIP-switch: set SW3[5:7] = '100'
on T1023RDB:
- via software: run command 'gpio vbank4' in u-boot.
+ via software: run command 'switch bank4' in u-boot.
via DIP-switch: set SW3[5:7] = '100'
To change boot source to vbank0:
@@ -208,7 +209,7 @@ Software configurations and board settings
via software: run command 'cpld reset' in u-boot.
via DIP-Switch: set SW3[5:7] = '000'
on T1023RDB:
- via software: run command 'gpio vbank0' in u-boot.
+ via software: run command 'switch bank0' in u-boot.
via DIP-switch: set SW3[5:7] = '000'
2. NAND Boot:
@@ -219,7 +220,7 @@ Software configurations and board settings
=> tftp 1000000 u-boot-with-spl-pbl.bin
=> nand erase 0 $filesize
=> nand write 1000000 0 $filesize
- set SW1[1:8] = '10001000', SW2[1] = '1', SW3[4] = '1' for NAND boot
+ set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
3. SPI Boot:
a. build PBL image for SPI boot
@@ -241,11 +242,14 @@ Software configurations and board settings
$ make
b. program u-boot-with-spl-pbl.bin to SD/MMC card
=> tftp 1000000 u-boot-with-spl-pbl.bin
- => mmc write 1000000 8 0x800
+ => mmc write 1000000 8 0x7f0
=> tftp 1000000 fsl_fman_ucode_t1024_xx.bin
=> mmc write 1000000 0x820 80
set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
+ SW3[3] = '1' for SD card(or 'switch sd' by software)
+ SW3[3] = '0' for eMMC (or 'switch emmc' by software)
+
2-stage NAND/SPI/SD boot loader
-------------------------------
@@ -292,7 +296,7 @@ Start End Definition Size
0x160000 0x17FFFF FMAN Ucode 128KB
-SD Card memory Map on T1024RDB
+SD Card memory Map on T102xRDB
----------------------------------------------------
Block #blocks Definition Size
0x008 2048 u-boot img 1MB
@@ -313,5 +317,5 @@ Start End Definition Size
0xa00000 0x3FFFFFF rootfs 54MB
-For more details, please refer to T1024RDB Reference Manual
+For more details, please refer to T1024RDB/T1023RDB User Guide
and Freescale QorIQ SDK Infocenter document.
diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c
index 1a3a996439646ef53e932b3139fe532abea9c0fc..9c581ff88e085395091ad9684933a1dee1235610 100644
--- a/board/freescale/t102xrdb/spl.c
+++ b/board/freescale/t102xrdb/spl.c
@@ -30,6 +30,30 @@ unsigned long get_board_ddr_clk(void)
return CONFIG_DDR_CLK_FREQ;
}
+#if defined(CONFIG_SPL_MMC_BOOT)
+#define GPIO1_SD_SEL 0x00020000
+int board_mmc_getcd(struct mmc *mmc)
+{
+ ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ u32 val = in_be32(&pgpio->gpdat);
+
+ /* GPIO1_14, 0: eMMC, 1: SD */
+ val &= GPIO1_SD_SEL;
+
+ return val ? -1 : 1;
+}
+
+int board_mmc_getwp(struct mmc *mmc)
+{
+ ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ u32 val = in_be32(&pgpio->gpdat);
+
+ val &= GPIO1_SD_SEL;
+
+ return val ? -1 : 0;
+}
+#endif
+
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;
diff --git a/board/freescale/t102xrdb/t1023_rcw.cfg b/board/freescale/t102xrdb/t1023_rcw.cfg
index fa781d61a5891363889abd69a16e46da4315ce08..1d11a2eed7f4636af3b0f1ed429c1898d389d6bd 100644
--- a/board/freescale/t102xrdb/t1023_rcw.cfg
+++ b/board/freescale/t102xrdb/t1023_rcw.cfg
@@ -4,5 +4,5 @@ aa55aa55 010e0100
#Core/DDR: 1400Mhz/1600MT/s with single source clock
0810000e 00000000 00000000 00000000
3b800003 00000012 e8104000 21000000
-00000000 00000000 00000000 00020800
+00000000 00000000 00000000 00022800
00000130 04020200 00000000 00000006
diff --git a/board/freescale/t102xrdb/t1024_pbi.cfg b/board/freescale/t102xrdb/t1024_pbi.cfg
index 7b9e9b05f7000c3a3bd77a484ddd3e5777359d3a..98efca25a290b549ad37c8f4a1126c0c4b98547e 100644
--- a/board/freescale/t102xrdb/t1024_pbi.cfg
+++ b/board/freescale/t102xrdb/t1024_pbi.cfg
@@ -6,7 +6,7 @@
#Configure CPC1 as 256KB SRAM
09010100 00000000
09010104 fffc0007
-09010f00 08000000
+09010f00 081e000d
09010000 80000000
#Configure LAW for CPC1
09000cd0 00000000
diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c
index f971976d73b3996a462dc9e9a89b5d265410aff2..fddd240f98a4c25ec55bd777535ecc1f044a7861 100644
--- a/board/freescale/t102xrdb/t102xrdb.c
+++ b/board/freescale/t102xrdb/t102xrdb.c
@@ -20,6 +20,9 @@
#include "t102xrdb.h"
#ifdef CONFIG_T1024RDB
#include "cpld.h"
+#elif defined(CONFIG_T1023RDB)
+#include <i2c.h>
+#include <mmc.h>
#endif
#include "../common/sleep.h"
@@ -27,13 +30,14 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_T1023RDB
enum {
- GPIO1_SD_SEL = 0x00020000, /* GPIO1_14, 0: EMMC, 1:SD/MMC */
+ GPIO1_SD_SEL = 0x00020000, /* GPIO1_14, 0: eMMC, 1:SD/MMC */
GPIO1_EMMC_SEL,
- GPIO1_VBANK0,
- GPIO1_VBANK4 = 0x00008000, /* GPIO1_16/20/22, 100:vBank4 */
- GPIO1_VBANK_MASK = 0x00008a00,
- GPIO1_DIR_OUTPUT = 0x00028a00,
- GPIO1_GET_VAL,
+ GPIO3_GET_VERSION, /* GPIO3_4/5, 00:RevB, 01: RevC */
+ GPIO3_BRD_VER_MASK = 0x0c000000,
+ GPIO3_OFFSET = 0x2000,
+ I2C_GET_BANK,
+ I2C_SET_BANK0,
+ I2C_SET_BANK4,
};
#endif
@@ -48,9 +52,11 @@ int checkboard(void)
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
printf("Board: %sRDB, ", cpu->name);
-#ifdef CONFIG_T1024RDB
+#if defined(CONFIG_T1024RDB)
printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
CPLD_READ(hw_ver), CPLD_READ(sw_ver));
+#elif defined(CONFIG_T1023RDB)
+ printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B');
#endif
printf("boot from ");
@@ -73,8 +79,7 @@ int checkboard(void)
#ifdef CONFIG_NAND
puts("NAND\n");
#else
- printf("NOR vBank%d\n", (t1023rdb_gpio_ctrl(GPIO1_GET_VAL) &
- GPIO1_VBANK4) >> 15 ? 4 : 0);
+ printf("NOR vBank%d\n", t1023rdb_ctrl(I2C_GET_BANK));
#endif
#endif
@@ -196,64 +201,126 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_board_enet(blob);
#endif
+#ifdef CONFIG_T1023RDB
+ if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0)
+ fdt_enable_nor(blob);
+#endif
+
return 0;
}
-
#ifdef CONFIG_T1023RDB
-static u32 t1023rdb_gpio_ctrl(u32 ctrl_type)
+/* Enable NOR flash for RevC */
+static void fdt_enable_nor(void *blob)
{
- ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
- u32 gpioval;
+ int nodeoff = fdt_node_offset_by_compatible(blob, 0, "cfi-flash");
+
+ if (nodeoff >= 0)
+ fdt_status_okay(blob, nodeoff);
+ else
+ printf("WARNING unable to set status for NOR\n");
+}
- setbits_be32(&pgpio->gpdir, GPIO1_DIR_OUTPUT);
- gpioval = in_be32(&pgpio->gpdat);
+int board_mmc_getcd(struct mmc *mmc)
+{
+ ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ u32 val = in_be32(&pgpio->gpdat);
+
+ /* GPIO1_14, 0: eMMC, 1: SD/MMC */
+ val &= GPIO1_SD_SEL;
+
+ return val ? -1 : 1;
+}
+
+int board_mmc_getwp(struct mmc *mmc)
+{
+ ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ u32 val = in_be32(&pgpio->gpdat);
+
+ val &= GPIO1_SD_SEL;
+
+ return val ? -1 : 0;
+}
+
+static u32 t1023rdb_ctrl(u32 ctrl_type)
+{
+ ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 val, orig_bus = i2c_get_bus_num();
+ u8 tmp;
switch (ctrl_type) {
case GPIO1_SD_SEL:
- gpioval |= GPIO1_SD_SEL;
+ val = in_be32(&pgpio->gpdat);
+ val |= GPIO1_SD_SEL;
+ out_be32(&pgpio->gpdat, val);
+ setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
break;
case GPIO1_EMMC_SEL:
- gpioval &= ~GPIO1_SD_SEL;
+ val = in_be32(&pgpio->gpdat);
+ val &= ~GPIO1_SD_SEL;
+ out_be32(&pgpio->gpdat, val);
+ setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
break;
- case GPIO1_VBANK0:
- gpioval &= ~GPIO1_VBANK_MASK;
+ case GPIO3_GET_VERSION:
+ pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
+ + GPIO3_OFFSET);
+ val = in_be32(&pgpio->gpdat);
+ val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
+ if (val == 0x3) /* GPIO3_4/5 not used on RevB */
+ val = 0;
+ return val;
+ case I2C_GET_BANK:
+ i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
+ i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1);
+ tmp &= 0x7;
+ tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
+ i2c_set_bus_num(orig_bus);
+ return tmp;
+ case I2C_SET_BANK0:
+ i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
+ tmp = 0x0;
+ i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
+ tmp = 0xf8;
+ i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
+ /* asserting HRESET_REQ */
+ out_be32(&gur->rstcr, 0x2);
break;
- case GPIO1_VBANK4:
- gpioval &= ~GPIO1_VBANK_MASK;
- gpioval |= GPIO1_VBANK4;
+ case I2C_SET_BANK4:
+ i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
+ tmp = 0x1;
+ i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
+ tmp = 0xf8;
+ i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
+ out_be32(&gur->rstcr, 0x2);
break;
- case GPIO1_GET_VAL:
- return gpioval;
default:
break;
}
- out_be32(&pgpio->gpdat, gpioval);
-
return 0;
}
-static int gpio_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
+static int switch_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
if (argc < 2)
return CMD_RET_USAGE;
- if (!strcmp(argv[1], "vbank0"))
- t1023rdb_gpio_ctrl(GPIO1_VBANK0);
- else if (!strcmp(argv[1], "vbank4"))
- t1023rdb_gpio_ctrl(GPIO1_VBANK4);
+ if (!strcmp(argv[1], "bank0"))
+ t1023rdb_ctrl(I2C_SET_BANK0);
+ else if (!strcmp(argv[1], "bank4") || !strcmp(argv[1], "altbank"))
+ t1023rdb_ctrl(I2C_SET_BANK4);
else if (!strcmp(argv[1], "sd"))
- t1023rdb_gpio_ctrl(GPIO1_SD_SEL);
- else if (!strcmp(argv[1], "EMMC"))
- t1023rdb_gpio_ctrl(GPIO1_EMMC_SEL);
+ t1023rdb_ctrl(GPIO1_SD_SEL);
+ else if (!strcmp(argv[1], "emmc"))
+ t1023rdb_ctrl(GPIO1_EMMC_SEL);
else
return CMD_RET_USAGE;
return 0;
}
U_BOOT_CMD(
- gpio, 2, 0, gpio_cmd,
- "for vbank0/vbank4/SD/eMMC switch control in runtime",
- "command (e.g. gpio vbank4)"
+ switch, 2, 0, switch_cmd,
+ "for bank0/bank4/sd/emmc switch control in runtime",
+ "command (e.g. switch bank4)"
);
#endif
diff --git a/board/freescale/t102xrdb/t102xrdb.h b/board/freescale/t102xrdb/t102xrdb.h
index 3f5d85aa822ef501e0ed16e9488fc71a55196058..ae5c60f86e60502a96d5cd5daac2c647848ec389 100644
--- a/board/freescale/t102xrdb/t102xrdb.h
+++ b/board/freescale/t102xrdb/t102xrdb.h
@@ -10,6 +10,7 @@
void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, bd_t *bd);
#ifdef CONFIG_T1023RDB
-static u32 t1023rdb_gpio_ctrl(u32 ctrl_type);
+static u32 t1023rdb_ctrl(u32 ctrl_type);
+static void fdt_enable_nor(void *blob);
#endif
#endif
diff --git a/board/freescale/t1040qds/t1040_pbi.cfg b/board/freescale/t1040qds/t1040_pbi.cfg
index 10b1a6d179f687ca46e66a37516de02ef3546ad2..121b005baf0412710772a95bf07c558ae2741f9c 100644
--- a/board/freescale/t1040qds/t1040_pbi.cfg
+++ b/board/freescale/t1040qds/t1040_pbi.cfg
@@ -6,7 +6,7 @@
#Configure CPC1 as 256KB SRAM
09010100 00000000
09010104 fffc0007
-09010f00 08000000
+09010f00 081e000d
09010000 80000000
#Configure LAW for CPC1
09000cf0 00000000
diff --git a/board/freescale/t104xrdb/MAINTAINERS b/board/freescale/t104xrdb/MAINTAINERS
index 13d9be9da8f808096cc76db409c856360e1d752c..7597800252d0ea5f060d8f5aec2bcc763e17770d 100644
--- a/board/freescale/t104xrdb/MAINTAINERS
+++ b/board/freescale/t104xrdb/MAINTAINERS
@@ -6,7 +6,13 @@ F: include/configs/T104xRDB.h
F: configs/T1040RDB_defconfig
F: configs/T1040RDB_NAND_defconfig
F: configs/T1040RDB_SPIFLASH_defconfig
+F: configs/T1040D4RDB_defconfig
+F: configs/T1040D4RDB_NAND_defconfig
+F: configs/T1040D4RDB_SPIFLASH_defconfig
F: configs/T1042RDB_defconfig
+F: configs/T1042D4RDB_defconfig
+F: configs/T1042D4RDB_NAND_defconfig
+F: configs/T1042D4RDB_SPIFLASH_defconfig
F: configs/T1042RDB_PI_defconfig
F: configs/T1042RDB_PI_NAND_defconfig
F: configs/T1042RDB_PI_SPIFLASH_defconfig
@@ -15,10 +21,14 @@ T1040RDB_SDCARD BOARD
#M: -
S: Maintained
F: configs/T1040RDB_SDCARD_defconfig
+F: configs/T1040D4RDB_SDCARD_defconfig
+F: configs/T1042D4RDB_SDCARD_defconfig
F: configs/T1042RDB_PI_SDCARD_defconfig
T1040RDB_SECURE_BOOT BOARD
M: Aneesh Bansal <aneesh.bansal@freescale.com>
S: Maintained
F: configs/T1040RDB_SECURE_BOOT_defconfig
+F: configs/T1040D4RDB_SECURE_BOOT_defconfig
F: configs/T1042RDB_SECURE_BOOT_defconfig
+F: configs/T1042D4RDB_SECURE_BOOT_defconfig
diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README
index ac95b5e5094da83c54b797b945f4e98784bbcf8e..b9d221200060fd0c42e044d6f15b5cdad7a89f44 100644
--- a/board/freescale/t104xrdb/README
+++ b/board/freescale/t104xrdb/README
@@ -12,6 +12,17 @@ The T1042RDB_PI is a Freescale reference board that hosts the T1042 SoC.
(a personality of T1040 SoC). The board is similar to T1040RDB but is
designed specially with low power features targeted for Printing Image Market.
+The T1040D4RDB is a Freescale reference board that hosts the T1040 SoC.
+The board is re-designed T1040RDB board with following changes :
+ - Support of DDR4 memory and some enhancements
+
+The T1042D4RDB is a Freescale reference board that hosts the T1042 SoC.
+The board is re-designed T1040RDB board with following changes :
+ - Support of DDR4 memory
+ - Support for 0x86 serdes protocol which can support following interfaces
+ - 2 RGMII's on DTSEC4, DTSEC5
+ - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
+
Basic difference's among T1040RDB, T1042RDB_PI, T1042RDB
-------------------------------------------------------------------------
Board Si Protocol Targeted Market
@@ -19,6 +30,8 @@ Board Si Protocol Targeted Market
T1040RDB T1040 0x66 Networking
T1040RDB T1042 0x86 Networking
T1042RDB_PI T1042 0x06 Printing & Imaging
+T1040D4RDB T1040 0x66 Networking
+T1042D4RDB T1042 0x86 Networking
T1040 SoC Overview
@@ -70,7 +83,6 @@ The T1040/T1042 SoC includes the following function and features:
T1040 SoC Personalities
-------------------------
-
T1022 Personality:
T1022 is a reduced personality of T1040 with less core/clusters.
@@ -268,8 +280,13 @@ SPI Flash memory Map on T104xRDB
Please note QE Firmware is only valid for T1040RDB
-Switch Settings: (ON is 0, OFF is 1)
-===============
+Switch Settings for T104xRDB boards: (ON is 0, OFF is 1)
+==========================================================
+NOR boot SW setting:
+SW1: 00010011
+SW2: 10111011
+SW3: 11100001
+
NAND boot SW setting:
SW1: 10001000
SW2: 00111011
@@ -284,3 +301,67 @@ SD boot SW setting:
SW1: 00100000
SW2: 00111011
SW3: 11100001
+
+Switch Settings for T104xD4RDB boards: (ON is 0, OFF is 1)
+=============================================================
+NOR boot SW setting:
+SW1: 00010011
+SW2: 10111001
+SW3: 11100001
+
+NAND boot SW setting:
+SW1: 10001000
+SW2: 00111001
+SW3: 11110001
+
+SPI boot SW setting:
+SW1: 00100010
+SW2: 10111001
+SW3: 11100001
+
+SD boot SW setting:
+SW1: 00100000
+SW2: 00111001
+SW3: 11100001
+
+PBL-based image generation
+==========================
+Changes only the required register bit in in PBI commands.
+
+Provides reference code which might needs some
+modification as per requirement.
+example:
+By default PBI_SRC=14 (which is for IFC-NAND/NOR) in rcw.cfg file
+which needs to be changed for SPI and SD.
+
+For SD-boot
+==============
+1. Set RCW[192:195], PBI_SRC bits as 6 in RCW file (t1040d4_rcw.cfg type files)
+
+example:
+ RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg
+
+Change
+66000002 40000002 ec027000 01000000
+to
+66000002 40000002 6c027000 01000000
+
+2. SD does not support flush so remove flush from pbl, make changes in
+ tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000
+ with 0x091380c0
+
+For SPI-boot
+==============
+1. Set RCW[192:195], PBI_SRC bits as 5 in RCW file (t1040d4_rcw.cfg type files)
+
+example:
+ RCW file: board/freescale/t104xrdb/t1040d4_rcw.cfg
+
+Change
+66000002 40000002 ec027000 01000000
+to
+66000002 40000002 5c027000 01000000
+
+2. SPI does not support flush so remove flush from pbl, make changes in
+ tools/pblimage.c file, Update value of pbl_end_cmd[0] = 0x09138000
+ with 0x091380c0
diff --git a/board/freescale/t104xrdb/cpld.c b/board/freescale/t104xrdb/cpld.c
index df0e348d4afd798547ba14e24d50206d0842571f..0ce4e470a71105652554ab8ae7b341c3c9b562eb 100644
--- a/board/freescale/t104xrdb/cpld.c
+++ b/board/freescale/t104xrdb/cpld.c
@@ -69,7 +69,11 @@ static void cpld_dump_regs(void)
printf("int_status = 0x%02x\n", CPLD_READ(int_status));
printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status));
printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status));
+#if defined(CONFIG_T104XD4RDB)
+ printf("int_mask = 0x%02x\n", CPLD_READ(int_mask));
+#else
printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status));
+#endif
printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status));
printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status));
printf("boot_override = 0x%02x\n", CPLD_READ(boot_override));
diff --git a/board/freescale/t104xrdb/cpld.h b/board/freescale/t104xrdb/cpld.h
index 0da9a0159ba5d5bfd158b9fb0a19542cb9dd666e..2fb4105275e88220d4090927c5da365bf386dac5 100644
--- a/board/freescale/t104xrdb/cpld.h
+++ b/board/freescale/t104xrdb/cpld.h
@@ -21,7 +21,11 @@ struct cpld_data {
u8 int_status; /* 0x12 - Interrupt status Register */
u8 flash_ctl_status; /* 0x13 - Flash control and status register */
u8 fan_ctl_status; /* 0x14 - Fan control and status register */
+#if defined(CONFIG_T104XD4RDB)
+ u8 int_mask; /* 0x15 - Interrupt mask Register */
+#else
u8 led_ctl_status; /* 0x15 - LED control and status register */
+#endif
u8 sfp_ctl_status; /* 0x16 - SFP control and status register */
u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/
u8 boot_override; /* 0x18 - Boot override register */
@@ -38,3 +42,5 @@ void cpld_write(unsigned int reg, u8 value);
#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
#define CPLD_WRITE(reg, value)\
cpld_write(offsetof(struct cpld_data, reg), value)
+#define MISC_CTL_SG_SEL 0x80
+#define MISC_CTL_AURORA_SEL 0x02
diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c
index e1148e568e8ee66a9ae36adf0764083a81621a84..cf79d2ddb2d462b7051ee473cbfc5909952f22e7 100644
--- a/board/freescale/t104xrdb/ddr.c
+++ b/board/freescale/t104xrdb/ddr.c
@@ -75,7 +75,11 @@ found:
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
*/
+#ifdef CONFIG_SYS_FSL_DDR4
+ popts->half_strength_driver_enable = 1;
+#else
popts->half_strength_driver_enable = 0;
+#endif
/*
* Write leveling override
*/
@@ -91,8 +95,14 @@ found:
popts->zq_en = 1;
/* DHC_EN =1, ODT = 75 Ohm */
+#ifdef CONFIG_SYS_FSL_DDR4
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_120OHM);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_120OHM) |
+ DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
+#else
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+#endif
}
#if defined(CONFIG_DEEP_SLEEP)
diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h
index ab1c32d10e791ab0a8f4d56f927b73d6215d8ed8..b9c02f7fe0fd9b402d44b9604e6f4821568eb0a7 100644
--- a/board/freescale/t104xrdb/ddr.h
+++ b/board/freescale/t104xrdb/ddr.h
@@ -28,6 +28,9 @@ static const struct board_specific_parameters udimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl
* ranks| mhz| GB |adjst| start | ctl2
*/
+#ifdef CONFIG_SYS_FSL_DDR4
+ {2, 1600, 4, 4, 6, 0x07090A0c, 0x0e0f100a},
+#elif defined(CONFIG_SYS_FSL_DDR3)
{2, 833, 4, 4, 6, 0x06060607, 0x08080807},
{2, 833, 0, 4, 6, 0x06060607, 0x08080807},
{2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09},
@@ -40,10 +43,14 @@ static const struct board_specific_parameters udimm0[] = {
{1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09},
{1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A},
{1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A},
+#else
+#error DDR type not defined
+#endif
{}
};
+#endif
+
static const struct board_specific_parameters *udimms[] = {
udimm0,
};
-#endif
diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c
index 7581a4cdd44b95a685720a3c052064116742ba7b..71d0457d43210db7ff5d4979a40284f6ec85ca01 100644
--- a/board/freescale/t104xrdb/eth.c
+++ b/board/freescale/t104xrdb/eth.c
@@ -43,9 +43,11 @@ int board_eth_init(bd_t *bis)
int idx = i - FM1_DTSEC1;
switch (fm_info_get_enet_if(i)) {
-#ifdef CONFIG_T1040RDB
+#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB)
case PHY_INTERFACE_MODE_SGMII:
- /* T1040RDB only supports SGMII on DTSEC3 */
+ /* T1040RDB & T1040D4RDB only supports SGMII on
+ * DTSEC3
+ */
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_SGMII1_PHY_ADDR);
break;
@@ -59,6 +61,20 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_SGMII1_PHY_ADDR);
break;
+#endif
+#ifdef CONFIG_T1042D4RDB
+ case PHY_INTERFACE_MODE_SGMII:
+ /* T1042D4RDB supports SGMII on DTSEC1, DTSEC2
+ * & DTSEC3
+ */
+ if (FM1_DTSEC1 == i)
+ phy_addr = CONFIG_SYS_SGMII1_PHY_ADDR;
+ if (FM1_DTSEC2 == i)
+ phy_addr = CONFIG_SYS_SGMII2_PHY_ADDR;
+ if (FM1_DTSEC3 == i)
+ phy_addr = CONFIG_SYS_SGMII3_PHY_ADDR;
+ fm_info_set_phy_address(i, phy_addr);
+ break;
#endif
case PHY_INTERFACE_MODE_RGMII:
if (FM1_DTSEC4 == i)
diff --git a/board/freescale/t104xrdb/t1040d4_rcw.cfg b/board/freescale/t104xrdb/t1040d4_rcw.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..c1034b3dfa3b0e392aeb76a4a5e43518ba6222e9
--- /dev/null
+++ b/board/freescale/t104xrdb/t1040d4_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x66
+0c18000e 0e000000 00000000 00000000
+66000002 40000002 ec027000 01000000
+00000000 00000000 00000000 00030810
+00000000 0342580f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t1042d4_rcw.cfg b/board/freescale/t104xrdb/t1042d4_rcw.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..9e0ee2795f87ef5601f04ef2fe01af4865e0e779
--- /dev/null
+++ b/board/freescale/t104xrdb/t1042d4_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x86
+0c18000e 0e000000 00000000 00000000
+86000002 40000002 ec027000 01000000
+00000000 00000000 00000000 00030810
+00000000 0342500f 00000000 00000000
diff --git a/board/freescale/t104xrdb/t104x_pbi.cfg b/board/freescale/t104xrdb/t104x_pbi.cfg
index b83b9b7a4593bc8f1f7a2da86a56a52c786a568b..51945b4748947525ceeec1c6999acac9bcf8e4d2 100644
--- a/board/freescale/t104xrdb/t104x_pbi.cfg
+++ b/board/freescale/t104xrdb/t104x_pbi.cfg
@@ -16,7 +16,7 @@
#Configure CPC1 as 256KB SRAM
09010100 00000000
09010104 fffc0007
-09010f00 08000000
+09010f00 081e000d
09010000 80000000
#Configure LAW for CPC1
09000cd0 00000000
diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c
index 9cd5e157c483bac3d00673f2931c22b4b76a0de3..d982dfc872c4c7e9fc55406964c0b640f82a21dd 100644
--- a/board/freescale/t104xrdb/t104xrdb.c
+++ b/board/freescale/t104xrdb/t104xrdb.c
@@ -28,17 +28,18 @@ int checkboard(void)
struct cpu_type *cpu = gd->arch.cpu;
u8 sw;
+#ifdef CONFIG_T104XD4RDB
+ printf("Board: %sD4RDB\n", cpu->name);
+#else
printf("Board: %sRDB\n", cpu->name);
+#endif
printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
CPLD_READ(hw_ver), CPLD_READ(sw_ver));
sw = CPLD_READ(flash_ctl_status);
sw = ((sw & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
- if (sw <= 7)
- printf("vBank: %d\n", sw);
- else
- printf("Unsupported Bank=%x\n", sw);
+ printf("vBank: %d\n", sw);
return 0;
}
@@ -91,6 +92,34 @@ int board_early_init_r(void)
int misc_init_r(void)
{
+ ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_s1;
+
+ srds_s1 = in_be32(&gur->rcwsr[4]) >> 24;
+
+ printf("SERDES Reference : 0x%X\n", srds_s1);
+
+ /* select SGMII*/
+ if (srds_s1 == 0x86)
+ CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
+ MISC_CTL_SG_SEL);
+
+ /* select SGMII and Aurora*/
+ if (srds_s1 == 0x8E)
+ CPLD_WRITE(misc_ctl_status, CPLD_READ(misc_ctl_status) |
+ MISC_CTL_SG_SEL | MISC_CTL_AURORA_SEL);
+
+#if defined(CONFIG_T1040D4RDB)
+ /* Mask all CPLD interrupt sources, except QSGMII interrupts */
+ if (CPLD_READ(sw_ver) < 0x03) {
+ debug("CPLD SW version 0x%02x doesn't support int_mask\n",
+ CPLD_READ(sw_ver));
+ } else {
+ CPLD_WRITE(int_mask, CPLD_INT_MASK_ALL &
+ ~(CPLD_INT_MASK_QSGMII1 | CPLD_INT_MASK_QSGMII2));
+ }
+#endif
+
return 0;
}
diff --git a/board/freescale/t4rdb/cpld.c b/board/freescale/t4rdb/cpld.c
index d5f3812872fb72986d63367ed662920d1e6266ff..d563d0d35ce1def903013922dec2800f3fdee994 100644
--- a/board/freescale/t4rdb/cpld.c
+++ b/board/freescale/t4rdb/cpld.c
@@ -47,14 +47,8 @@ void cpld_set_altbank(void)
switch (curbank) {
case CPLD_SELECT_BANK0:
- altbank = CPLD_SELECT_BANK4;
- CPLD_WRITE(vbank, altbank);
- override = CPLD_READ(software_on);
- CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN);
- CPLD_WRITE(sys_reset, CPLD_SYSTEM_RESET);
- break;
case CPLD_SELECT_BANK4:
- altbank = CPLD_SELECT_BANK0;
+ altbank = CPLD_SELECT_BANK4;
CPLD_WRITE(vbank, altbank);
override = CPLD_READ(software_on);
CPLD_WRITE(software_on, override | CPLD_BANK_SEL_EN);
diff --git a/configs/P3041DS_NAND_SECURE_BOOT_defconfig b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..2f18bc1777531290915f25c10be0d8567999b860
--- /dev/null
+++ b/configs/P3041DS_NAND_SECURE_BOOT_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P3041DS=y
+CONFIG_SPI_FLASH=y
diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..98cdd35f9298ed2ea52a97e519d3442b2f23f8c0
--- /dev/null
+++ b/configs/P5020DS_NAND_SECURE_BOOT_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P5020DS=y
+CONFIG_SPI_FLASH=y
diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..a6cc7c465ebf51e85bb9bb6c5c286192f36b53e5
--- /dev/null
+++ b/configs/P5040DS_NAND_SECURE_BOOT_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_P5040DS=y
+CONFIG_SPI_FLASH=y
diff --git a/configs/T1040D4RDB_NAND_defconfig b/configs/T1040D4RDB_NAND_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..3051f0c1be0925a67042f209133b23719f9625b6
--- /dev/null
+++ b/configs/T1040D4RDB_NAND_defconfig
@@ -0,0 +1,6 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y
+CONFIG_SPI_FLASH=y
diff --git a/configs/T1040D4RDB_SDCARD_defconfig b/configs/T1040D4RDB_SDCARD_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..6c10c50bf9d1a319eb00467cab1a0c567bf6cd3b
--- /dev/null
+++ b/configs/T1040D4RDB_SDCARD_defconfig
@@ -0,0 +1,6 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y
+CONFIG_SPI_FLASH=y
diff --git a/configs/T1040D4RDB_SECURE_BOOT_defconfig b/configs/T1040D4RDB_SECURE_BOOT_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..f779126058f1baba9b2fe31e4adfb24e9072ee13
--- /dev/null
+++ b/configs/T1040D4RDB_SECURE_BOOT_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y
+CONFIG_SPI_FLASH=y
diff --git a/configs/T1040D4RDB_SPIFLASH_defconfig b/configs/T1040D4RDB_SPIFLASH_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..6614e345b32543d7dfb4e7a75713c7a61fb6dd97
--- /dev/null
+++ b/configs/T1040D4RDB_SPIFLASH_defconfig
@@ -0,0 +1,6 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y
+CONFIG_SPI_FLASH=y
diff --git a/configs/T1040D4RDB_defconfig b/configs/T1040D4RDB_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..ce0cfa339a0bd338b9a663ffa57657569dc5f14b
--- /dev/null
+++ b/configs/T1040D4RDB_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y
+CONFIG_SPI_FLASH=y
diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..fa4c250009e27a01cdba24dd6abc2b7e1b2abc4d
--- /dev/null
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -0,0 +1,6 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y
+CONFIG_SPI_FLASH=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..12644d614812717b9090b9d0058db277befb4107
--- /dev/null
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -0,0 +1,6 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y
+CONFIG_SPI_FLASH=y
diff --git a/configs/T1042D4RDB_SECURE_BOOT_defconfig b/configs/T1042D4RDB_SECURE_BOOT_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..e8065915f1ee80295655923c9c5d8a34613846f9
--- /dev/null
+++ b/configs/T1042D4RDB_SECURE_BOOT_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y
+CONFIG_SPI_FLASH=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..2504499ba7fd6b72e68a5937bef315881547c36c
--- /dev/null
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -0,0 +1,6 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y
+CONFIG_SPI_FLASH=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..3df74966feea399919fb4fa73ed1b131002e8ab3
--- /dev/null
+++ b/configs/T1042D4RDB_defconfig
@@ -0,0 +1,5 @@
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T104XRDB=y
+CONFIG_SPI_FLASH=y
diff --git a/doc/README.b4860qds b/doc/README.b4860qds
index eada0c7dd89b55d7be39bc500c241dd491e6eaa4..6fcc3bd6e8ae4b4c6a99f9c6b5bcf39ad920c131 100644
--- a/doc/README.b4860qds
+++ b/doc/README.b4860qds
@@ -119,7 +119,7 @@ B4860QDS Default Settings
Switch Settings
----------------
-SW1 OFF [0] OFF [1] OFF [1] OFF [0] OFF [1] OFF [0] OFF [1] OFF [1]
+SW1 OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0]
SW2 ON ON ON ON ON ON OFF OFF
SW3 OFF OFF OFF ON OFF OFF ON OFF
SW5 OFF OFF OFF OFF OFF OFF ON ON
diff --git a/include/config_fsl_secboot.h b/include/config_fsl_secboot.h
index 050b15790211992a29c64cbd51a3b2c783e0bd24..fc6788a7a614aced44fc38f7a937832ccb517533 100644
--- a/include/config_fsl_secboot.h
+++ b/include/config_fsl_secboot.h
@@ -55,6 +55,22 @@
/* For secure boot flow, default environment used will be used */
#if defined(CONFIG_SYS_RAMBOOT)
+#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
+#define CONFIG_BS_COPY_ENV \
+ "setenv bs_hdr_ram " __stringify(CONFIG_BS_HDR_ADDR_RAM)";" \
+ "setenv bs_hdr_flash " __stringify(CONFIG_BS_HDR_ADDR_FLASH)";" \
+ "setenv bs_hdr_size " __stringify(CONFIG_BS_HDR_SIZE)";" \
+ "setenv bs_ram " __stringify(CONFIG_BS_ADDR_RAM)";" \
+ "setenv bs_flash " __stringify(CONFIG_BS_ADDR_FLASH)";" \
+ "setenv bs_size " __stringify(CONFIG_BS_SIZE)";"
+
+#if defined(CONFIG_RAMBOOT_NAND)
+#define CONFIG_BS_COPY_CMD \
+ "nand read $bs_hdr_ram $bs_hdr_flash $bs_hdr_size ;" \
+ "nand read $bs_ram $bs_flash $bs_size ;"
+#endif /* CONFIG_RAMBOOT_NAND */
+#endif /* CONFIG_BOOTSCRIPT_COPY_RAM */
+
#if defined(CONFIG_RAMBOOT_SPIFLASH)
#undef CONFIG_ENV_IS_IN_SPI_FLASH
#elif defined(CONFIG_RAMBOOT_NAND)
@@ -68,6 +84,17 @@
#define CONFIG_ENV_IS_NOWHERE
+#ifndef CONFIG_BS_COPY_ENV
+#define CONFIG_BS_COPY_ENV
+#endif
+
+#ifndef CONFIG_BS_COPY_CMD
+#define CONFIG_BS_COPY_CMD
+#endif
+
+#define CONFIG_SECBOOT_CMD CONFIG_BS_COPY_ENV \
+ CONFIG_BS_COPY_CMD \
+ CONFIG_SECBOOT
/*
* We don't want boot delay for secure boot flow
* before autoboot starts
@@ -75,7 +102,7 @@
#undef CONFIG_BOOTDELAY
#define CONFIG_BOOTDELAY 0
#undef CONFIG_BOOTCOMMAND
-#define CONFIG_BOOTCOMMAND CONFIG_SECBOOT
+#define CONFIG_BOOTCOMMAND CONFIG_SECBOOT_CMD
/*
* CONFIG_ZERO_BOOTDELAY_CHECK should not be defined for
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index f99663a65ba095aeaa33f21aed2684ed37541652..bde71fbca35c47b6754b8ca41caef918dc8c6329 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -11,12 +11,6 @@
#ifndef __T1024RDB_H
#define __T1024RDB_H
-#if defined(CONFIG_T1023RDB)
-#ifdef CONFIG_SPL
-#define CONFIG_SYS_NO_FLASH
-#endif
-#endif
-
/* High Level Configuration Options */
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO
@@ -320,7 +314,7 @@ unsigned long get_board_ddr_clk(void);
#if defined(CONFIG_T1024RDB)
#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
#elif defined(CONFIG_T1023RDB)
-#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
+#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \
CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
#endif
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
@@ -395,7 +389,9 @@ unsigned long get_board_ddr_clk(void);
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
#elif defined(CONFIG_T1023RDB)
-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
+ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
+ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
| CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
@@ -557,9 +553,8 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
-#define I2C_MUX_PCA_ADDR 0x77
-#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
-
+#define I2C_PCA6408_BUS_NUM 1
+#define I2C_PCA6408_ADDR 0x20
/* I2C bus multiplexer */
#define I2C_MUX_CH_DEFAULT 0x8
@@ -757,8 +752,10 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_DPAA_FMAN
+#ifdef CONFIG_T1024RDB
#define CONFIG_QE
#define CONFIG_U_QE
+#endif
/* Default address of microcode for the Linux FMan driver */
#if defined(CONFIG_SPIFLASH)
/*
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 16d2e0e1c7d69328c7723850c182aa2e794e5e7d..e88cad678afceadef8f18faa226ec7588e1d57cb 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -29,6 +29,14 @@
#ifdef CONFIG_T1042RDB
#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1042_rcw.cfg
#endif
+#ifdef CONFIG_T1040D4RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1040d4_rcw.cfg
+#endif
+#ifdef CONFIG_T1042D4RDB
+#define CONFIG_SYS_FSL_PBL_RCW \
+$(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg
+#endif
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
@@ -220,7 +228,9 @@
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_DDR_SPD
+#ifndef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_FSL_DDR3
+#endif
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x51
@@ -278,8 +288,23 @@
#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
#define CPLD_LBMAP_RESET 0xFF
#define CPLD_LBMAP_SHIFT 0x03
-#ifdef CONFIG_T1042RDB_PI
+
+#if defined(CONFIG_T1042RDB_PI)
#define CPLD_DIU_SEL_DFP 0x80
+#elif defined(CONFIG_T1042D4RDB)
+#define CPLD_DIU_SEL_DFP 0xc0
+#endif
+
+#if defined(CONFIG_T1040D4RDB)
+#define CPLD_INT_MASK_ALL 0xFF
+#define CPLD_INT_MASK_THERM 0x80
+#define CPLD_INT_MASK_DVI_DFP 0x40
+#define CPLD_INT_MASK_QSGMII1 0x20
+#define CPLD_INT_MASK_QSGMII2 0x10
+#define CPLD_INT_MASK_SGMI1 0x08
+#define CPLD_INT_MASK_SGMI2 0x04
+#define CPLD_INT_MASK_TDMR1 0x02
+#define CPLD_INT_MASK_TDMR2 0x01
#endif
#define CONFIG_SYS_CPLD_BASE 0xffdf0000
@@ -447,7 +472,7 @@
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#ifdef CONFIG_T1042RDB_PI
+#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB)
/* Video */
#define CONFIG_FSL_DIU_FB
@@ -492,11 +517,11 @@
/* I2C bus multiplexer */
#define I2C_MUX_PCA_ADDR 0x70
-#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
+#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
#define I2C_MUX_CH_DEFAULT 0x8
#endif
-#ifdef CONFIG_T1042RDB_PI
+#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB)
/* LDI/DVI Encoder for display */
#define CONFIG_SYS_I2C_LDI_ADDR 0x38
#define CONFIG_SYS_I2C_DVI_ADDR 0x75
@@ -664,7 +689,7 @@
#define CONFIG_SYS_DPAA_FMAN
#define CONFIG_SYS_DPAA_PME
-#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
+#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
#define CONFIG_QE
#define CONFIG_U_QE
#endif
@@ -693,7 +718,7 @@
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
#endif
-#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
+#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
#if defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_QE_FW_ADDR 0x130000
#elif defined(CONFIG_SDCARD)
@@ -718,17 +743,32 @@
#ifdef CONFIG_FMAN_ENET
#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
-#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
+#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
+#elif defined(CONFIG_T1040D4RDB) || defined(CONFIG_T1042D4RDB)
+#define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
+#define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
+#define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
+#endif
+
+#ifdef CONFIG_T104XD4RDB
+#define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
+#define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
+#else
+#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
+#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
#endif
-#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
-#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
/* Enable VSC9953 L2 Switch driver on T1040 SoC */
-#ifdef CONFIG_T1040RDB
+#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB)
#define CONFIG_VSC9953
#define CONFIG_VSC9953_CMD
+#ifdef CONFIG_T1040RDB
#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
+#else
+#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
+#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
+#endif
#endif
#define CONFIG_MII /* MII PHY management */
@@ -836,6 +876,10 @@
#define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
#elif defined(CONFIG_T1042RDB)
#define FDTFILE "t1042rdb/t1042rdb.dtb"
+#elif defined(CONFIG_T1040D4RDB)
+#define FDTFILE "t1042rdb/t1040d4rdb.dtb"
+#elif defined(CONFIG_T1042D4RDB)
+#define FDTFILE "t1042rdb/t1042d4rdb.dtb"
#endif
#ifdef CONFIG_FSL_DIU_FB
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 88750e057e8fd0a4834f2fe1de10d52d2fd8996e..9aaa0f533b8f96d602076a82a198f77345da056d 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -16,6 +16,14 @@
#include "../board/freescale/common/ics307_clk.h"
#ifdef CONFIG_RAMBOOT_PBL
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
+#ifdef CONFIG_NAND
+#define CONFIG_RAMBOOT_NAND
+#endif
+#define CONFIG_BOOTSCRIPT_COPY_RAM
+#else
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
@@ -29,6 +37,7 @@
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg
#endif
#endif
+#endif
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/* Set 1M boot space */