diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c b/drivers/clk/renesas/r8a7792-cpg-mssr.c
index 260bb892d607c628824f219ff7a1c172fde9f69e..4ba18b18beaf40850b6654cbcce0a672c4b87a15 100644
--- a/drivers/clk/renesas/r8a7792-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c
@@ -39,7 +39,7 @@ enum clk_ids {
 	MOD_CLK_BASE
 };
 
-static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
+static const struct cpg_core_clk r8a7792_core_clks[] = {
 	/* External Clock Inputs */
 	DEF_INPUT("extal",     CLK_EXTAL),
 
@@ -78,7 +78,7 @@ static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
 	DEF_FIXED("osc",    R8A7792_CLK_OSC,   CLK_PLL1,      12288, 1),
 };
 
-static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = {
+static const struct mssr_mod_clk r8a7792_mod_clks[] = {
 	DEF_MOD("msiof0",		   0,	R8A7792_CLK_MP),
 	DEF_MOD("jpu",			 106,	R8A7792_CLK_M2),
 	DEF_MOD("tmu1",			 111,	R8A7792_CLK_P),
@@ -152,10 +152,6 @@ static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = {
 	DEF_MOD("ssi3",			1012,	MOD_CLK_ID(1005)),
 };
 
-static const unsigned int r8a7792_crit_mod_clks[] __initconst = {
-	MOD_CLK_ID(408),	/* INTC-SYS (GIC) */
-};
-
 /*
  * CPG Clock Data
  */
@@ -179,7 +175,7 @@ static const unsigned int r8a7792_crit_mod_clks[] __initconst = {
 #define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 12) | \
 					 (((md) & BIT(13)) >> 12) | \
 					 (((md) & BIT(19)) >> 19))
-static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = {
 	{ 1, 208, 106, 200 },
 	{ 1, 208,  88, 200 },
 	{ 1, 156,  80, 150 },