diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c
index de7503c015233eca9cf5aa3466055fb9d915a1a5..e4b07d0744774e857770ef52b76aa301bfe98b38 100644
--- a/arch/arm/cpu/arm1136/mx35/generic.c
+++ b/arch/arm/cpu/arm1136/mx35/generic.c
@@ -174,17 +174,14 @@ static u32 get_ipg_per_clk(void)
u32 pdr4 = readl(&ccm->pdr4);
u32 div;
if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
- div = (CCM_GET_DIVIDER(pdr4,
- MXC_CCM_PDR4_PER0_PRDF_MASK,
- MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1) *
- (CCM_GET_DIVIDER(pdr4,
+ div = CCM_GET_DIVIDER(pdr4,
MXC_CCM_PDR4_PER0_PODF_MASK,
- MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1);
+ MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;
} else {
div = CCM_GET_DIVIDER(pdr0,
MXC_CCM_PDR0_PER_PODF_MASK,
MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
- freq /= get_ahb_div(pdr0);
+ div *= get_ahb_div(pdr0);
}
return freq / div;
}
@@ -202,19 +199,16 @@ u32 imx_get_uartclk(void)
freq = decode_pll(readl(&ccm->ppctl),
CONFIG_MX35_HCLK_FREQ);
}
- freq /= ((CCM_GET_DIVIDER(pdr4,
- MXC_CCM_PDR4_UART_PRDF_MASK,
- MXC_CCM_PDR4_UART_PRDF_OFFSET) + 1) *
- (CCM_GET_DIVIDER(pdr4,
+ freq /= CCM_GET_DIVIDER(pdr4,
MXC_CCM_PDR4_UART_PODF_MASK,
- MXC_CCM_PDR4_UART_PODF_OFFSET) + 1));
+ MXC_CCM_PDR4_UART_PODF_OFFSET) + 1;
return freq;
}
unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
{
u32 nfc_pdf, hsp_podf;
- u32 pll, ret_val = 0, usb_prdf, usb_podf;
+ u32 pll, ret_val = 0, usb_podf;
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
@@ -258,8 +252,7 @@ unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
ret_val = pll / (nfc_pdf + 1);
break;
case USB_CLK:
- usb_prdf = (reg4 >> 25) & 0x7;
- usb_podf = (reg4 >> 22) & 0x7;
+ usb_podf = (reg4 >> 22) & 0x3F;
if (reg4 & 0x200) {
pll = get_mcu_main_clk();
} else {
@@ -267,7 +260,7 @@ unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
CONFIG_MX35_HCLK_FREQ);
}
- ret_val = pll / ((usb_prdf + 1) * (usb_podf + 1));
+ ret_val = pll / (usb_podf + 1);
break;
default:
printf("Unknown clock: %d\n", clk);
@@ -290,11 +283,10 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
case UART2_BAUD:
case UART3_BAUD:
clk_sel = mpdr3 & (1 << 14);
- pre_pdf = (mpdr4 >> 13) & 0x7;
- pdf = (mpdr4 >> 10) & 0x7;
+ pdf = (mpdr4 >> 10) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
- ((pre_pdf + 1) * (pdf + 1));
+ (pdf + 1);
break;
case SSI1_BAUD:
pre_pdf = (mpdr2 >> 24) & 0x7;
@@ -314,11 +306,10 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
break;
case CSI_BAUD:
clk_sel = mpdr2 & (1 << 7);
- pre_pdf = (mpdr2 >> 16) & 0x7;
- pdf = (mpdr2 >> 19) & 0x7;
+ pdf = (mpdr2 >> 16) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
- ((pre_pdf + 1) * (pdf + 1));
+ (pdf + 1);
break;
case MSHC_CLK:
pre_pdf = readl(&ccm->pdr1);
@@ -331,27 +322,24 @@ unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
break;
case ESDHC1_CLK:
clk_sel = mpdr3 & 0x40;
- pre_pdf = mpdr3 & 0x7;
- pdf = (mpdr3>>3) & 0x7;
+ pdf = mpdr3 & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
- ((pre_pdf + 1) * (pdf + 1));
+ (pdf + 1);
break;
case ESDHC2_CLK:
clk_sel = mpdr3 & 0x40;
- pre_pdf = (mpdr3 >> 8) & 0x7;
- pdf = (mpdr3 >> 11) & 0x7;
+ pdf = (mpdr3 >> 8) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
- ((pre_pdf + 1) * (pdf + 1));
+ (pdf + 1);
break;
case ESDHC3_CLK:
clk_sel = mpdr3 & 0x40;
- pre_pdf = (mpdr3 >> 16) & 0x7;
- pdf = (mpdr3 >> 19) & 0x7;
+ pdf = (mpdr3 >> 16) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
- ((pre_pdf + 1) * (pdf + 1));
+ (pdf + 1);
break;
case SPDIF_CLK:
clk_sel = mpdr3 & 0x400000;
diff --git a/arch/arm/include/asm/arch-mx35/crm_regs.h b/arch/arm/include/asm/arch-mx35/crm_regs.h
index fa71dead30088716aea80c18b29bc773f8ffe787..3fcde0ba52511fe9fc409a5745ba2a80f78b14ab 100644
--- a/arch/arm/include/asm/arch-mx35/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx35/crm_regs.h
@@ -32,8 +32,8 @@
#define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20)
#define MXC_CCM_CCMR_ROMW_OFFSET 18
#define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18)
-#define MXC_CCM_CCMR_RAMW_OFFSET 21
-#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 21)
+#define MXC_CCM_CCMR_RAMW_OFFSET 16
+#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 16)
#define MXC_CCM_CCMR_LPM_OFFSET 14
#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14)
#define MXC_CCM_CCMR_UPE (1 << 9)
@@ -47,7 +47,7 @@
#define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16)
#define MXC_CCM_PDR0_CKIL_SEL (1 << 15)
#define MXC_CCM_PDR0_PER_PODF_OFFSET 12
-#define MXC_CCM_PDR0_PER_PODF_MASK (0xF << 12)
+#define MXC_CCM_PDR0_PER_PODF_MASK (0x7 << 12)
#define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET 9
#define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9)
#define MXC_CCM_PDR0_AUTO_CON 0x1
@@ -62,10 +62,8 @@
#define MXC_CCM_PDR2_SSI2_PRDF_MASK (0x7 << 27)
#define MXC_CCM_PDR2_SSI1_PRDF_OFFSET 24
#define MXC_CCM_PDR2_SSI1_PRDF_MASK (0x7 << 24)
-#define MXC_CCM_PDR2_CSI_PRDF_OFFSET 19
-#define MXC_CCM_PDR2_CSI_PRDF_MASK (0x7 << 19)
#define MXC_CCM_PDR2_CSI_PODF_OFFSET 16
-#define MXC_CCM_PDR2_CSI_PODF_MASK (0x7 << 16)
+#define MXC_CCM_PDR2_CSI_PODF_MASK (0x3F << 16)
#define MXC_CCM_PDR2_SSI2_PODF_OFFSET 8
#define MXC_CCM_PDR2_SSI2_PODF_MASK (0x3F << 8)
#define MXC_CCM_PDR2_CSI_M_U (1 << 7)
@@ -78,35 +76,23 @@
#define MXC_CCM_PDR3_SPDIF_PODF_OFFSET 23
#define MXC_CCM_PDR3_SPDIF_PODF_MASK (0x3F << 23)
#define MXC_CCM_PDR3_SPDIF_M_U (1 << 22)
-#define MXC_CCM_PDR3_ESDHC3_PRDF_OFFSET 19
-#define MXC_CCM_PDR3_ESDHC3_PRDF_MASK (0x7 << 19)
#define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET 16
-#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x7 << 16)
-#define MXC_CCM_PDR3_UART_M_U (1 << 15)
-#define MXC_CCM_PDR3_ESDHC2_PRDF_OFFSET 11
-#define MXC_CCM_PDR3_ESDHC2_PRDF_MASK (0x7 << 11)
+#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x3F << 16)
+#define MXC_CCM_PDR3_UART_M_U (1 << 14)
#define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET 8
-#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x7 << 8)
+#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x3F << 8)
#define MXC_CCM_PDR3_ESDHC_M_U (1 << 6)
-#define MXC_CCM_PDR3_ESDHC1_PRDF_OFFSET 3
-#define MXC_CCM_PDR3_ESDHC1_PRDF_MASK (0x7 << 3)
#define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET 0
-#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x7)
+#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x3F)
#define MXC_CCM_PDR4_NFC_PODF_OFFSET 28
#define MXC_CCM_PDR4_NFC_PODF_MASK (0xF << 28)
-#define MXC_CCM_PDR4_USB_PRDF_OFFSET 25
-#define MXC_CCM_PDR4_USB_PRDF_MASK (0x7 << 25)
#define MXC_CCM_PDR4_USB_PODF_OFFSET 22
-#define MXC_CCM_PDR4_USB_PODF_MASK (0x7 << 22)
-#define MXC_CCM_PDR4_PER0_PRDF_OFFSET 19
-#define MXC_CCM_PDR4_PER0_PRDF_MASK (0x7 << 19)
+#define MXC_CCM_PDR4_USB_PODF_MASK (0x3F << 22)
#define MXC_CCM_PDR4_PER0_PODF_OFFSET 16
-#define MXC_CCM_PDR4_PER0_PODF_MASK (0x7 << 16)
-#define MXC_CCM_PDR4_UART_PRDF_OFFSET 13
-#define MXC_CCM_PDR4_UART_PRDF_MASK (0x7 << 13)
+#define MXC_CCM_PDR4_PER0_PODF_MASK (0x3F << 16)
#define MXC_CCM_PDR4_UART_PODF_OFFSET 10
-#define MXC_CCM_PDR4_UART_PODF_MASK (0x7 << 10)
+#define MXC_CCM_PDR4_UART_PODF_MASK (0x3F << 10)
#define MXC_CCM_PDR4_USB_M_U (1 << 9)
/* Bit definitions for RCSR */
@@ -257,10 +243,8 @@
#define MXC_CCM_COSR_CLKOSEL_OFFSET 0
#define MXC_CCM_COSR_CLKOEN (1 << 5)
#define MXC_CCM_COSR_CLKOUTDIV_1 (1 << 6)
-#define MXC_CCM_COSR_CLKOUT_PREDIV_MASK (0x7 << 10)
-#define MXC_CCM_COSR_CLKOUT_PREDIV_OFFSET 10
-#define MXC_CCM_COSR_CLKOUT_PRODIV_MASK (0x7 << 13)
-#define MXC_CCM_COSR_CLKOUT_PRODIV_OFFSET 13
+#define MXC_CCM_COSR_CLKOUT_DIV_MASK (0x3F << 10)
+#define MXC_CCM_COSR_CLKOUT_DIV_OFFSET 10
#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK (0x3 << 16)
#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET 16
#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK (0x3 << 18)