diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 43a93ac272b8ea71ac9b7ee670bb30434efc509b..50f444c80024dbd324e84f64fe986471b8897b31 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -119,17 +119,14 @@ struct esdhc_soc_data {
  * @wp_gpio: gpio for write protection
  */
 struct fsl_esdhc_priv {
-	struct fsl_esdhc *esdhc_regs;
-	unsigned int sdhc_clk;
+	struct fsl_esdhc_cfg c;
 	unsigned int clock;
 	unsigned int mode;
-	unsigned int bus_width;
 #if !CONFIG_IS_ENABLED(BLK)
 	struct mmc *mmc;
 #endif
 	struct udevice *dev;
 	int non_removable;
-	int wp_enable;
 	int vs18_enable;
 	u32 flags;
 	u32 caps;
@@ -194,7 +191,7 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
 				 struct mmc_data *data)
 {
-	struct fsl_esdhc *regs = priv->esdhc_regs;
+	struct fsl_esdhc *regs = priv->c.esdhc_regs;
 	uint blocks;
 	char *buffer;
 	uint databuf;
@@ -256,7 +253,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
 			    struct mmc_data *data)
 {
 	int timeout;
-	struct fsl_esdhc *regs = priv->esdhc_regs;
+	struct fsl_esdhc *regs = priv->c.esdhc_regs;
 #if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
 	defined(CONFIG_MX8M)
 	dma_addr_t addr;
@@ -291,7 +288,7 @@ static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
 		if (wml_value > WML_WR_WML_MAX)
 			wml_value = WML_WR_WML_MAX_VAL;
 #ifndef CONFIG_SYS_FSL_ESDHC_GPIO_WP
-		if (priv->wp_enable) {
+		if (priv->c.wp_enable) {
 			if ((esdhc_read32(&regs->prsstat) &
 			    PRSSTAT_WPSPL) == 0) {
 				printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
@@ -395,7 +392,7 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
 	uint	xfertyp;
 	uint	irqstat;
 	u32	flags = IRQSTAT_CC | IRQSTAT_CTOE;
-	struct fsl_esdhc *regs = priv->esdhc_regs;
+	struct fsl_esdhc *regs = priv->c.esdhc_regs;
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
 	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
@@ -579,7 +576,7 @@ out:
 
 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
 {
-	struct fsl_esdhc *regs = priv->esdhc_regs;
+	struct fsl_esdhc *regs = priv->c.esdhc_regs;
 	int div = 1;
 #ifdef ARCH_MXC
 #ifdef CONFIG_MX53
@@ -592,7 +589,7 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
 	int pre_div = 2;
 #endif
 	int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
-	int sdhc_clk = priv->sdhc_clk;
+	int sdhc_clk = priv->c.sdhc_clk;
 	uint clk;
 
 	if (clock < mmc->cfg->f_min)
@@ -631,7 +628,7 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
 {
-	struct fsl_esdhc *regs = priv->esdhc_regs;
+	struct fsl_esdhc *regs = priv->c.esdhc_regs;
 	u32 value;
 	u32 time_out;
 
@@ -888,7 +885,7 @@ static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
 
 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
 {
-	struct fsl_esdhc *regs = priv->esdhc_regs;
+	struct fsl_esdhc *regs = priv->c.esdhc_regs;
 	int ret __maybe_unused;
 
 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
@@ -947,7 +944,7 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
 
 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
 {
-	struct fsl_esdhc *regs = priv->esdhc_regs;
+	struct fsl_esdhc *regs = priv->c.esdhc_regs;
 	ulong start;
 
 	/* Reset the entire host controller */
@@ -1006,7 +1003,7 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
 
 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
 {
-	struct fsl_esdhc *regs = priv->esdhc_regs;
+	struct fsl_esdhc *regs = priv->c.esdhc_regs;
 	int timeout = 1000;
 
 #ifdef CONFIG_ESDHC_DETECT_QUIRK
@@ -1097,7 +1094,7 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
 	if (!priv)
 		return -EINVAL;
 
-	regs = priv->esdhc_regs;
+	regs = priv->c.esdhc_regs;
 
 	/* First reset the eSDHC controller */
 	ret = esdhc_reset(regs);
@@ -1159,9 +1156,9 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
 		return -1;
 	}
 
-	if (priv->bus_width == 8)
+	if (priv->c.bus_width == 8)
 		cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
-	else if (priv->bus_width == 4)
+	else if (priv->c.bus_width == 4)
 		cfg->host_caps = MMC_MODE_4BIT;
 
 	cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
@@ -1169,10 +1166,10 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
 	cfg->host_caps |= MMC_MODE_DDR_52MHz;
 #endif
 
-	if (priv->bus_width > 0) {
-		if (priv->bus_width < 8)
+	if (priv->c.bus_width > 0) {
+		if (priv->c.bus_width < 8)
 			cfg->host_caps &= ~MMC_MODE_8BIT;
-		if (priv->bus_width < 4)
+		if (priv->c.bus_width < 4)
 			cfg->host_caps &= ~MMC_MODE_4BIT;
 	}
 
@@ -1187,7 +1184,7 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
 	cfg->host_caps |= priv->caps;
 
 	cfg->f_min = 400000;
-	cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
+	cfg->f_max = min(priv->c.sdhc_clk, (u32)200000000);
 
 	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 
@@ -1215,12 +1212,8 @@ static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
 	if (!cfg || !priv)
 		return -EINVAL;
 
-	priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
-	priv->bus_width = cfg->max_bus_width;
-	priv->sdhc_clk = cfg->sdhc_clk;
-	priv->wp_enable  = cfg->wp_enable;
-	priv->vs18_enable  = cfg->vs18_enable;
-
+	priv->c = *cfg;
+	priv->c.esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
 	return 0;
 };
 
@@ -1379,7 +1372,7 @@ static int fsl_esdhc_probe(struct udevice *dev)
 	if (addr == FDT_ADDR_T_NONE)
 		return -EINVAL;
 
-	priv->esdhc_regs = (struct fsl_esdhc *)addr;
+	priv->c.esdhc_regs = (struct fsl_esdhc *)addr;
 	priv->dev = dev;
 	priv->mode = -1;
 	if (data) {
@@ -1389,11 +1382,11 @@ static int fsl_esdhc_probe(struct udevice *dev)
 
 	val = dev_read_u32_default(dev, "bus-width", -1);
 	if (val == 8)
-		priv->bus_width = 8;
+		priv->c.bus_width = 8;
 	else if (val == 4)
-		priv->bus_width = 4;
+		priv->c.bus_width = 4;
 	else
-		priv->bus_width = 1;
+		priv->c.bus_width = 1;
 
 	val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
 	priv->tuning_step = val;
@@ -1414,13 +1407,13 @@ static int fsl_esdhc_probe(struct udevice *dev)
 #endif
 	}
 
-	priv->wp_enable = 1;
+	priv->c.wp_enable = 1;
 
 #ifdef CONFIG_DM_GPIO
 	ret = gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
 				   GPIOD_IS_IN);
 	if (ret)
-		priv->wp_enable = 0;
+		priv->c.wp_enable = 0;
 	gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset_gpio,
 			     GPIOD_IS_OUT_ACTIVE);
 #endif
@@ -1472,8 +1465,8 @@ static int fsl_esdhc_probe(struct udevice *dev)
 
 	init_clk_usdhc(dev->seq);
 
-	priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
-	if (priv->sdhc_clk <= 0) {
+	priv->c.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
+	if (priv->c.sdhc_clk <= 0) {
 		dev_err(dev, "Unable to get clk for %s\n", dev->name);
 		return -EINVAL;
 	}
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index acd8dd06f87a55501c37b866509711a53fe2ad74..969e41b6958e9374318a4f1da405d1d9646a1a23 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -220,12 +220,17 @@
 #define	ESDHC_FLAG_HS400_ES		BIT(11)
 
 struct fsl_esdhc_cfg {
-	phys_addr_t esdhc_base;
+	union
+	{
+		phys_addr_t esdhc_base;
+		struct fsl_esdhc *esdhc_regs;
+	};
 	u32	sdhc_clk;
-	u8	max_bus_width;
-	int	wp_enable;
+	u8	bus_width;
+	u8	wp_enable;
+	u16	gp_cd;
+	u16	gp_reset;
 	int	vs18_enable; /* Use 1.8V if set to 1 */
-	struct mmc_config cfg;
 };
 
 /* Select the correct accessors depending on endianess */